llvm/test/CodeGen/RISCV/rvp-insert-subvector.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=riscv32 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32
; RUN: llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64

define <8 x i8> @insert_zero_v4i8(<4 x i8> %v) {
; RV32-LABEL: insert_zero_v4i8:
; RV32:       # %bb.0:
; RV32-NEXT:    li a1, 0
; RV32-NEXT:    ret
;
; RV64-LABEL: insert_zero_v4i8:
; RV64:       # %bb.0:
; RV64-NEXT:    zext.w a0, a0
; RV64-NEXT:    ret
  %r = call <8 x i8> @llvm.vector.insert.v8i8.v4i8(<8 x i8> zeroinitializer, <4 x i8> %v, i64 0)
  ret <8 x i8> %r
}

define <4 x i16> @insert_zero_v2i16(<2 x i16> %v) {
; RV32-LABEL: insert_zero_v2i16:
; RV32:       # %bb.0:
; RV32-NEXT:    li a1, 0
; RV32-NEXT:    ret
;
; RV64-LABEL: insert_zero_v2i16:
; RV64:       # %bb.0:
; RV64-NEXT:    zext.w a0, a0
; RV64-NEXT:    ret
  %r = call <4 x i16> @llvm.vector.insert.v4i16.v2i16(<4 x i16> zeroinitializer, <2 x i16> %v, i64 0)
  ret <4 x i16> %r
}

define <2 x i32> @insert_zero_v1i32(<1 x i32> %v) {
; RV32-LABEL: insert_zero_v1i32:
; RV32:       # %bb.0:
; RV32-NEXT:    li a1, 0
; RV32-NEXT:    ret
;
; RV64-LABEL: insert_zero_v1i32:
; RV64:       # %bb.0:
; RV64-NEXT:    pack a0, a0, zero
; RV64-NEXT:    ret
  %r = call <2 x i32> @llvm.vector.insert.v2i32.v1i32(<2 x i32> zeroinitializer, <1 x i32> %v, i64 0)
  ret <2 x i32> %r
}