llvm/test/CodeGen/ARM/load-store-pair-volatile.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=arm-none-eabi -stop-after=finalize-isel < %s | FileCheck %s

define void @test(ptr %vol_one, ptr %p_in, ptr %p_out, i32 %n) {
  ; CHECK-LABEL: name: test
  ; CHECK: bb.0.entry:
  ; CHECK-NEXT:   liveins: $r0, $r1, $r2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $r2
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $r1
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr = COPY $r0
  ; CHECK-NEXT:   [[LDRi12_:%[0-9]+]]:gpr = LDRi12 [[COPY1]], 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.p_in)
  ; CHECK-NEXT:   STRi12 killed [[LDRi12_]], [[COPY2]], 0, 14 /* CC::al */, $noreg :: (volatile store (s32) into %ir.vol_one)
  ; CHECK-NEXT:   [[LDRi12_1:%[0-9]+]]:gpr = LDRi12 [[COPY2]], 4, 14 /* CC::al */, $noreg :: (volatile load (s32) from %ir.vol_two)
  ; CHECK-NEXT:   STRi12 killed [[LDRi12_1]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.p_out)
  ; CHECK-NEXT:   MOVPCLR 14 /* CC::al */, $noreg
entry:
  %vol_two = getelementptr inbounds i8, ptr %vol_one, i32 4
  %a = load float, ptr %p_in, align 4
  store volatile float %a, ptr %vol_one, align 4
  %b = load volatile float, ptr %vol_two, align 4
  store float %b, ptr %p_out, align 4
  ret void
}