llvm/test/CodeGen/AMDGPU/scmp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel=0 -mtriple=amdgpu7.00 < %s | FileCheck -check-prefix=GFX7-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgpu7.00 < %s | FileCheck -check-prefix=GFX7-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu12.00 < %s | FileCheck -check-prefix=GFX12-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgpu12.00 < %s | FileCheck -check-prefix=GFX12-GISEL %s

define i32 @scmp_i128(i128 %a, i128 %b) {
; GFX7-SDAG-LABEL: scmp_i128:
; GFX7-SDAG:       ; %bb.0:
; GFX7-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-SDAG-NEXT:    v_cmp_gt_u64_e32 vcc, v[0:1], v[4:5]
; GFX7-SDAG-NEXT:    v_cmp_lt_u64_e64 s[4:5], v[0:1], v[4:5]
; GFX7-SDAG-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX7-SDAG-NEXT:    v_cmp_gt_i64_e32 vcc, v[2:3], v[6:7]
; GFX7-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX7-SDAG-NEXT:    v_cmp_lt_i64_e64 s[4:5], v[2:3], v[6:7]
; GFX7-SDAG-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
; GFX7-SDAG-NEXT:    v_cmp_eq_u64_e32 vcc, v[2:3], v[6:7]
; GFX7-SDAG-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s[4:5]
; GFX7-SDAG-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX7-SDAG-NEXT:    v_cndmask_b32_e32 v8, v9, v8, vcc
; GFX7-SDAG-NEXT:    v_and_b32_e32 v0, 1, v0
; GFX7-SDAG-NEXT:    v_and_b32_e32 v8, 1, v8
; GFX7-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
; GFX7-SDAG-NEXT:    v_cndmask_b32_e64 v0, v8, -1, vcc
; GFX7-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: scmp_i128:
; GFX7-GISEL:       ; %bb.0:
; GFX7-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT:    v_cmp_gt_u64_e32 vcc, v[0:1], v[4:5]
; GFX7-GISEL-NEXT:    v_cmp_lt_u64_e64 s[4:5], v[0:1], v[4:5]
; GFX7-GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX7-GISEL-NEXT:    v_cmp_gt_i64_e32 vcc, v[2:3], v[6:7]
; GFX7-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX7-GISEL-NEXT:    v_cmp_lt_i64_e64 s[4:5], v[2:3], v[6:7]
; GFX7-GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
; GFX7-GISEL-NEXT:    v_cmp_eq_u64_e32 vcc, v[2:3], v[6:7]
; GFX7-GISEL-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s[4:5]
; GFX7-GISEL-NEXT:    v_cndmask_b32_e32 v8, v9, v8, vcc
; GFX7-GISEL-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX7-GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v8, v0
; GFX7-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: scmp_i128:
; GFX12-SDAG:       ; %bb.0:
; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT:    v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[6:7]
; GFX12-SDAG-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX12-SDAG-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
; GFX12-SDAG-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc_lo
; GFX12-SDAG-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[6:7]
; GFX12-SDAG-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc_lo
; GFX12-SDAG-NEXT:    v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[4:5]
; GFX12-SDAG-NEXT:    v_mov_b16_e32 v0.l, v8.l
; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX12-SDAG-NEXT:    v_mov_b16_e32 v1.l, v10.l
; GFX12-SDAG-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; GFX12-SDAG-NEXT:    v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[6:7]
; GFX12-SDAG-NEXT:    v_mov_b16_e32 v2.l, v9.l
; GFX12-SDAG-NEXT:    v_mov_b16_e32 v3.l, v4.l
; GFX12-SDAG-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT:    v_cndmask_b16 v0.h, v1.l, v2.l, vcc_lo
; GFX12-SDAG-NEXT:    v_cndmask_b16 v1.l, v0.l, v3.l, vcc_lo
; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT:    v_and_b16 v0.l, 1, v0.h
; GFX12-SDAG-NEXT:    v_and_b32_e32 v1, 1, v1
; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
; GFX12-SDAG-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT:    v_cndmask_b32_e64 v0, v1, -1, vcc_lo
; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: scmp_i128:
; GFX12-GISEL:       ; %bb.0:
; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[4:5]
; GFX12-GISEL-NEXT:    v_cmp_lt_u64_e64 s0, v[0:1], v[4:5]
; GFX12-GISEL-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX12-GISEL-NEXT:    v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[6:7]
; GFX12-GISEL-NEXT:    s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX12-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
; GFX12-GISEL-NEXT:    v_cmp_lt_i64_e64 s0, v[2:3], v[6:7]
; GFX12-GISEL-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc_lo
; GFX12-GISEL-NEXT:    v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[6:7]
; GFX12-GISEL-NEXT:    s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s0
; GFX12-GISEL-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT:    v_cndmask_b32_e32 v2, v9, v8, vcc_lo
; GFX12-GISEL-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT:    v_sub_nc_u32_e32 v0, v2, v0
; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
  %r = call i32 @llvm.scmp.i32.i128(i128 %a, i128 %b)
  ret i32 %r
}

define i32 @scmp_i64(i64 %a, i64 %b) {
; GFX7-SDAG-LABEL: scmp_i64:
; GFX7-SDAG:       ; %bb.0:
; GFX7-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-SDAG-NEXT:    v_cmp_gt_i64_e32 vcc, v[0:1], v[2:3]
; GFX7-SDAG-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX7-SDAG-NEXT:    v_cmp_ge_i64_e32 vcc, v[0:1], v[2:3]
; GFX7-SDAG-NEXT:    v_cndmask_b32_e32 v0, -1, v4, vcc
; GFX7-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: scmp_i64:
; GFX7-GISEL:       ; %bb.0:
; GFX7-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT:    v_cmp_gt_i64_e32 vcc, v[0:1], v[2:3]
; GFX7-GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX7-GISEL-NEXT:    v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
; GFX7-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX7-GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v4, v0
; GFX7-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: scmp_i64:
; GFX12-SDAG:       ; %bb.0:
; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT:    v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-SDAG-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; GFX12-SDAG-NEXT:    v_cmp_ge_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-SDAG-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX12-SDAG-NEXT:    v_cndmask_b32_e32 v0, -1, v4, vcc_lo
; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: scmp_i64:
; GFX12-GISEL:       ; %bb.0:
; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-GISEL-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; GFX12-GISEL-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-GISEL-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT:    v_sub_nc_u32_e32 v0, v4, v0
; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
  %r = call i32 @llvm.scmp.i32.i64(i64 %a, i64 %b)
  ret i32 %r
}

define i32 @scmp_i32(i32 %a, i32 %b) {
; GFX7-SDAG-LABEL: scmp_i32:
; GFX7-SDAG:       ; %bb.0:
; GFX7-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, v0, v1
; GFX7-SDAG-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX7-SDAG-NEXT:    v_cmp_ge_i32_e32 vcc, v0, v1
; GFX7-SDAG-NEXT:    v_cndmask_b32_e32 v0, -1, v2, vcc
; GFX7-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: scmp_i32:
; GFX7-GISEL:       ; %bb.0:
; GFX7-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, v0, v1
; GFX7-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX7-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, v0, v1
; GFX7-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX7-GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v2, v0
; GFX7-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: scmp_i32:
; GFX12-SDAG:       ; %bb.0:
; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc_lo, v0, v1
; GFX12-SDAG-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX12-SDAG-NEXT:    v_cmp_ge_i32_e32 vcc_lo, v0, v1
; GFX12-SDAG-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX12-SDAG-NEXT:    v_cndmask_b32_e32 v0, -1, v2, vcc_lo
; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: scmp_i32:
; GFX12-GISEL:       ; %bb.0:
; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc_lo, v0, v1
; GFX12-GISEL-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX12-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc_lo, v0, v1
; GFX12-GISEL-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT:    v_sub_nc_u32_e32 v0, v2, v0
; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
  %r = call i32 @llvm.scmp.i32.i32(i32 %a, i32 %b)
  ret i32 %r
}

define i32 @scmp_i16(i16 %a, i16 %b) {
; GFX7-SDAG-LABEL: scmp_i16:
; GFX7-SDAG:       ; %bb.0:
; GFX7-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 16
; GFX7-SDAG-NEXT:    v_bfe_i32 v0, v0, 0, 16
; GFX7-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, v0, v1
; GFX7-SDAG-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX7-SDAG-NEXT:    v_cmp_ge_i32_e32 vcc, v0, v1
; GFX7-SDAG-NEXT:    v_cndmask_b32_e32 v0, -1, v2, vcc
; GFX7-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: scmp_i16:
; GFX7-GISEL:       ; %bb.0:
; GFX7-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT:    v_bfe_i32 v0, v0, 0, 16
; GFX7-GISEL-NEXT:    v_bfe_i32 v1, v1, 0, 16
; GFX7-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, v0, v1
; GFX7-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX7-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, v0, v1
; GFX7-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX7-GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v2, v0
; GFX7-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: scmp_i16:
; GFX12-SDAG:       ; %bb.0:
; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT:    v_cmp_gt_i16_e32 vcc_lo, v0.l, v1.l
; GFX12-SDAG-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX12-SDAG-NEXT:    v_cmp_ge_i16_e32 vcc_lo, v0.l, v1.l
; GFX12-SDAG-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX12-SDAG-NEXT:    v_cndmask_b32_e32 v0, -1, v2, vcc_lo
; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: scmp_i16:
; GFX12-GISEL:       ; %bb.0:
; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    v_cmp_gt_i16_e32 vcc_lo, v0.l, v1.l
; GFX12-GISEL-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX12-GISEL-NEXT:    v_cmp_lt_i16_e32 vcc_lo, v0.l, v1.l
; GFX12-GISEL-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT:    v_sub_nc_u32_e32 v0, v2, v0
; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
  %r = call i32 @llvm.scmp.i32.i16(i16 %a, i16 %b)
  ret i32 %r
}

define i32 @scmp_i8(i8 %a, i8 %b) {
; GFX7-SDAG-LABEL: scmp_i8:
; GFX7-SDAG:       ; %bb.0:
; GFX7-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
; GFX7-SDAG-NEXT:    v_bfe_i32 v0, v0, 0, 8
; GFX7-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, v0, v1
; GFX7-SDAG-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX7-SDAG-NEXT:    v_cmp_ge_i32_e32 vcc, v0, v1
; GFX7-SDAG-NEXT:    v_cndmask_b32_e32 v0, -1, v2, vcc
; GFX7-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: scmp_i8:
; GFX7-GISEL:       ; %bb.0:
; GFX7-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT:    v_bfe_i32 v0, v0, 0, 8
; GFX7-GISEL-NEXT:    v_bfe_i32 v1, v1, 0, 8
; GFX7-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, v0, v1
; GFX7-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX7-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, v0, v1
; GFX7-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX7-GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v2, v0
; GFX7-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: scmp_i8:
; GFX12-SDAG:       ; %bb.0:
; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT:    v_bfe_i32 v0, v0, 0, 8
; GFX12-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT:    v_cmp_gt_i16_e32 vcc_lo, v0.l, v1.l
; GFX12-SDAG-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX12-SDAG-NEXT:    v_cmp_ge_i16_e32 vcc_lo, v0.l, v1.l
; GFX12-SDAG-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT:    v_cndmask_b32_e32 v0, -1, v2, vcc_lo
; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: scmp_i8:
; GFX12-GISEL:       ; %bb.0:
; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    v_bfe_i32 v0, v0, 0, 8
; GFX12-GISEL-NEXT:    v_bfe_i32 v1, v1, 0, 8
; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc_lo, v0, v1
; GFX12-GISEL-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX12-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc_lo, v0, v1
; GFX12-GISEL-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT:    v_sub_nc_u32_e32 v0, v2, v0
; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
  %r = call i32 @llvm.scmp.i32.i8(i8 %a, i8 %b)
  ret i32 %r
}

define <2 x i32> @scmp_v2i16(<2 x i16> %a, <2 x i16> %b) {
; GFX7-SDAG-LABEL: scmp_v2i16:
; GFX7-SDAG:       ; %bb.0:
; GFX7-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-SDAG-NEXT:    v_ashrrev_i32_e32 v2, 16, v1
; GFX7-SDAG-NEXT:    v_ashrrev_i32_e32 v3, 16, v0
; GFX7-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, v3, v2
; GFX7-SDAG-NEXT:    v_bfe_i32 v4, v1, 0, 16
; GFX7-SDAG-NEXT:    v_bfe_i32 v0, v0, 0, 16
; GFX7-SDAG-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX7-SDAG-NEXT:    v_cmp_ge_i32_e32 vcc, v3, v2
; GFX7-SDAG-NEXT:    v_cndmask_b32_e32 v1, -1, v1, vcc
; GFX7-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, v0, v4
; GFX7-SDAG-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX7-SDAG-NEXT:    v_cmp_ge_i32_e32 vcc, v0, v4
; GFX7-SDAG-NEXT:    v_cndmask_b32_e32 v0, -1, v2, vcc
; GFX7-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: scmp_v2i16:
; GFX7-GISEL:       ; %bb.0:
; GFX7-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT:    v_bfe_i32 v2, v0, 0, 16
; GFX7-GISEL-NEXT:    v_bfe_i32 v3, v1, 0, 16
; GFX7-GISEL-NEXT:    v_bfe_i32 v0, v0, 16, 16
; GFX7-GISEL-NEXT:    v_bfe_i32 v1, v1, 16, 16
; GFX7-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, v2, v3
; GFX7-GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX7-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, v0, v1
; GFX7-GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX7-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, v2, v3
; GFX7-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX7-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, v0, v1
; GFX7-GISEL-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX7-GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v4, v2
; GFX7-GISEL-NEXT:    v_sub_i32_e32 v1, vcc, v5, v1
; GFX7-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: scmp_v2i16:
; GFX12-SDAG:       ; %bb.0:
; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
; GFX12-SDAG-NEXT:    v_cmp_gt_i16_e32 vcc_lo, v0.l, v1.l
; GFX12-SDAG-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX12-SDAG-NEXT:    v_cmp_gt_i16_e32 vcc_lo, v3.l, v2.l
; GFX12-SDAG-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX12-SDAG-NEXT:    v_cmp_ge_i16_e32 vcc_lo, v0.l, v1.l
; GFX12-SDAG-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT:    v_cndmask_b32_e32 v0, -1, v4, vcc_lo
; GFX12-SDAG-NEXT:    v_cmp_ge_i16_e32 vcc_lo, v3.l, v2.l
; GFX12-SDAG-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT:    v_cndmask_b32_e32 v1, -1, v5, vcc_lo
; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: scmp_v2i16:
; GFX12-GISEL:       ; %bb.0:
; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    v_cmp_gt_i16_e32 vcc_lo, v0.l, v1.l
; GFX12-GISEL-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX12-GISEL-NEXT:    v_cmp_gt_i16_e32 vcc_lo, v0.h, v1.h
; GFX12-GISEL-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc_lo
; GFX12-GISEL-NEXT:    v_cmp_lt_i16_e32 vcc_lo, v0.l, v1.l
; GFX12-GISEL-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; GFX12-GISEL-NEXT:    v_cmp_lt_i16_e32 vcc_lo, v0.h, v1.h
; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT:    v_sub_nc_u32_e32 v0, v2, v4
; GFX12-GISEL-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX12-GISEL-NEXT:    v_sub_nc_u32_e32 v1, v3, v1
; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
  %r = call <2 x i32> @llvm.scmp.v2i32.v2i16(<2 x i16> %a, <2 x i16> %b)
  ret <2 x i32> %r
}

define <4 x i32> @scmp_v4i8(<4 x i8> %a, <4 x i8> %b) {
; GFX7-SDAG-LABEL: scmp_v4i8:
; GFX7-SDAG:       ; %bb.0:
; GFX7-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-SDAG-NEXT:    v_bfe_i32 v4, v4, 0, 8
; GFX7-SDAG-NEXT:    v_bfe_i32 v0, v0, 0, 8
; GFX7-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, v0, v4
; GFX7-SDAG-NEXT:    v_bfe_i32 v5, v5, 0, 8
; GFX7-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
; GFX7-SDAG-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX7-SDAG-NEXT:    v_cmp_ge_i32_e32 vcc, v0, v4
; GFX7-SDAG-NEXT:    v_cndmask_b32_e32 v0, -1, v8, vcc
; GFX7-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, v1, v5
; GFX7-SDAG-NEXT:    v_bfe_i32 v6, v6, 0, 8
; GFX7-SDAG-NEXT:    v_bfe_i32 v2, v2, 0, 8
; GFX7-SDAG-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX7-SDAG-NEXT:    v_cmp_ge_i32_e32 vcc, v1, v5
; GFX7-SDAG-NEXT:    v_cndmask_b32_e32 v1, -1, v4, vcc
; GFX7-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, v2, v6
; GFX7-SDAG-NEXT:    v_bfe_i32 v7, v7, 0, 8
; GFX7-SDAG-NEXT:    v_bfe_i32 v3, v3, 0, 8
; GFX7-SDAG-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX7-SDAG-NEXT:    v_cmp_ge_i32_e32 vcc, v2, v6
; GFX7-SDAG-NEXT:    v_cndmask_b32_e32 v2, -1, v4, vcc
; GFX7-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, v3, v7
; GFX7-SDAG-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX7-SDAG-NEXT:    v_cmp_ge_i32_e32 vcc, v3, v7
; GFX7-SDAG-NEXT:    v_cndmask_b32_e32 v3, -1, v4, vcc
; GFX7-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: scmp_v4i8:
; GFX7-GISEL:       ; %bb.0:
; GFX7-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT:    v_bfe_i32 v0, v0, 0, 8
; GFX7-GISEL-NEXT:    v_bfe_i32 v4, v4, 0, 8
; GFX7-GISEL-NEXT:    v_bfe_i32 v1, v1, 0, 8
; GFX7-GISEL-NEXT:    v_bfe_i32 v5, v5, 0, 8
; GFX7-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, v0, v4
; GFX7-GISEL-NEXT:    v_bfe_i32 v2, v2, 0, 8
; GFX7-GISEL-NEXT:    v_bfe_i32 v6, v6, 0, 8
; GFX7-GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX7-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, v1, v5
; GFX7-GISEL-NEXT:    v_bfe_i32 v3, v3, 0, 8
; GFX7-GISEL-NEXT:    v_bfe_i32 v7, v7, 0, 8
; GFX7-GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
; GFX7-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, v2, v6
; GFX7-GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
; GFX7-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, v3, v7
; GFX7-GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
; GFX7-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, v0, v4
; GFX7-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX7-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, v1, v5
; GFX7-GISEL-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX7-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, v2, v6
; GFX7-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX7-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, v3, v7
; GFX7-GISEL-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX7-GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v8, v0
; GFX7-GISEL-NEXT:    v_sub_i32_e32 v1, vcc, v9, v1
; GFX7-GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v10, v2
; GFX7-GISEL-NEXT:    v_sub_i32_e32 v3, vcc, v11, v3
; GFX7-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: scmp_v4i8:
; GFX12-SDAG:       ; %bb.0:
; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT:    v_bfe_i32 v4, v4, 0, 8
; GFX12-SDAG-NEXT:    v_bfe_i32 v0, v0, 0, 8
; GFX12-SDAG-NEXT:    v_bfe_i32 v8, v3, 0, 8
; GFX12-SDAG-NEXT:    v_bfe_i32 v5, v5, 0, 8
; GFX12-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
; GFX12-SDAG-NEXT:    v_mov_b16_e32 v3.l, v4.l
; GFX12-SDAG-NEXT:    v_bfe_i32 v4, v6, 0, 8
; GFX12-SDAG-NEXT:    v_bfe_i32 v9, v2, 0, 8
; GFX12-SDAG-NEXT:    v_mov_b16_e32 v2.l, v5.l
; GFX12-SDAG-NEXT:    v_bfe_i32 v7, v7, 0, 8
; GFX12-SDAG-NEXT:    v_cmp_gt_i16_e32 vcc_lo, v0.l, v3.l
; GFX12-SDAG-NEXT:    v_mov_b16_e32 v5.l, v8.l
; GFX12-SDAG-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX12-SDAG-NEXT:    v_cmp_ge_i16_e32 vcc_lo, v0.l, v3.l
; GFX12-SDAG-NEXT:    v_mov_b16_e32 v3.l, v9.l
; GFX12-SDAG-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX12-SDAG-NEXT:    v_cndmask_b32_e32 v0, -1, v6, vcc_lo
; GFX12-SDAG-NEXT:    v_cmp_gt_i16_e32 vcc_lo, v1.l, v2.l
; GFX12-SDAG-NEXT:    v_mov_b16_e32 v6.l, v7.l
; GFX12-SDAG-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX12-SDAG-NEXT:    v_cmp_gt_i16_e32 vcc_lo, v3.l, v4.l
; GFX12-SDAG-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX12-SDAG-NEXT:    v_cmp_gt_i16_e32 vcc_lo, v5.l, v6.l
; GFX12-SDAG-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc_lo
; GFX12-SDAG-NEXT:    v_cmp_ge_i16_e32 vcc_lo, v1.l, v2.l
; GFX12-SDAG-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT:    v_cndmask_b32_e32 v1, -1, v7, vcc_lo
; GFX12-SDAG-NEXT:    v_cmp_ge_i16_e32 vcc_lo, v3.l, v4.l
; GFX12-SDAG-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT:    v_cndmask_b32_e32 v2, -1, v8, vcc_lo
; GFX12-SDAG-NEXT:    v_cmp_ge_i16_e32 vcc_lo, v5.l, v6.l
; GFX12-SDAG-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT:    v_cndmask_b32_e32 v3, -1, v9, vcc_lo
; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: scmp_v4i8:
; GFX12-GISEL:       ; %bb.0:
; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    v_bfe_i32 v0, v0, 0, 8
; GFX12-GISEL-NEXT:    v_bfe_i32 v4, v4, 0, 8
; GFX12-GISEL-NEXT:    v_bfe_i32 v1, v1, 0, 8
; GFX12-GISEL-NEXT:    v_bfe_i32 v5, v5, 0, 8
; GFX12-GISEL-NEXT:    v_bfe_i32 v2, v2, 0, 8
; GFX12-GISEL-NEXT:    v_bfe_i32 v6, v6, 0, 8
; GFX12-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc_lo, v0, v4
; GFX12-GISEL-NEXT:    v_bfe_i32 v3, v3, 0, 8
; GFX12-GISEL-NEXT:    v_bfe_i32 v7, v7, 0, 8
; GFX12-GISEL-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX12-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc_lo, v1, v5
; GFX12-GISEL-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc_lo
; GFX12-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc_lo, v2, v6
; GFX12-GISEL-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc_lo
; GFX12-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc_lo, v3, v7
; GFX12-GISEL-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc_lo
; GFX12-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc_lo, v0, v4
; GFX12-GISEL-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX12-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc_lo, v1, v5
; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT:    v_sub_nc_u32_e32 v0, v8, v0
; GFX12-GISEL-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX12-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc_lo, v2, v6
; GFX12-GISEL-NEXT:    v_sub_nc_u32_e32 v1, v9, v1
; GFX12-GISEL-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX12-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc_lo, v3, v7
; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT:    v_sub_nc_u32_e32 v2, v10, v2
; GFX12-GISEL-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc_lo
; GFX12-GISEL-NEXT:    v_sub_nc_u32_e32 v3, v11, v3
; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
  %r = call <4 x i32> @llvm.scmp.v4i32.v4i8(<4 x i8> %a, <4 x i8> %b)
  ret <4 x i32> %r
}

define i32 @scmp_i128_uniform(i128 inreg %a, i128 inreg %b) {
; GFX7-SDAG-LABEL: scmp_i128_uniform:
; GFX7-SDAG:       ; %bb.0:
; GFX7-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-SDAG-NEXT:    v_mov_b32_e32 v0, s22
; GFX7-SDAG-NEXT:    v_mov_b32_e32 v1, s23
; GFX7-SDAG-NEXT:    v_cmp_gt_i64_e32 vcc, s[18:19], v[0:1]
; GFX7-SDAG-NEXT:    v_mov_b32_e32 v2, s20
; GFX7-SDAG-NEXT:    v_mov_b32_e32 v3, s21
; GFX7-SDAG-NEXT:    s_and_b64 s[6:7], vcc, exec
; GFX7-SDAG-NEXT:    v_cmp_gt_u64_e32 vcc, s[16:17], v[2:3]
; GFX7-SDAG-NEXT:    v_cmp_eq_u64_e64 s[4:5], s[18:19], v[0:1]
; GFX7-SDAG-NEXT:    s_cselect_b32 s8, 1, 0
; GFX7-SDAG-NEXT:    s_and_b64 s[6:7], vcc, exec
; GFX7-SDAG-NEXT:    s_cselect_b32 s9, 1, 0
; GFX7-SDAG-NEXT:    s_and_b64 s[6:7], s[4:5], exec
; GFX7-SDAG-NEXT:    s_cselect_b32 s6, s9, s8
; GFX7-SDAG-NEXT:    v_cmp_lt_i64_e32 vcc, s[18:19], v[0:1]
; GFX7-SDAG-NEXT:    s_and_b32 s8, s6, 1
; GFX7-SDAG-NEXT:    s_and_b64 s[6:7], vcc, exec
; GFX7-SDAG-NEXT:    v_cmp_lt_u64_e32 vcc, s[16:17], v[2:3]
; GFX7-SDAG-NEXT:    s_cselect_b32 s9, 1, 0
; GFX7-SDAG-NEXT:    s_and_b64 s[6:7], vcc, exec
; GFX7-SDAG-NEXT:    s_cselect_b32 s6, 1, 0
; GFX7-SDAG-NEXT:    s_and_b64 s[4:5], s[4:5], exec
; GFX7-SDAG-NEXT:    s_cselect_b32 s4, s6, s9
; GFX7-SDAG-NEXT:    s_bitcmp1_b32 s4, 0
; GFX7-SDAG-NEXT:    s_cselect_b32 s4, -1, s8
; GFX7-SDAG-NEXT:    v_mov_b32_e32 v0, s4
; GFX7-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: scmp_i128_uniform:
; GFX7-GISEL:       ; %bb.0:
; GFX7-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT:    v_mov_b32_e32 v0, s20
; GFX7-GISEL-NEXT:    v_mov_b32_e32 v1, s21
; GFX7-GISEL-NEXT:    v_cmp_gt_u64_e32 vcc, s[16:17], v[0:1]
; GFX7-GISEL-NEXT:    v_mov_b32_e32 v2, s22
; GFX7-GISEL-NEXT:    v_mov_b32_e32 v3, s23
; GFX7-GISEL-NEXT:    s_or_b64 s[4:5], vcc, vcc
; GFX7-GISEL-NEXT:    v_cmp_gt_i64_e32 vcc, s[18:19], v[2:3]
; GFX7-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
; GFX7-GISEL-NEXT:    s_or_b64 s[4:5], vcc, vcc
; GFX7-GISEL-NEXT:    v_cmp_eq_u64_e32 vcc, s[18:19], v[2:3]
; GFX7-GISEL-NEXT:    s_cselect_b32 s7, 1, 0
; GFX7-GISEL-NEXT:    s_or_b64 s[4:5], vcc, vcc
; GFX7-GISEL-NEXT:    v_cmp_lt_u64_e64 s[4:5], s[16:17], v[0:1]
; GFX7-GISEL-NEXT:    s_cselect_b32 s8, 1, 0
; GFX7-GISEL-NEXT:    s_or_b64 s[4:5], s[4:5], s[4:5]
; GFX7-GISEL-NEXT:    v_cmp_lt_i64_e64 s[4:5], s[18:19], v[2:3]
; GFX7-GISEL-NEXT:    s_cselect_b32 s9, 1, 0
; GFX7-GISEL-NEXT:    s_or_b64 s[4:5], s[4:5], s[4:5]
; GFX7-GISEL-NEXT:    s_cselect_b32 s10, 1, 0
; GFX7-GISEL-NEXT:    s_or_b64 s[4:5], vcc, vcc
; GFX7-GISEL-NEXT:    s_cselect_b32 s4, 1, 0
; GFX7-GISEL-NEXT:    s_cmp_lg_u32 s8, 0
; GFX7-GISEL-NEXT:    s_cselect_b32 s5, s6, s7
; GFX7-GISEL-NEXT:    s_cmp_lg_u32 s4, 0
; GFX7-GISEL-NEXT:    s_cselect_b32 s4, s9, s10
; GFX7-GISEL-NEXT:    s_sub_i32 s4, s5, s4
; GFX7-GISEL-NEXT:    v_mov_b32_e32 v0, s4
; GFX7-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: scmp_i128_uniform:
; GFX12-SDAG:       ; %bb.0:
; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT:    v_cmp_gt_u64_e64 s4, s[0:1], s[16:17]
; GFX12-SDAG-NEXT:    v_cmp_gt_i64_e64 s5, s[2:3], s[18:19]
; GFX12-SDAG-NEXT:    v_cmp_lt_i64_e64 s6, s[2:3], s[18:19]
; GFX12-SDAG-NEXT:    v_cmp_lt_u64_e64 s0, s[0:1], s[16:17]
; GFX12-SDAG-NEXT:    s_and_b32 s4, s4, exec_lo
; GFX12-SDAG-NEXT:    s_cselect_b32 s1, 1, 0
; GFX12-SDAG-NEXT:    s_and_b32 s4, s5, exec_lo
; GFX12-SDAG-NEXT:    s_cselect_b32 s4, 1, 0
; GFX12-SDAG-NEXT:    s_and_b32 s5, s6, exec_lo
; GFX12-SDAG-NEXT:    s_cselect_b32 s5, 1, 0
; GFX12-SDAG-NEXT:    s_and_b32 s0, s0, exec_lo
; GFX12-SDAG-NEXT:    s_cselect_b32 s0, 1, 0
; GFX12-SDAG-NEXT:    s_cmp_eq_u64 s[2:3], s[18:19]
; GFX12-SDAG-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT:    s_cselect_b32 s1, s1, s4
; GFX12-SDAG-NEXT:    s_cselect_b32 s0, s0, s5
; GFX12-SDAG-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT:    s_and_b32 s1, s1, 1
; GFX12-SDAG-NEXT:    s_bitcmp1_b32 s0, 0
; GFX12-SDAG-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT:    s_cselect_b32 s0, -1, s1
; GFX12-SDAG-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT:    v_mov_b32_e32 v0, s0
; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: scmp_i128_uniform:
; GFX12-GISEL:       ; %bb.0:
; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    v_cmp_gt_u64_e64 s4, s[0:1], s[16:17]
; GFX12-GISEL-NEXT:    v_cmp_gt_i64_e64 s5, s[2:3], s[18:19]
; GFX12-GISEL-NEXT:    v_cmp_lt_u64_e64 s0, s[0:1], s[16:17]
; GFX12-GISEL-NEXT:    v_cmp_lt_i64_e64 s6, s[2:3], s[18:19]
; GFX12-GISEL-NEXT:    s_cmp_lg_u32 s4, 0
; GFX12-GISEL-NEXT:    s_cselect_b32 s4, 1, 0
; GFX12-GISEL-NEXT:    s_cmp_lg_u32 s5, 0
; GFX12-GISEL-NEXT:    s_cselect_b32 s5, 1, 0
; GFX12-GISEL-NEXT:    s_cmp_eq_u64 s[2:3], s[18:19]
; GFX12-GISEL-NEXT:    s_cselect_b32 s1, 1, 0
; GFX12-GISEL-NEXT:    s_cmp_lg_u32 s0, 0
; GFX12-GISEL-NEXT:    s_cselect_b32 s0, 1, 0
; GFX12-GISEL-NEXT:    s_cmp_lg_u32 s6, 0
; GFX12-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
; GFX12-GISEL-NEXT:    s_cmp_eq_u64 s[2:3], s[18:19]
; GFX12-GISEL-NEXT:    s_cselect_b32 s2, 1, 0
; GFX12-GISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT:    s_cmp_lg_u32 s1, 0
; GFX12-GISEL-NEXT:    s_cselect_b32 s1, s4, s5
; GFX12-GISEL-NEXT:    s_cmp_lg_u32 s2, 0
; GFX12-GISEL-NEXT:    s_cselect_b32 s0, s0, s6
; GFX12-GISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT:    s_sub_co_i32 s0, s1, s0
; GFX12-GISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT:    v_mov_b32_e32 v0, s0
; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
  %r = call i32 @llvm.scmp.i32.i128(i128 %a, i128 %b)
  ret i32 %r
}

define i32 @scmp_i64_uniform(i64 inreg %a, i64 inreg %b) {
; GFX7-SDAG-LABEL: scmp_i64_uniform:
; GFX7-SDAG:       ; %bb.0:
; GFX7-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-SDAG-NEXT:    v_mov_b32_e32 v0, s18
; GFX7-SDAG-NEXT:    v_mov_b32_e32 v1, s19
; GFX7-SDAG-NEXT:    v_cmp_gt_i64_e32 vcc, s[16:17], v[0:1]
; GFX7-SDAG-NEXT:    s_and_b64 s[4:5], vcc, exec
; GFX7-SDAG-NEXT:    v_cmp_ge_i64_e32 vcc, s[16:17], v[0:1]
; GFX7-SDAG-NEXT:    s_cselect_b32 s6, 1, 0
; GFX7-SDAG-NEXT:    s_and_b64 s[4:5], vcc, exec
; GFX7-SDAG-NEXT:    s_cselect_b32 s4, s6, -1
; GFX7-SDAG-NEXT:    v_mov_b32_e32 v0, s4
; GFX7-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: scmp_i64_uniform:
; GFX7-GISEL:       ; %bb.0:
; GFX7-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT:    v_mov_b32_e32 v0, s18
; GFX7-GISEL-NEXT:    v_mov_b32_e32 v1, s19
; GFX7-GISEL-NEXT:    v_cmp_gt_i64_e32 vcc, s[16:17], v[0:1]
; GFX7-GISEL-NEXT:    s_or_b64 s[4:5], vcc, vcc
; GFX7-GISEL-NEXT:    v_cmp_lt_i64_e32 vcc, s[16:17], v[0:1]
; GFX7-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
; GFX7-GISEL-NEXT:    s_or_b64 s[4:5], vcc, vcc
; GFX7-GISEL-NEXT:    s_cselect_b32 s4, 1, 0
; GFX7-GISEL-NEXT:    s_cmp_lg_u32 s6, 0
; GFX7-GISEL-NEXT:    s_cselect_b32 s5, 1, 0
; GFX7-GISEL-NEXT:    s_cmp_lg_u32 s4, 0
; GFX7-GISEL-NEXT:    s_cselect_b32 s4, 1, 0
; GFX7-GISEL-NEXT:    s_sub_i32 s4, s5, s4
; GFX7-GISEL-NEXT:    v_mov_b32_e32 v0, s4
; GFX7-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: scmp_i64_uniform:
; GFX12-SDAG:       ; %bb.0:
; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT:    v_cmp_gt_i64_e64 s4, s[0:1], s[2:3]
; GFX12-SDAG-NEXT:    v_cmp_ge_i64_e64 s0, s[0:1], s[2:3]
; GFX12-SDAG-NEXT:    s_and_b32 s1, s4, exec_lo
; GFX12-SDAG-NEXT:    s_cselect_b32 s1, 1, 0
; GFX12-SDAG-NEXT:    s_and_b32 s0, s0, exec_lo
; GFX12-SDAG-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT:    s_cselect_b32 s0, s1, -1
; GFX12-SDAG-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT:    v_mov_b32_e32 v0, s0
; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: scmp_i64_uniform:
; GFX12-GISEL:       ; %bb.0:
; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    v_cmp_gt_i64_e64 s4, s[0:1], s[2:3]
; GFX12-GISEL-NEXT:    v_cmp_lt_i64_e64 s0, s[0:1], s[2:3]
; GFX12-GISEL-NEXT:    s_cmp_lg_u32 s4, 0
; GFX12-GISEL-NEXT:    s_cselect_b32 s1, 1, 0
; GFX12-GISEL-NEXT:    s_cmp_lg_u32 s0, 0
; GFX12-GISEL-NEXT:    s_cselect_b32 s0, 1, 0
; GFX12-GISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT:    s_cmp_lg_u32 s1, 0
; GFX12-GISEL-NEXT:    s_cselect_b32 s1, 1, 0
; GFX12-GISEL-NEXT:    s_cmp_lg_u32 s0, 0
; GFX12-GISEL-NEXT:    s_cselect_b32 s0, 1, 0
; GFX12-GISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT:    s_sub_co_i32 s0, s1, s0
; GFX12-GISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT:    v_mov_b32_e32 v0, s0
; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
  %r = call i32 @llvm.scmp.i32.i64(i64 %a, i64 %b)
  ret i32 %r
}

define i32 @scmp_i32_uniform(i32 inreg %a, i32 inreg %b) {
; GFX7-SDAG-LABEL: scmp_i32_uniform:
; GFX7-SDAG:       ; %bb.0:
; GFX7-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-SDAG-NEXT:    s_cmp_gt_i32 s16, s17
; GFX7-SDAG-NEXT:    s_cselect_b32 s4, 1, 0
; GFX7-SDAG-NEXT:    s_cmp_ge_i32 s16, s17
; GFX7-SDAG-NEXT:    s_cselect_b32 s4, s4, -1
; GFX7-SDAG-NEXT:    v_mov_b32_e32 v0, s4
; GFX7-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: scmp_i32_uniform:
; GFX7-GISEL:       ; %bb.0:
; GFX7-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT:    s_cmp_gt_i32 s16, s17
; GFX7-GISEL-NEXT:    s_cselect_b32 s4, 1, 0
; GFX7-GISEL-NEXT:    s_cmp_lt_i32 s16, s17
; GFX7-GISEL-NEXT:    s_cselect_b32 s5, 1, 0
; GFX7-GISEL-NEXT:    s_cmp_lg_u32 s4, 0
; GFX7-GISEL-NEXT:    s_cselect_b32 s4, 1, 0
; GFX7-GISEL-NEXT:    s_cmp_lg_u32 s5, 0
; GFX7-GISEL-NEXT:    s_cselect_b32 s5, 1, 0
; GFX7-GISEL-NEXT:    s_sub_i32 s4, s4, s5
; GFX7-GISEL-NEXT:    v_mov_b32_e32 v0, s4
; GFX7-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: scmp_i32_uniform:
; GFX12-SDAG:       ; %bb.0:
; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT:    s_cmp_gt_i32 s0, s1
; GFX12-SDAG-NEXT:    s_cselect_b32 s2, 1, 0
; GFX12-SDAG-NEXT:    s_cmp_ge_i32 s0, s1
; GFX12-SDAG-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT:    s_cselect_b32 s0, s2, -1
; GFX12-SDAG-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT:    v_mov_b32_e32 v0, s0
; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: scmp_i32_uniform:
; GFX12-GISEL:       ; %bb.0:
; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    s_cmp_gt_i32 s0, s1
; GFX12-GISEL-NEXT:    s_cselect_b32 s2, 1, 0
; GFX12-GISEL-NEXT:    s_cmp_lt_i32 s0, s1
; GFX12-GISEL-NEXT:    s_cselect_b32 s0, 1, 0
; GFX12-GISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT:    s_cmp_lg_u32 s2, 0
; GFX12-GISEL-NEXT:    s_cselect_b32 s1, 1, 0
; GFX12-GISEL-NEXT:    s_cmp_lg_u32 s0, 0
; GFX12-GISEL-NEXT:    s_cselect_b32 s0, 1, 0
; GFX12-GISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT:    s_sub_co_i32 s0, s1, s0
; GFX12-GISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT:    v_mov_b32_e32 v0, s0
; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
  %r = call i32 @llvm.scmp.i32.i32(i32 %a, i32 %b)
  ret i32 %r
}

define i32 @scmp_i16_uniform(i16 inreg %a, i16 inreg %b) {
; GFX7-SDAG-LABEL: scmp_i16_uniform:
; GFX7-SDAG:       ; %bb.0:
; GFX7-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-SDAG-NEXT:    s_sext_i32_i16 s4, s17
; GFX7-SDAG-NEXT:    s_sext_i32_i16 s5, s16
; GFX7-SDAG-NEXT:    s_cmp_gt_i32 s5, s4
; GFX7-SDAG-NEXT:    s_cselect_b32 s6, 1, 0
; GFX7-SDAG-NEXT:    s_cmp_ge_i32 s5, s4
; GFX7-SDAG-NEXT:    s_cselect_b32 s4, s6, -1
; GFX7-SDAG-NEXT:    v_mov_b32_e32 v0, s4
; GFX7-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: scmp_i16_uniform:
; GFX7-GISEL:       ; %bb.0:
; GFX7-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT:    s_sext_i32_i16 s4, s16
; GFX7-GISEL-NEXT:    s_sext_i32_i16 s5, s17
; GFX7-GISEL-NEXT:    s_cmp_gt_i32 s4, s5
; GFX7-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
; GFX7-GISEL-NEXT:    s_cmp_lt_i32 s4, s5
; GFX7-GISEL-NEXT:    s_cselect_b32 s4, 1, 0
; GFX7-GISEL-NEXT:    s_cmp_lg_u32 s6, 0
; GFX7-GISEL-NEXT:    s_cselect_b32 s5, 1, 0
; GFX7-GISEL-NEXT:    s_cmp_lg_u32 s4, 0
; GFX7-GISEL-NEXT:    s_cselect_b32 s4, 1, 0
; GFX7-GISEL-NEXT:    s_sub_i32 s4, s5, s4
; GFX7-GISEL-NEXT:    v_mov_b32_e32 v0, s4
; GFX7-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: scmp_i16_uniform:
; GFX12-SDAG:       ; %bb.0:
; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT:    s_sext_i32_i16 s1, s1
; GFX12-SDAG-NEXT:    s_sext_i32_i16 s0, s0
; GFX12-SDAG-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT:    s_cmp_gt_i32 s0, s1
; GFX12-SDAG-NEXT:    s_cselect_b32 s2, 1, 0
; GFX12-SDAG-NEXT:    s_cmp_ge_i32 s0, s1
; GFX12-SDAG-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT:    s_cselect_b32 s0, s2, -1
; GFX12-SDAG-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT:    v_mov_b32_e32 v0, s0
; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: scmp_i16_uniform:
; GFX12-GISEL:       ; %bb.0:
; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    s_sext_i32_i16 s0, s0
; GFX12-GISEL-NEXT:    s_sext_i32_i16 s1, s1
; GFX12-GISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT:    s_cmp_gt_i32 s0, s1
; GFX12-GISEL-NEXT:    s_cselect_b32 s2, 1, 0
; GFX12-GISEL-NEXT:    s_cmp_lt_i32 s0, s1
; GFX12-GISEL-NEXT:    s_cselect_b32 s0, 1, 0
; GFX12-GISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT:    s_cmp_lg_u32 s2, 0
; GFX12-GISEL-NEXT:    s_cselect_b32 s1, 1, 0
; GFX12-GISEL-NEXT:    s_cmp_lg_u32 s0, 0
; GFX12-GISEL-NEXT:    s_cselect_b32 s0, 1, 0
; GFX12-GISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT:    s_sub_co_i32 s0, s1, s0
; GFX12-GISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT:    v_mov_b32_e32 v0, s0
; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
  %r = call i32 @llvm.scmp.i32.i16(i16 %a, i16 %b)
  ret i32 %r
}

define i32 @scmp_i8_uniform(i8 inreg %a, i8 inreg %b) {
; GFX7-SDAG-LABEL: scmp_i8_uniform:
; GFX7-SDAG:       ; %bb.0:
; GFX7-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-SDAG-NEXT:    s_sext_i32_i8 s4, s17
; GFX7-SDAG-NEXT:    s_sext_i32_i8 s5, s16
; GFX7-SDAG-NEXT:    s_cmp_gt_i32 s5, s4
; GFX7-SDAG-NEXT:    s_cselect_b32 s6, 1, 0
; GFX7-SDAG-NEXT:    s_cmp_ge_i32 s5, s4
; GFX7-SDAG-NEXT:    s_cselect_b32 s4, s6, -1
; GFX7-SDAG-NEXT:    v_mov_b32_e32 v0, s4
; GFX7-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: scmp_i8_uniform:
; GFX7-GISEL:       ; %bb.0:
; GFX7-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT:    s_sext_i32_i8 s4, s16
; GFX7-GISEL-NEXT:    s_sext_i32_i8 s5, s17
; GFX7-GISEL-NEXT:    s_cmp_gt_i32 s4, s5
; GFX7-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
; GFX7-GISEL-NEXT:    s_cmp_lt_i32 s4, s5
; GFX7-GISEL-NEXT:    s_cselect_b32 s4, 1, 0
; GFX7-GISEL-NEXT:    s_cmp_lg_u32 s6, 0
; GFX7-GISEL-NEXT:    s_cselect_b32 s5, 1, 0
; GFX7-GISEL-NEXT:    s_cmp_lg_u32 s4, 0
; GFX7-GISEL-NEXT:    s_cselect_b32 s4, 1, 0
; GFX7-GISEL-NEXT:    s_sub_i32 s4, s5, s4
; GFX7-GISEL-NEXT:    v_mov_b32_e32 v0, s4
; GFX7-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: scmp_i8_uniform:
; GFX12-SDAG:       ; %bb.0:
; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT:    s_bfe_i32 s1, s1, 0x80000
; GFX12-SDAG-NEXT:    s_bfe_i32 s0, s0, 0x80000
; GFX12-SDAG-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT:    s_sext_i32_i16 s1, s1
; GFX12-SDAG-NEXT:    s_sext_i32_i16 s0, s0
; GFX12-SDAG-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT:    s_cmp_gt_i32 s0, s1
; GFX12-SDAG-NEXT:    s_cselect_b32 s2, 1, 0
; GFX12-SDAG-NEXT:    s_cmp_ge_i32 s0, s1
; GFX12-SDAG-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT:    s_cselect_b32 s0, s2, -1
; GFX12-SDAG-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT:    v_mov_b32_e32 v0, s0
; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: scmp_i8_uniform:
; GFX12-GISEL:       ; %bb.0:
; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    s_sext_i32_i8 s0, s0
; GFX12-GISEL-NEXT:    s_sext_i32_i8 s1, s1
; GFX12-GISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT:    s_cmp_gt_i32 s0, s1
; GFX12-GISEL-NEXT:    s_cselect_b32 s2, 1, 0
; GFX12-GISEL-NEXT:    s_cmp_lt_i32 s0, s1
; GFX12-GISEL-NEXT:    s_cselect_b32 s0, 1, 0
; GFX12-GISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT:    s_cmp_lg_u32 s2, 0
; GFX12-GISEL-NEXT:    s_cselect_b32 s1, 1, 0
; GFX12-GISEL-NEXT:    s_cmp_lg_u32 s0, 0
; GFX12-GISEL-NEXT:    s_cselect_b32 s0, 1, 0
; GFX12-GISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT:    s_sub_co_i32 s0, s1, s0
; GFX12-GISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT:    v_mov_b32_e32 v0, s0
; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
  %r = call i32 @llvm.scmp.i32.i8(i8 %a, i8 %b)
  ret i32 %r
}

define <2 x i32> @scmp_v2i16_uniform(<2 x i16> inreg %a, <2 x i16> inreg %b) {
; GFX7-SDAG-LABEL: scmp_v2i16_uniform:
; GFX7-SDAG:       ; %bb.0:
; GFX7-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-SDAG-NEXT:    s_ashr_i32 s4, s17, 16
; GFX7-SDAG-NEXT:    s_ashr_i32 s5, s16, 16
; GFX7-SDAG-NEXT:    s_cmp_gt_i32 s5, s4
; GFX7-SDAG-NEXT:    s_sext_i32_i16 s6, s17
; GFX7-SDAG-NEXT:    s_sext_i32_i16 s7, s16
; GFX7-SDAG-NEXT:    s_cselect_b32 s8, 1, 0
; GFX7-SDAG-NEXT:    s_cmp_ge_i32 s5, s4
; GFX7-SDAG-NEXT:    s_cselect_b32 s4, s8, -1
; GFX7-SDAG-NEXT:    s_cmp_gt_i32 s7, s6
; GFX7-SDAG-NEXT:    s_cselect_b32 s5, 1, 0
; GFX7-SDAG-NEXT:    s_cmp_ge_i32 s7, s6
; GFX7-SDAG-NEXT:    s_cselect_b32 s5, s5, -1
; GFX7-SDAG-NEXT:    v_mov_b32_e32 v0, s5
; GFX7-SDAG-NEXT:    v_mov_b32_e32 v1, s4
; GFX7-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: scmp_v2i16_uniform:
; GFX7-GISEL:       ; %bb.0:
; GFX7-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT:    s_sext_i32_i16 s4, s16
; GFX7-GISEL-NEXT:    s_sext_i32_i16 s5, s17
; GFX7-GISEL-NEXT:    s_cmp_gt_i32 s4, s5
; GFX7-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
; GFX7-GISEL-NEXT:    s_bfe_i32 s7, s16, 0x100010
; GFX7-GISEL-NEXT:    s_bfe_i32 s8, s17, 0x100010
; GFX7-GISEL-NEXT:    s_cmp_gt_i32 s7, s8
; GFX7-GISEL-NEXT:    s_cselect_b32 s9, 1, 0
; GFX7-GISEL-NEXT:    s_cmp_lt_i32 s4, s5
; GFX7-GISEL-NEXT:    s_cselect_b32 s4, 1, 0
; GFX7-GISEL-NEXT:    s_cmp_lt_i32 s7, s8
; GFX7-GISEL-NEXT:    s_cselect_b32 s5, 1, 0
; GFX7-GISEL-NEXT:    s_cmp_lg_u32 s6, 0
; GFX7-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
; GFX7-GISEL-NEXT:    s_cmp_lg_u32 s9, 0
; GFX7-GISEL-NEXT:    s_cselect_b32 s7, 1, 0
; GFX7-GISEL-NEXT:    s_cmp_lg_u32 s4, 0
; GFX7-GISEL-NEXT:    s_cselect_b32 s4, 1, 0
; GFX7-GISEL-NEXT:    s_cmp_lg_u32 s5, 0
; GFX7-GISEL-NEXT:    s_cselect_b32 s5, 1, 0
; GFX7-GISEL-NEXT:    s_sub_i32 s4, s6, s4
; GFX7-GISEL-NEXT:    s_sub_i32 s5, s7, s5
; GFX7-GISEL-NEXT:    v_mov_b32_e32 v0, s4
; GFX7-GISEL-NEXT:    v_mov_b32_e32 v1, s5
; GFX7-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: scmp_v2i16_uniform:
; GFX12-SDAG:       ; %bb.0:
; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT:    s_ashr_i32 s2, s1, 16
; GFX12-SDAG-NEXT:    s_ashr_i32 s3, s0, 16
; GFX12-SDAG-NEXT:    s_sext_i32_i16 s1, s1
; GFX12-SDAG-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT:    s_cmp_gt_i32 s3, s2
; GFX12-SDAG-NEXT:    s_sext_i32_i16 s0, s0
; GFX12-SDAG-NEXT:    s_cselect_b32 s4, 1, 0
; GFX12-SDAG-NEXT:    s_cmp_ge_i32 s3, s2
; GFX12-SDAG-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT:    s_cselect_b32 s2, s4, -1
; GFX12-SDAG-NEXT:    s_cmp_gt_i32 s0, s1
; GFX12-SDAG-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT:    v_mov_b32_e32 v1, s2
; GFX12-SDAG-NEXT:    s_cselect_b32 s3, 1, 0
; GFX12-SDAG-NEXT:    s_cmp_ge_i32 s0, s1
; GFX12-SDAG-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT:    s_cselect_b32 s0, s3, -1
; GFX12-SDAG-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT:    v_mov_b32_e32 v0, s0
; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: scmp_v2i16_uniform:
; GFX12-GISEL:       ; %bb.0:
; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    s_lshr_b32 s2, s0, 16
; GFX12-GISEL-NEXT:    s_sext_i32_i16 s0, s0
; GFX12-GISEL-NEXT:    s_sext_i32_i16 s3, s1
; GFX12-GISEL-NEXT:    s_lshr_b32 s1, s1, 16
; GFX12-GISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT:    s_cmp_gt_i32 s0, s3
; GFX12-GISEL-NEXT:    s_sext_i32_i16 s2, s2
; GFX12-GISEL-NEXT:    s_sext_i32_i16 s1, s1
; GFX12-GISEL-NEXT:    s_cselect_b32 s4, 1, 0
; GFX12-GISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT:    s_cmp_gt_i32 s2, s1
; GFX12-GISEL-NEXT:    s_cselect_b32 s5, 1, 0
; GFX12-GISEL-NEXT:    s_cmp_lt_i32 s0, s3
; GFX12-GISEL-NEXT:    s_cselect_b32 s0, 1, 0
; GFX12-GISEL-NEXT:    s_cmp_lt_i32 s2, s1
; GFX12-GISEL-NEXT:    s_cselect_b32 s1, 1, 0
; GFX12-GISEL-NEXT:    s_cmp_lg_u32 s4, 0
; GFX12-GISEL-NEXT:    s_cselect_b32 s2, 1, 0
; GFX12-GISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT:    s_cmp_lg_u32 s5, 0
; GFX12-GISEL-NEXT:    s_cselect_b32 s3, 1, 0
; GFX12-GISEL-NEXT:    s_cmp_lg_u32 s0, 0
; GFX12-GISEL-NEXT:    s_cselect_b32 s0, 1, 0
; GFX12-GISEL-NEXT:    s_cmp_lg_u32 s1, 0
; GFX12-GISEL-NEXT:    s_cselect_b32 s1, 1, 0
; GFX12-GISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT:    s_sub_co_i32 s0, s2, s0
; GFX12-GISEL-NEXT:    s_sub_co_i32 s1, s3, s1
; GFX12-GISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
  %r = call <2 x i32> @llvm.scmp.v2i32.v2i16(<2 x i16> %a, <2 x i16> %b)
  ret <2 x i32> %r
}

define <4 x i32> @scmp_v4i8_uniform(<4 x i8> inreg %a, <4 x i8> inreg %b) {
; GFX7-SDAG-LABEL: scmp_v4i8_uniform:
; GFX7-SDAG:       ; %bb.0:
; GFX7-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-SDAG-NEXT:    s_sext_i32_i8 s10, s20
; GFX7-SDAG-NEXT:    s_sext_i32_i8 s11, s16
; GFX7-SDAG-NEXT:    s_cmp_gt_i32 s11, s10
; GFX7-SDAG-NEXT:    s_sext_i32_i8 s8, s21
; GFX7-SDAG-NEXT:    s_sext_i32_i8 s9, s17
; GFX7-SDAG-NEXT:    s_cselect_b32 s12, 1, 0
; GFX7-SDAG-NEXT:    s_cmp_ge_i32 s11, s10
; GFX7-SDAG-NEXT:    s_cselect_b32 s10, s12, -1
; GFX7-SDAG-NEXT:    s_cmp_gt_i32 s9, s8
; GFX7-SDAG-NEXT:    s_sext_i32_i8 s6, s22
; GFX7-SDAG-NEXT:    s_sext_i32_i8 s7, s18
; GFX7-SDAG-NEXT:    s_cselect_b32 s11, 1, 0
; GFX7-SDAG-NEXT:    s_cmp_ge_i32 s9, s8
; GFX7-SDAG-NEXT:    s_cselect_b32 s8, s11, -1
; GFX7-SDAG-NEXT:    s_cmp_gt_i32 s7, s6
; GFX7-SDAG-NEXT:    s_sext_i32_i8 s4, s23
; GFX7-SDAG-NEXT:    s_sext_i32_i8 s5, s19
; GFX7-SDAG-NEXT:    s_cselect_b32 s9, 1, 0
; GFX7-SDAG-NEXT:    s_cmp_ge_i32 s7, s6
; GFX7-SDAG-NEXT:    s_cselect_b32 s6, s9, -1
; GFX7-SDAG-NEXT:    s_cmp_gt_i32 s5, s4
; GFX7-SDAG-NEXT:    s_cselect_b32 s7, 1, 0
; GFX7-SDAG-NEXT:    s_cmp_ge_i32 s5, s4
; GFX7-SDAG-NEXT:    s_cselect_b32 s4, s7, -1
; GFX7-SDAG-NEXT:    v_mov_b32_e32 v0, s10
; GFX7-SDAG-NEXT:    v_mov_b32_e32 v1, s8
; GFX7-SDAG-NEXT:    v_mov_b32_e32 v2, s6
; GFX7-SDAG-NEXT:    v_mov_b32_e32 v3, s4
; GFX7-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: scmp_v4i8_uniform:
; GFX7-GISEL:       ; %bb.0:
; GFX7-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT:    s_sext_i32_i8 s4, s16
; GFX7-GISEL-NEXT:    s_sext_i32_i8 s5, s20
; GFX7-GISEL-NEXT:    s_cmp_gt_i32 s4, s5
; GFX7-GISEL-NEXT:    s_sext_i32_i8 s7, s17
; GFX7-GISEL-NEXT:    s_sext_i32_i8 s8, s21
; GFX7-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
; GFX7-GISEL-NEXT:    s_cmp_gt_i32 s7, s8
; GFX7-GISEL-NEXT:    s_sext_i32_i8 s10, s18
; GFX7-GISEL-NEXT:    s_sext_i32_i8 s11, s22
; GFX7-GISEL-NEXT:    s_cselect_b32 s9, 1, 0
; GFX7-GISEL-NEXT:    s_cmp_gt_i32 s10, s11
; GFX7-GISEL-NEXT:    s_sext_i32_i8 s13, s19
; GFX7-GISEL-NEXT:    s_sext_i32_i8 s14, s23
; GFX7-GISEL-NEXT:    s_cselect_b32 s12, 1, 0
; GFX7-GISEL-NEXT:    s_cmp_gt_i32 s13, s14
; GFX7-GISEL-NEXT:    s_cselect_b32 s15, 1, 0
; GFX7-GISEL-NEXT:    s_cmp_lt_i32 s4, s5
; GFX7-GISEL-NEXT:    s_cselect_b32 s4, 1, 0
; GFX7-GISEL-NEXT:    s_cmp_lt_i32 s7, s8
; GFX7-GISEL-NEXT:    s_cselect_b32 s5, 1, 0
; GFX7-GISEL-NEXT:    s_cmp_lt_i32 s10, s11
; GFX7-GISEL-NEXT:    s_cselect_b32 s7, 1, 0
; GFX7-GISEL-NEXT:    s_cmp_lt_i32 s13, s14
; GFX7-GISEL-NEXT:    s_cselect_b32 s8, 1, 0
; GFX7-GISEL-NEXT:    s_cmp_lg_u32 s6, 0
; GFX7-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
; GFX7-GISEL-NEXT:    s_cmp_lg_u32 s9, 0
; GFX7-GISEL-NEXT:    s_cselect_b32 s9, 1, 0
; GFX7-GISEL-NEXT:    s_cmp_lg_u32 s12, 0
; GFX7-GISEL-NEXT:    s_cselect_b32 s10, 1, 0
; GFX7-GISEL-NEXT:    s_cmp_lg_u32 s15, 0
; GFX7-GISEL-NEXT:    s_cselect_b32 s11, 1, 0
; GFX7-GISEL-NEXT:    s_cmp_lg_u32 s4, 0
; GFX7-GISEL-NEXT:    s_cselect_b32 s4, 1, 0
; GFX7-GISEL-NEXT:    s_cmp_lg_u32 s5, 0
; GFX7-GISEL-NEXT:    s_cselect_b32 s5, 1, 0
; GFX7-GISEL-NEXT:    s_cmp_lg_u32 s7, 0
; GFX7-GISEL-NEXT:    s_cselect_b32 s7, 1, 0
; GFX7-GISEL-NEXT:    s_cmp_lg_u32 s8, 0
; GFX7-GISEL-NEXT:    s_cselect_b32 s8, 1, 0
; GFX7-GISEL-NEXT:    s_sub_i32 s4, s6, s4
; GFX7-GISEL-NEXT:    s_sub_i32 s5, s9, s5
; GFX7-GISEL-NEXT:    s_sub_i32 s6, s10, s7
; GFX7-GISEL-NEXT:    s_sub_i32 s7, s11, s8
; GFX7-GISEL-NEXT:    v_mov_b32_e32 v0, s4
; GFX7-GISEL-NEXT:    v_mov_b32_e32 v1, s5
; GFX7-GISEL-NEXT:    v_mov_b32_e32 v2, s6
; GFX7-GISEL-NEXT:    v_mov_b32_e32 v3, s7
; GFX7-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: scmp_v4i8_uniform:
; GFX12-SDAG:       ; %bb.0:
; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT:    s_bfe_i32 s6, s16, 0x80000
; GFX12-SDAG-NEXT:    s_bfe_i32 s0, s0, 0x80000
; GFX12-SDAG-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT:    s_sext_i32_i16 s6, s6
; GFX12-SDAG-NEXT:    s_sext_i32_i16 s0, s0
; GFX12-SDAG-NEXT:    s_bfe_i32 s3, s3, 0x80000
; GFX12-SDAG-NEXT:    s_bfe_i32 s4, s19, 0x80000
; GFX12-SDAG-NEXT:    s_bfe_i32 s2, s2, 0x80000
; GFX12-SDAG-NEXT:    s_bfe_i32 s5, s18, 0x80000
; GFX12-SDAG-NEXT:    s_bfe_i32 s1, s1, 0x80000
; GFX12-SDAG-NEXT:    s_bfe_i32 s7, s17, 0x80000
; GFX12-SDAG-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT:    s_cmp_gt_i32 s0, s6
; GFX12-SDAG-NEXT:    s_sext_i32_i16 s1, s1
; GFX12-SDAG-NEXT:    s_cselect_b32 s8, 1, 0
; GFX12-SDAG-NEXT:    s_cmp_ge_i32 s0, s6
; GFX12-SDAG-NEXT:    s_sext_i32_i16 s0, s7
; GFX12-SDAG-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT:    s_cselect_b32 s6, s8, -1
; GFX12-SDAG-NEXT:    s_cmp_gt_i32 s1, s0
; GFX12-SDAG-NEXT:    s_cselect_b32 s7, 1, 0
; GFX12-SDAG-NEXT:    s_cmp_ge_i32 s1, s0
; GFX12-SDAG-NEXT:    s_sext_i32_i16 s0, s5
; GFX12-SDAG-NEXT:    s_sext_i32_i16 s1, s2
; GFX12-SDAG-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT:    s_cselect_b32 s2, s7, -1
; GFX12-SDAG-NEXT:    s_cmp_gt_i32 s1, s0
; GFX12-SDAG-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT:    v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s2
; GFX12-SDAG-NEXT:    s_cselect_b32 s5, 1, 0
; GFX12-SDAG-NEXT:    s_cmp_ge_i32 s1, s0
; GFX12-SDAG-NEXT:    s_sext_i32_i16 s0, s4
; GFX12-SDAG-NEXT:    s_sext_i32_i16 s1, s3
; GFX12-SDAG-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT:    s_cselect_b32 s3, s5, -1
; GFX12-SDAG-NEXT:    s_cmp_gt_i32 s1, s0
; GFX12-SDAG-NEXT:    s_cselect_b32 s4, 1, 0
; GFX12-SDAG-NEXT:    s_cmp_ge_i32 s1, s0
; GFX12-SDAG-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT:    s_cselect_b32 s0, s4, -1
; GFX12-SDAG-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT:    v_dual_mov_b32 v2, s3 :: v_dual_mov_b32 v3, s0
; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: scmp_v4i8_uniform:
; GFX12-GISEL:       ; %bb.0:
; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    s_sext_i32_i8 s0, s0
; GFX12-GISEL-NEXT:    s_sext_i32_i8 s4, s16
; GFX12-GISEL-NEXT:    s_sext_i32_i8 s1, s1
; GFX12-GISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT:    s_cmp_gt_i32 s0, s4
; GFX12-GISEL-NEXT:    s_sext_i32_i8 s6, s17
; GFX12-GISEL-NEXT:    s_cselect_b32 s5, 1, 0
; GFX12-GISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT:    s_cmp_gt_i32 s1, s6
; GFX12-GISEL-NEXT:    s_sext_i32_i8 s2, s2
; GFX12-GISEL-NEXT:    s_sext_i32_i8 s8, s18
; GFX12-GISEL-NEXT:    s_cselect_b32 s7, 1, 0
; GFX12-GISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT:    s_cmp_gt_i32 s2, s8
; GFX12-GISEL-NEXT:    s_sext_i32_i8 s3, s3
; GFX12-GISEL-NEXT:    s_sext_i32_i8 s10, s19
; GFX12-GISEL-NEXT:    s_cselect_b32 s9, 1, 0
; GFX12-GISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT:    s_cmp_gt_i32 s3, s10
; GFX12-GISEL-NEXT:    s_cselect_b32 s11, 1, 0
; GFX12-GISEL-NEXT:    s_cmp_lt_i32 s0, s4
; GFX12-GISEL-NEXT:    s_cselect_b32 s0, 1, 0
; GFX12-GISEL-NEXT:    s_cmp_lt_i32 s1, s6
; GFX12-GISEL-NEXT:    s_cselect_b32 s1, 1, 0
; GFX12-GISEL-NEXT:    s_cmp_lt_i32 s2, s8
; GFX12-GISEL-NEXT:    s_cselect_b32 s2, 1, 0
; GFX12-GISEL-NEXT:    s_cmp_lt_i32 s3, s10
; GFX12-GISEL-NEXT:    s_cselect_b32 s3, 1, 0
; GFX12-GISEL-NEXT:    s_cmp_lg_u32 s5, 0
; GFX12-GISEL-NEXT:    s_cselect_b32 s4, 1, 0
; GFX12-GISEL-NEXT:    s_cmp_lg_u32 s7, 0
; GFX12-GISEL-NEXT:    s_cselect_b32 s5, 1, 0
; GFX12-GISEL-NEXT:    s_cmp_lg_u32 s9, 0
; GFX12-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
; GFX12-GISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT:    s_cmp_lg_u32 s11, 0
; GFX12-GISEL-NEXT:    s_cselect_b32 s7, 1, 0
; GFX12-GISEL-NEXT:    s_cmp_lg_u32 s0, 0
; GFX12-GISEL-NEXT:    s_cselect_b32 s0, 1, 0
; GFX12-GISEL-NEXT:    s_cmp_lg_u32 s1, 0
; GFX12-GISEL-NEXT:    s_cselect_b32 s1, 1, 0
; GFX12-GISEL-NEXT:    s_cmp_lg_u32 s2, 0
; GFX12-GISEL-NEXT:    s_cselect_b32 s2, 1, 0
; GFX12-GISEL-NEXT:    s_cmp_lg_u32 s3, 0
; GFX12-GISEL-NEXT:    s_cselect_b32 s3, 1, 0
; GFX12-GISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT:    s_sub_co_i32 s0, s4, s0
; GFX12-GISEL-NEXT:    s_sub_co_i32 s1, s5, s1
; GFX12-GISEL-NEXT:    s_sub_co_i32 s2, s6, s2
; GFX12-GISEL-NEXT:    s_sub_co_i32 s3, s7, s3
; GFX12-GISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-GISEL-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
  %r = call <4 x i32> @llvm.scmp.v4i32.v4i8(<4 x i8> %a, <4 x i8> %b)
  ret <4 x i32> %r
}