llvm/test/CodeGen/AMDGPU/s-wakeup-barrier.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX1250-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX1250-GISEL %s

@bar = internal addrspace(3) global target("amdgcn.named.barrier", 0) poison

define amdgpu_kernel void @kernel1(ptr addrspace(1) %out, ptr addrspace(3) %in) #0 {
; GFX1250-SDAG-LABEL: kernel1:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT:    s_load_b32 s0, s[4:5], 0x2c
; GFX1250-SDAG-NEXT:    s_mov_b32 m0, 1
; GFX1250-SDAG-NEXT:    s_wakeup_barrier m0
; GFX1250-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-NEXT:    s_lshr_b32 s0, s0, 4
; GFX1250-SDAG-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-SDAG-NEXT:    s_and_b32 m0, s0, 63
; GFX1250-SDAG-NEXT:    s_wakeup_barrier m0
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: kernel1:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT:    s_load_b32 s0, s[4:5], 0x2c
; GFX1250-GISEL-NEXT:    s_wakeup_barrier 1
; GFX1250-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-NEXT:    s_lshr_b32 s0, s0, 4
; GFX1250-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-GISEL-NEXT:    s_and_b32 m0, s0, 63
; GFX1250-GISEL-NEXT:    s_wakeup_barrier m0
; GFX1250-GISEL-NEXT:    s_endpgm
    call void @llvm.amdgcn.s.wakeup.barrier(ptr addrspace(3) @bar)
    call void @llvm.amdgcn.s.wakeup.barrier(ptr addrspace(3) %in)
    ret void
}


declare void @llvm.amdgcn.s.wakeup.barrier(ptr addrspace(3)) #1

attributes #0 = { nounwind }
attributes #1 = { convergent nounwind }