llvm/test/CodeGen/AMDGPU/remat-through-copy.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 --stress-regalloc=3 -run-pass=greedy,virtregrewriter -o - %s | FileCheck %s

# Test that remat is successful when there are artificial COPY instructions due to live ranges splitting

---
name: test_remat_s_add_i32
tracksRegLiveness: true
body: |
  ; CHECK-LABEL: name: test_remat_s_add_i32
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT:   liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   renamable $vgpr2 = V_OR_B32_e32 $vgpr0, $vgpr1, implicit $exec
  ; CHECK-NEXT:   renamable $vgpr0 = V_XOR_B32_e32 killed $vgpr0, killed $vgpr1, implicit $exec
  ; CHECK-NEXT:   renamable $sgpr2 = S_MOV_B32 0
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; CHECK-NEXT:   liveins: $sgpr2, $vgpr0, $vgpr2, $sgpr0_sgpr1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   renamable $sgpr4_sgpr5 = V_CMP_EQ_U32_e64 $vgpr0, $vgpr2, implicit $exec
  ; CHECK-NEXT:   S_NOP 0, implicit killed renamable $sgpr4_sgpr5, implicit renamable $sgpr0_sgpr1
  ; CHECK-NEXT:   renamable $sgpr4_sgpr5 = V_CMP_EQ_U32_e64 $vgpr0, $vgpr2, implicit $exec
  ; CHECK-NEXT:   S_NOP 0, implicit killed renamable $sgpr4_sgpr5, implicit renamable $sgpr0_sgpr1
  ; CHECK-NEXT:   renamable $sgpr4_sgpr5 = V_CMP_EQ_U32_e64 $vgpr0, $vgpr2, implicit $exec
  ; CHECK-NEXT:   S_NOP 0, implicit killed renamable $sgpr4_sgpr5, implicit renamable $sgpr0_sgpr1
  ; CHECK-NEXT:   renamable $sgpr4_sgpr5 = V_CMP_EQ_U32_e64 $vgpr0, $vgpr2, implicit $exec
  ; CHECK-NEXT:   S_NOP 0, implicit killed renamable $sgpr4_sgpr5, implicit renamable $sgpr0_sgpr1
  ; CHECK-NEXT:   renamable $sgpr4_sgpr5 = V_CMP_EQ_U32_e64 $vgpr0, $vgpr2, implicit $exec
  ; CHECK-NEXT:   S_NOP 0, implicit killed renamable $sgpr4_sgpr5, implicit renamable $sgpr0_sgpr1
  ; CHECK-NEXT:   renamable $sgpr4_sgpr5 = V_CMP_EQ_U32_e64 $vgpr0, $vgpr2, implicit $exec
  ; CHECK-NEXT:   S_NOP 0, implicit killed renamable $sgpr4_sgpr5, implicit renamable $sgpr0_sgpr1
  ; CHECK-NEXT:   renamable $sgpr2 = S_ADD_U32 killed renamable $sgpr2, 1, implicit-def $scc
  ; CHECK-NEXT:   S_CMP_LT_U32 renamable $sgpr2, 10, implicit-def $scc
  ; CHECK-NEXT:   S_CBRANCH_SCC1 %bb.1, implicit $scc
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   liveins: $vgpr0, $vgpr2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   S_NOP 0, implicit killed renamable $vgpr2, implicit killed renamable $vgpr0
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    liveins: $vgpr0, $vgpr1, $sgpr0, $sgpr1

    %in1:vgpr_32 = COPY $vgpr0
    %in2:vgpr_32 = COPY $vgpr1
    %vec0:vgpr_32 = V_OR_B32_e32 %in1, %in2, implicit $exec
    %vec1:vgpr_32 = V_XOR_B32_e32 %in1, %in2, implicit $exec
    %17:sgpr_64 = COPY $sgpr0_sgpr1

    %new_var:sreg_64 = V_CMP_EQ_U32_e64 %vec1:vgpr_32, %vec0:vgpr_32, implicit $exec
    %new_var2:sreg_64 = V_CMP_EQ_U32_e64 %vec1:vgpr_32, %vec0:vgpr_32, implicit $exec

    %i:sgpr_32 = S_MOV_B32 0
    S_BRANCH %bb.1

  bb.1:

    S_NOP 0, implicit %new_var, implicit %17

    S_NOP 0, implicit %new_var2, implicit %17

    S_NOP 0, implicit %new_var, implicit %17

    S_NOP 0, implicit %new_var2, implicit %17

    S_NOP 0, implicit %new_var, implicit %17

    S_NOP 0, implicit %new_var2, implicit %17

    %i:sgpr_32 = S_ADD_U32 %i:sgpr_32, 1, implicit-def $scc
    S_CMP_LT_U32 %i:sgpr_32, 10, implicit-def $scc
    S_CBRANCH_SCC1 %bb.1, implicit $scc

  bb.2:
    S_NOP 0, implicit %vec0, implicit %vec1
    S_ENDPGM 0
...