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llvm/llvm-project/refs/heads/main/./llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll
blob: 2df2dd63497058fb29c19fc2e7f8fcdb1876a927 [file] [edit]
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=amdgpu9.50-amd-amdhsa | FileCheck -check-prefix=GFX950 %s
; RUN: llc < %s -mtriple=amdgpu12.00-amd-amdhsa | FileCheck -check-prefix=GFX1200 %s
; RUN: llc < %s -mtriple=amdgpu12.50-amd-amdhsa -mattr=+real-true16 | FileCheck -check-prefixes=GFX1250,GFX1250-TRUE16 %s
; RUN: llc < %s -mtriple=amdgpu12.50-amd-amdhsa -mattr=-real-true16 | FileCheck -check-prefixes=GFX1250,GFX1250-FAKE16 %s
; RUN: llc < %s -mtriple=amdgpu13.10-amd-amdhsa | FileCheck -check-prefix=GFX1310 %s
; llvm.convert.to.arbitrary.fp to OCP FP8 E4M3FN and BF8 E5M2 from f32, plus
; E5M3FNU on GFX1250, lowered to packed HW instructions. The FNUZ subtargets
; are covered by float-to-arbitrary-fp-fp8-fnuz.ll.
define i8 @to_fp8_f32(float %x) {
; GFX950-LABEL: to_fp8_f32:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_cvt_pk_fp8_f32 v0, v0, v0
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: to_fp8_f32:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT: s_wait_expcnt 0x0
; GFX1200-NEXT: s_wait_samplecnt 0x0
; GFX1200-NEXT: s_wait_bvhcnt 0x0
; GFX1200-NEXT: s_wait_kmcnt 0x0
; GFX1200-NEXT: v_cvt_pk_fp8_f32 v0.l, v0, v0
; GFX1200-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-TRUE16-LABEL: to_fp8_f32:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v0.l, v0, v0
; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1250-FAKE16-LABEL: to_fp8_f32:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v0, v0, v0
; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1310-LABEL: to_fp8_f32:
; GFX1310: ; %bb.0:
; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1310-NEXT: s_wait_expcnt 0x0
; GFX1310-NEXT: s_wait_samplecnt 0x0
; GFX1310-NEXT: s_wait_bvhcnt 0x0
; GFX1310-NEXT: s_wait_kmcnt 0x0
; GFX1310-NEXT: v_cvt_pk_fp8_f32 v0, v0, v0
; GFX1310-NEXT: s_set_pc_i64 s[30:31]
%r = call i8 @llvm.convert.to.arbitrary.fp.i8.f32(float %x, metadata !"Float8E4M3FN", metadata !"round.tonearest", i1 false)
ret i8 %r
}
define i8 @to_bf8_f32(float %x) {
; GFX950-LABEL: to_bf8_f32:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_cvt_pk_bf8_f32 v0, v0, v0
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: to_bf8_f32:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT: s_wait_expcnt 0x0
; GFX1200-NEXT: s_wait_samplecnt 0x0
; GFX1200-NEXT: s_wait_bvhcnt 0x0
; GFX1200-NEXT: s_wait_kmcnt 0x0
; GFX1200-NEXT: v_cvt_pk_bf8_f32 v0.l, v0, v0
; GFX1200-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-TRUE16-LABEL: to_bf8_f32:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f32 v0.l, v0, v0
; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1250-FAKE16-LABEL: to_bf8_f32:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-FAKE16-NEXT: v_cvt_pk_bf8_f32 v0, v0, v0
; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1310-LABEL: to_bf8_f32:
; GFX1310: ; %bb.0:
; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1310-NEXT: s_wait_expcnt 0x0
; GFX1310-NEXT: s_wait_samplecnt 0x0
; GFX1310-NEXT: s_wait_bvhcnt 0x0
; GFX1310-NEXT: s_wait_kmcnt 0x0
; GFX1310-NEXT: v_cvt_pk_bf8_f32 v0, v0, v0
; GFX1310-NEXT: s_set_pc_i64 s[30:31]
%r = call i8 @llvm.convert.to.arbitrary.fp.i8.f32(float %x, metadata !"Float8E5M2", metadata !"round.tonearest", i1 false)
ret i8 %r
}
define <2 x i8> @to_fp8_v2f32(<2 x float> %x) {
; GFX950-LABEL: to_fp8_v2f32:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_cvt_pk_fp8_f32 v0, v0, v1
; GFX950-NEXT: v_lshrrev_b16_e32 v1, 8, v0
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: to_fp8_v2f32:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT: s_wait_expcnt 0x0
; GFX1200-NEXT: s_wait_samplecnt 0x0
; GFX1200-NEXT: s_wait_bvhcnt 0x0
; GFX1200-NEXT: s_wait_kmcnt 0x0
; GFX1200-NEXT: v_cvt_pk_fp8_f32 v0.l, v0, v1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_lshrrev_b16 v1.l, 8, v0.l
; GFX1200-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-TRUE16-LABEL: to_fp8_v2f32:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v0.l, v0, v1
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v1.l, 8, v0.l
; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1250-FAKE16-LABEL: to_fp8_v2f32:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v0, v0, v1
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v1, 8, v0
; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1310-LABEL: to_fp8_v2f32:
; GFX1310: ; %bb.0:
; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1310-NEXT: s_wait_expcnt 0x0
; GFX1310-NEXT: s_wait_samplecnt 0x0
; GFX1310-NEXT: s_wait_bvhcnt 0x0
; GFX1310-NEXT: s_wait_kmcnt 0x0
; GFX1310-NEXT: v_cvt_pk_fp8_f32 v0, v0, v1
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1310-NEXT: v_lshrrev_b16 v1, 8, v0
; GFX1310-NEXT: s_set_pc_i64 s[30:31]
%r = call <2 x i8> @llvm.convert.to.arbitrary.fp.v2i8.v2f32(<2 x float> %x, metadata !"Float8E4M3FN", metadata !"round.tonearest", i1 false)
ret <2 x i8> %r
}
define <2 x i8> @to_bf8_v2f32(<2 x float> %x) {
; GFX950-LABEL: to_bf8_v2f32:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_cvt_pk_bf8_f32 v0, v0, v1
; GFX950-NEXT: v_lshrrev_b16_e32 v1, 8, v0
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: to_bf8_v2f32:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT: s_wait_expcnt 0x0
; GFX1200-NEXT: s_wait_samplecnt 0x0
; GFX1200-NEXT: s_wait_bvhcnt 0x0
; GFX1200-NEXT: s_wait_kmcnt 0x0
; GFX1200-NEXT: v_cvt_pk_bf8_f32 v0.l, v0, v1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_lshrrev_b16 v1.l, 8, v0.l
; GFX1200-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-TRUE16-LABEL: to_bf8_v2f32:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f32 v0.l, v0, v1
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v1.l, 8, v0.l
; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1250-FAKE16-LABEL: to_bf8_v2f32:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-FAKE16-NEXT: v_cvt_pk_bf8_f32 v0, v0, v1
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v1, 8, v0
; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1310-LABEL: to_bf8_v2f32:
; GFX1310: ; %bb.0:
; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1310-NEXT: s_wait_expcnt 0x0
; GFX1310-NEXT: s_wait_samplecnt 0x0
; GFX1310-NEXT: s_wait_bvhcnt 0x0
; GFX1310-NEXT: s_wait_kmcnt 0x0
; GFX1310-NEXT: v_cvt_pk_bf8_f32 v0, v0, v1
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1310-NEXT: v_lshrrev_b16 v1, 8, v0
; GFX1310-NEXT: s_set_pc_i64 s[30:31]
%r = call <2 x i8> @llvm.convert.to.arbitrary.fp.v2i8.v2f32(<2 x float> %x, metadata !"Float8E5M2", metadata !"round.tonearest", i1 false)
ret <2 x i8> %r
}
define <3 x i8> @to_fp8_v3f32(<3 x float> %x) {
; GFX950-LABEL: to_fp8_v3f32:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_cvt_pk_fp8_f32 v0, v0, v0
; GFX950-NEXT: v_cvt_pk_fp8_f32 v1, v1, v1
; GFX950-NEXT: v_cvt_pk_fp8_f32 v2, v2, v2
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: to_fp8_v3f32:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT: s_wait_expcnt 0x0
; GFX1200-NEXT: s_wait_samplecnt 0x0
; GFX1200-NEXT: s_wait_bvhcnt 0x0
; GFX1200-NEXT: s_wait_kmcnt 0x0
; GFX1200-NEXT: v_cvt_pk_fp8_f32 v0.l, v0, v0
; GFX1200-NEXT: v_cvt_pk_fp8_f32 v1.l, v1, v1
; GFX1200-NEXT: v_cvt_pk_fp8_f32 v2.l, v2, v2
; GFX1200-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-TRUE16-LABEL: to_fp8_v3f32:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v0.l, v0, v0
; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v1.l, v1, v1
; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v2.l, v2, v2
; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1250-FAKE16-LABEL: to_fp8_v3f32:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v0, v0, v0
; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v1, v1, v1
; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v2, v2, v2
; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1310-LABEL: to_fp8_v3f32:
; GFX1310: ; %bb.0:
; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1310-NEXT: s_wait_expcnt 0x0
; GFX1310-NEXT: s_wait_samplecnt 0x0
; GFX1310-NEXT: s_wait_bvhcnt 0x0
; GFX1310-NEXT: s_wait_kmcnt 0x0
; GFX1310-NEXT: v_cvt_pk_fp8_f32 v0, v0, v0
; GFX1310-NEXT: v_cvt_pk_fp8_f32 v1, v1, v1
; GFX1310-NEXT: v_cvt_pk_fp8_f32 v2, v2, v2
; GFX1310-NEXT: s_set_pc_i64 s[30:31]
%r = call <3 x i8> @llvm.convert.to.arbitrary.fp.v3i8.v3f32(<3 x float> %x, metadata !"Float8E4M3FN", metadata !"round.tonearest", i1 false)
ret <3 x i8> %r
}
define <3 x i8> @to_bf8_v3f32(<3 x float> %x) {
; GFX950-LABEL: to_bf8_v3f32:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_cvt_pk_bf8_f32 v0, v0, v0
; GFX950-NEXT: v_cvt_pk_bf8_f32 v1, v1, v1
; GFX950-NEXT: v_cvt_pk_bf8_f32 v2, v2, v2
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: to_bf8_v3f32:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT: s_wait_expcnt 0x0
; GFX1200-NEXT: s_wait_samplecnt 0x0
; GFX1200-NEXT: s_wait_bvhcnt 0x0
; GFX1200-NEXT: s_wait_kmcnt 0x0
; GFX1200-NEXT: v_cvt_pk_bf8_f32 v0.l, v0, v0
; GFX1200-NEXT: v_cvt_pk_bf8_f32 v1.l, v1, v1
; GFX1200-NEXT: v_cvt_pk_bf8_f32 v2.l, v2, v2
; GFX1200-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-TRUE16-LABEL: to_bf8_v3f32:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f32 v0.l, v0, v0
; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f32 v1.l, v1, v1
; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f32 v2.l, v2, v2
; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1250-FAKE16-LABEL: to_bf8_v3f32:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-FAKE16-NEXT: v_cvt_pk_bf8_f32 v0, v0, v0
; GFX1250-FAKE16-NEXT: v_cvt_pk_bf8_f32 v1, v1, v1
; GFX1250-FAKE16-NEXT: v_cvt_pk_bf8_f32 v2, v2, v2
; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1310-LABEL: to_bf8_v3f32:
; GFX1310: ; %bb.0:
; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1310-NEXT: s_wait_expcnt 0x0
; GFX1310-NEXT: s_wait_samplecnt 0x0
; GFX1310-NEXT: s_wait_bvhcnt 0x0
; GFX1310-NEXT: s_wait_kmcnt 0x0
; GFX1310-NEXT: v_cvt_pk_bf8_f32 v0, v0, v0
; GFX1310-NEXT: v_cvt_pk_bf8_f32 v1, v1, v1
; GFX1310-NEXT: v_cvt_pk_bf8_f32 v2, v2, v2
; GFX1310-NEXT: s_set_pc_i64 s[30:31]
%r = call <3 x i8> @llvm.convert.to.arbitrary.fp.v3i8.v3f32(<3 x float> %x, metadata !"Float8E5M2", metadata !"round.tonearest", i1 false)
ret <3 x i8> %r
}
define <4 x i8> @to_fp8_v4f32(<4 x float> %x) {
; GFX950-LABEL: to_fp8_v4f32:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_cvt_pk_fp8_f32 v2, v2, v3
; GFX950-NEXT: v_cvt_pk_fp8_f32 v0, v0, v1
; GFX950-NEXT: s_mov_b32 s0, 0xff00
; GFX950-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GFX950-NEXT: v_and_or_b32 v1, v0, s0, v1
; GFX950-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX950-NEXT: v_bfe_u32 v3, v2, 8, 8
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: to_fp8_v4f32:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT: s_wait_expcnt 0x0
; GFX1200-NEXT: s_wait_samplecnt 0x0
; GFX1200-NEXT: s_wait_bvhcnt 0x0
; GFX1200-NEXT: s_wait_kmcnt 0x0
; GFX1200-NEXT: v_cvt_pk_fp8_f32 v2.l, v2, v3
; GFX1200-NEXT: v_cvt_pk_fp8_f32 v0.l, v0, v1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GFX1200-NEXT: v_bfe_u32 v3, v2, 8, 8
; GFX1200-NEXT: v_and_or_b32 v1, 0xff00, v0, v1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX1200-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-TRUE16-LABEL: to_fp8_v4f32:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v2.l, v2, v3
; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v0.l, v0, v1
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GFX1250-TRUE16-NEXT: v_bfe_u32 v3, v2, 8, 8
; GFX1250-TRUE16-NEXT: v_and_or_b32 v1, 0xff00, v0, v1
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1250-FAKE16-LABEL: to_fp8_v4f32:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v2, v2, v3
; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v0, v0, v1
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GFX1250-FAKE16-NEXT: v_bfe_u32 v3, v2, 8, 8
; GFX1250-FAKE16-NEXT: v_and_or_b32 v1, 0xff00, v0, v1
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1310-LABEL: to_fp8_v4f32:
; GFX1310: ; %bb.0:
; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1310-NEXT: s_wait_expcnt 0x0
; GFX1310-NEXT: s_wait_samplecnt 0x0
; GFX1310-NEXT: s_wait_bvhcnt 0x0
; GFX1310-NEXT: s_wait_kmcnt 0x0
; GFX1310-NEXT: v_cvt_pk_fp8_f32 v2, v2, v3
; GFX1310-NEXT: v_cvt_pk_fp8_f32 v0, v0, v1
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GFX1310-NEXT: v_bfe_u32 v3, v2, 8, 8
; GFX1310-NEXT: v_and_or_b32 v1, 0xff00, v0, v1
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1310-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX1310-NEXT: s_set_pc_i64 s[30:31]
%r = call <4 x i8> @llvm.convert.to.arbitrary.fp.v4i8.v4f32(<4 x float> %x, metadata !"Float8E4M3FN", metadata !"round.tonearest", i1 false)
ret <4 x i8> %r
}
define <4 x i8> @to_bf8_v4f32(<4 x float> %x) {
; GFX950-LABEL: to_bf8_v4f32:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_cvt_pk_bf8_f32 v2, v2, v3
; GFX950-NEXT: v_cvt_pk_bf8_f32 v0, v0, v1
; GFX950-NEXT: s_mov_b32 s0, 0xff00
; GFX950-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GFX950-NEXT: v_and_or_b32 v1, v0, s0, v1
; GFX950-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX950-NEXT: v_bfe_u32 v3, v2, 8, 8
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: to_bf8_v4f32:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT: s_wait_expcnt 0x0
; GFX1200-NEXT: s_wait_samplecnt 0x0
; GFX1200-NEXT: s_wait_bvhcnt 0x0
; GFX1200-NEXT: s_wait_kmcnt 0x0
; GFX1200-NEXT: v_cvt_pk_bf8_f32 v2.l, v2, v3
; GFX1200-NEXT: v_cvt_pk_bf8_f32 v0.l, v0, v1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GFX1200-NEXT: v_bfe_u32 v3, v2, 8, 8
; GFX1200-NEXT: v_and_or_b32 v1, 0xff00, v0, v1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX1200-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-TRUE16-LABEL: to_bf8_v4f32:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f32 v2.l, v2, v3
; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f32 v0.l, v0, v1
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GFX1250-TRUE16-NEXT: v_bfe_u32 v3, v2, 8, 8
; GFX1250-TRUE16-NEXT: v_and_or_b32 v1, 0xff00, v0, v1
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1250-FAKE16-LABEL: to_bf8_v4f32:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-FAKE16-NEXT: v_cvt_pk_bf8_f32 v2, v2, v3
; GFX1250-FAKE16-NEXT: v_cvt_pk_bf8_f32 v0, v0, v1
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GFX1250-FAKE16-NEXT: v_bfe_u32 v3, v2, 8, 8
; GFX1250-FAKE16-NEXT: v_and_or_b32 v1, 0xff00, v0, v1
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1310-LABEL: to_bf8_v4f32:
; GFX1310: ; %bb.0:
; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1310-NEXT: s_wait_expcnt 0x0
; GFX1310-NEXT: s_wait_samplecnt 0x0
; GFX1310-NEXT: s_wait_bvhcnt 0x0
; GFX1310-NEXT: s_wait_kmcnt 0x0
; GFX1310-NEXT: v_cvt_pk_bf8_f32 v2, v2, v3
; GFX1310-NEXT: v_cvt_pk_bf8_f32 v0, v0, v1
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GFX1310-NEXT: v_bfe_u32 v3, v2, 8, 8
; GFX1310-NEXT: v_and_or_b32 v1, 0xff00, v0, v1
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1310-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX1310-NEXT: s_set_pc_i64 s[30:31]
%r = call <4 x i8> @llvm.convert.to.arbitrary.fp.v4i8.v4f32(<4 x float> %x, metadata !"Float8E5M2", metadata !"round.tonearest", i1 false)
ret <4 x i8> %r
}
; Saturation is not implemented by the HW conversion, so it uses the generic
; expansion.
define i8 @to_fp8_f32_saturate(float %x) {
; GFX950-LABEL: to_fp8_f32_saturate:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
; GFX950-NEXT: v_sub_u32_e32 v2, 15, v1
; GFX950-NEXT: v_frexp_mant_f32_e32 v3, v0
; GFX950-NEXT: v_min_u32_e32 v2, 31, v2
; GFX950-NEXT: v_and_b32_e32 v4, 0x7fffff, v3
; GFX950-NEXT: v_or_b32_e32 v5, 0x800000, v4
; GFX950-NEXT: v_sub_u32_e64 v7, v2, 1 clamp
; GFX950-NEXT: v_lshrrev_b32_e32 v8, v7, v5
; GFX950-NEXT: v_bfe_u32 v7, v5, 0, v7
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; GFX950-NEXT: v_bfe_u32 v6, v5, v2, 1
; GFX950-NEXT: s_movk_i32 s0, 0x80
; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX950-NEXT: v_bitop3_b32 v6, v8, v7, v6 bitop3:0xe0
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GFX950-NEXT: v_lshrrev_b32_e32 v2, v2, v5
; GFX950-NEXT: v_and_b32_e32 v7, 0x7ffff, v3
; GFX950-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
; GFX950-NEXT: v_add_u32_e32 v2, v2, v6
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v2
; GFX950-NEXT: v_and_b32_sdwa v6, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
; GFX950-NEXT: v_bfe_u32 v4, v4, 20, 1
; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 8, vcc
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; GFX950-NEXT: v_or3_b32 v2, v6, v5, v2
; GFX950-NEXT: v_lshrrev_b32_e32 v5, 19, v3
; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX950-NEXT: v_bitop3_b32 v4, v5, v7, v4 bitop3:0xe0
; GFX950-NEXT: v_bfe_u32 v3, v3, 20, 3
; GFX950-NEXT: v_add_u32_e32 v3, v3, v4
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v3
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
; GFX950-NEXT: v_addc_co_u32_e32 v1, vcc, 6, v1, vcc
; GFX950-NEXT: v_lshlrev_b32_e32 v4, 3, v1
; GFX950-NEXT: v_or3_b32 v4, v6, v4, v3
; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, 1, v1
; GFX950-NEXT: v_cmp_eq_u32_e64 s[0:1], 15, v1
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 6, v3
; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], vcc
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 15, v1
; GFX950-NEXT: v_or_b32_e32 v1, 0x7e, v6
; GFX950-NEXT: s_or_b64 vcc, vcc, s[0:1]
; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v1, vcc
; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0
; GFX950-NEXT: s_movk_i32 s0, 0x204
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
; GFX950-NEXT: v_cmp_class_f32_e64 vcc, v0, s0
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX950-NEXT: v_mov_b32_e32 v2, 0x7f
; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: to_fp8_f32_saturate:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT: s_wait_expcnt 0x0
; GFX1200-NEXT: s_wait_samplecnt 0x0
; GFX1200-NEXT: s_wait_bvhcnt 0x0
; GFX1200-NEXT: s_wait_kmcnt 0x0
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
; GFX1200-NEXT: v_frexp_mant_f32_e32 v3, v0
; GFX1200-NEXT: s_mov_b32 s0, 0x7fffff
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_sub_nc_u32_e32 v2, 15, v1
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_and_or_b32 v4, v3, s0, 0x800000
; GFX1200-NEXT: v_and_b32_e32 v6, 0x7ffff, v3
; GFX1200-NEXT: v_bfe_u32 v8, v3, 20, 3
; GFX1200-NEXT: v_lshrrev_b32_e32 v3, 19, v3
; GFX1200-NEXT: v_min_u32_e32 v2, 31, v2
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
; GFX1200-NEXT: v_sub_nc_u32_e64 v5, v2, 1 clamp
; GFX1200-NEXT: v_lshrrev_b32_e32 v9, v2, v4
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_bfe_u32 v7, v4, 0, v5
; GFX1200-NEXT: v_lshrrev_b32_e32 v4, v5, v4
; GFX1200-NEXT: v_and_or_b32 v6, v8, 1, v6
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v7
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX1200-NEXT: v_and_or_b32 v5, v9, 1, v7
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_and_b32_e32 v4, v4, v5
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_dual_cndmask_b32 v2, 0, v4 :: v_dual_and_b32 v3, v3, v6
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_add_nc_u32_e32 v3, v8, v3
; GFX1200-NEXT: v_lshrrev_b32_e32 v4, 24, v0
; GFX1200-NEXT: v_add_nc_u32_e32 v2, v9, v2
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v3
; GFX1200-NEXT: v_and_b32_e32 v4, 0x80, v4
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo
; GFX1200-NEXT: v_add_co_ci_u32_e64 v1, null, 6, v1, vcc_lo
; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v2
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT: v_lshlrev_b32_e32 v5, 3, v1
; GFX1200-NEXT: v_cmp_gt_i32_e64 s2, 1, v1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
; GFX1200-NEXT: v_cndmask_b32_e64 v6, 0, 8, vcc_lo
; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 6, v3
; GFX1200-NEXT: v_or3_b32 v5, v4, v5, v3
; GFX1200-NEXT: v_cmp_eq_u32_e64 s0, 15, v1
; GFX1200-NEXT: v_cmp_lt_i32_e64 s1, 15, v1
; GFX1200-NEXT: v_or3_b32 v2, v4, v6, v2
; GFX1200-NEXT: s_and_b32 s0, s0, vcc_lo
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b32_e64 v1, v5, v2, s2
; GFX1200-NEXT: v_or_b32_e32 v2, 0x7e, v4
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_or_b32 vcc_lo, s1, s0
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
; GFX1200-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX1200-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x204
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
; GFX1200-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT: v_cndmask_b32_e32 v0, 0x7f, v1, vcc_lo
; GFX1200-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: to_fp8_f32_saturate:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
; GFX1250-NEXT: v_frexp_mant_f32_e32 v2, v0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX1250-NEXT: v_dual_sub_nc_u32 v3, 15, v1 :: v_dual_lshrrev_b32 v8, 19, v2
; GFX1250-NEXT: v_and_b32_e32 v4, 0x7fffff, v2
; GFX1250-NEXT: v_and_b32_e32 v7, 0x7ffff, v2
; GFX1250-NEXT: v_bfe_u32 v2, v2, 20, 3
; GFX1250-NEXT: v_min_u32_e32 v3, 31, v3
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1250-NEXT: v_or_b32_e32 v5, 0x800000, v4
; GFX1250-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v7
; GFX1250-NEXT: v_bfe_u32 v4, v4, 20, 1
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1250-NEXT: v_sub_nc_u32_e64 v6, v3, 1 clamp
; GFX1250-NEXT: v_bfe_u32 v10, v5, v3, 1
; GFX1250-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1250-NEXT: v_bfe_u32 v9, v5, 0, v6
; GFX1250-NEXT: v_dual_lshrrev_b32 v6, v6, v5 :: v_dual_lshrrev_b32 v5, v3, v5
; GFX1250-NEXT: v_bitop3_b32 v4, v8, v7, v4 bitop3:0xe0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v9
; GFX1250-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
; GFX1250-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3
; GFX1250-NEXT: v_bitop3_b32 v6, v6, v9, v10 bitop3:0xe0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_dual_cndmask_b32 v3, 0, v6 :: v_dual_add_nc_u32 v2, v2, v4
; GFX1250-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v2
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1250-NEXT: v_dual_lshrrev_b32 v4, 24, v0 :: v_dual_add_nc_u32 v3, v5, v3
; GFX1250-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
; GFX1250-NEXT: v_add_co_ci_u32_e64 v1, null, 6, v1, vcc_lo
; GFX1250-NEXT: v_and_b32_e32 v4, 0x80, v4
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v3
; GFX1250-NEXT: v_cmp_eq_u32_e64 s0, 15, v1
; GFX1250-NEXT: v_cmp_lt_i32_e64 s1, 15, v1
; GFX1250-NEXT: v_cmp_gt_i32_e64 s2, 1, v1
; GFX1250-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo
; GFX1250-NEXT: v_cndmask_b32_e64 v6, 0, 8, vcc_lo
; GFX1250-NEXT: v_cmp_lt_i32_e32 vcc_lo, 6, v2
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1250-NEXT: v_or3_b32 v3, v4, v6, v3
; GFX1250-NEXT: s_and_b32 s0, s0, vcc_lo
; GFX1250-NEXT: s_or_b32 vcc_lo, s1, s0
; GFX1250-NEXT: v_lshlrev_b32_e32 v5, 3, v1
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_or3_b32 v5, v4, v5, v2
; GFX1250-NEXT: v_or_b32_e32 v2, 0x7e, v4
; GFX1250-NEXT: v_cndmask_b32_e64 v1, v5, v3, s2
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
; GFX1250-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0
; GFX1250-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX1250-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x204
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
; GFX1250-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
; GFX1250-NEXT: v_cndmask_b32_e32 v0, 0x7f, v1, vcc_lo
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1310-LABEL: to_fp8_f32_saturate:
; GFX1310: ; %bb.0:
; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1310-NEXT: s_wait_expcnt 0x0
; GFX1310-NEXT: s_wait_samplecnt 0x0
; GFX1310-NEXT: s_wait_bvhcnt 0x0
; GFX1310-NEXT: s_wait_kmcnt 0x0
; GFX1310-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
; GFX1310-NEXT: v_frexp_mant_f32_e32 v2, v0
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX1310-NEXT: v_dual_sub_nc_u32 v3, 15, v1 :: v_dual_lshrrev_b32 v8, 19, v2
; GFX1310-NEXT: v_and_b32_e32 v4, 0x7fffff, v2
; GFX1310-NEXT: v_and_b32_e32 v7, 0x7ffff, v2
; GFX1310-NEXT: v_bfe_u32 v2, v2, 20, 3
; GFX1310-NEXT: v_min_u32_e32 v3, 31, v3
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1310-NEXT: v_or_b32_e32 v5, 0x800000, v4
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v7
; GFX1310-NEXT: v_bfe_u32 v4, v4, 20, 1
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1310-NEXT: v_sub_nc_u32_e64 v6, v3, 1 clamp
; GFX1310-NEXT: v_bfe_u32 v10, v5, v3, 1
; GFX1310-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1310-NEXT: v_bfe_u32 v9, v5, 0, v6
; GFX1310-NEXT: v_dual_lshrrev_b32 v6, v6, v5 :: v_dual_lshrrev_b32 v5, v3, v5
; GFX1310-NEXT: v_bitop3_b32 v4, v8, v7, v4 bitop3:0xe0
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v9
; GFX1310-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3
; GFX1310-NEXT: v_bitop3_b32 v6, v6, v9, v10 bitop3:0xe0
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1310-NEXT: v_dual_cndmask_b32 v3, 0, v6 :: v_dual_add_nc_u32 v2, v2, v4
; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v2
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1310-NEXT: v_dual_lshrrev_b32 v4, 24, v0 :: v_dual_add_nc_u32 v3, v5, v3
; GFX1310-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
; GFX1310-NEXT: v_add_co_ci_u32_e64 v1, null, 6, v1, vcc_lo
; GFX1310-NEXT: v_and_b32_e32 v4, 0x80, v4
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v3
; GFX1310-NEXT: v_cmp_eq_u32_e64 s0, 15, v1
; GFX1310-NEXT: v_cmp_lt_i32_e64 s1, 15, v1
; GFX1310-NEXT: v_cmp_gt_i32_e64 s2, 1, v1
; GFX1310-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo
; GFX1310-NEXT: v_cndmask_b32_e64 v6, 0, 8, vcc_lo
; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 6, v2
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1310-NEXT: v_or3_b32 v3, v4, v6, v3
; GFX1310-NEXT: s_and_b32 s0, s0, vcc_lo
; GFX1310-NEXT: s_or_b32 vcc_lo, s1, s0
; GFX1310-NEXT: v_lshlrev_b32_e32 v5, 3, v1
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_or3_b32 v5, v4, v5, v2
; GFX1310-NEXT: v_or_b32_e32 v2, 0x7e, v4
; GFX1310-NEXT: v_cndmask_b32_e64 v1, v5, v3, s2
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
; GFX1310-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0
; GFX1310-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX1310-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x204
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
; GFX1310-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
; GFX1310-NEXT: v_cndmask_b32_e32 v0, 0x7f, v1, vcc_lo
; GFX1310-NEXT: s_set_pc_i64 s[30:31]
%r = call i8 @llvm.convert.to.arbitrary.fp.i8.f32(float %x, metadata !"Float8E4M3FN", metadata !"round.tonearest", i1 true)
ret i8 %r
}
; Only round-to-nearest-even maps to the HW conversion.
define i8 @to_fp8_f32_towardzero(float %x) {
; GFX950-LABEL: to_fp8_f32_towardzero:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_frexp_mant_f32_e32 v1, v0
; GFX950-NEXT: v_bfe_u32 v2, v1, 20, 3
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v2
; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v4, v0
; GFX950-NEXT: v_and_b32_e32 v1, 0x7fffff, v1
; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
; GFX950-NEXT: v_addc_co_u32_e32 v5, vcc, 6, v4, vcc
; GFX950-NEXT: v_sub_u32_e32 v4, 15, v4
; GFX950-NEXT: v_or_b32_e32 v1, 0x800000, v1
; GFX950-NEXT: v_min_u32_e32 v4, 31, v4
; GFX950-NEXT: v_lshrrev_b32_e32 v1, v4, v1
; GFX950-NEXT: s_movk_i32 s0, 0x80
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v1
; GFX950-NEXT: v_and_b32_sdwa v3, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
; GFX950-NEXT: v_lshlrev_b32_e32 v6, 3, v5
; GFX950-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 8, vcc
; GFX950-NEXT: v_or3_b32 v2, v3, v6, v2
; GFX950-NEXT: v_or3_b32 v1, v3, v4, v1
; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, 1, v5
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0
; GFX950-NEXT: v_mov_b32_e32 v2, 0x7f
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: to_fp8_f32_towardzero:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT: s_wait_expcnt 0x0
; GFX1200-NEXT: s_wait_samplecnt 0x0
; GFX1200-NEXT: s_wait_bvhcnt 0x0
; GFX1200-NEXT: s_wait_kmcnt 0x0
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
; GFX1200-NEXT: v_frexp_mant_f32_e32 v2, v0
; GFX1200-NEXT: s_mov_b32 s0, 0x7fffff
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_sub_nc_u32_e32 v3, 15, v1
; GFX1200-NEXT: v_bfe_u32 v4, v2, 20, 3
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_and_or_b32 v2, v2, s0, 0x800000
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_min_u32_e32 v3, 31, v3
; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v4
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT: v_lshrrev_b32_e32 v2, v3, v2
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo
; GFX1200-NEXT: v_lshrrev_b32_e32 v3, 24, v0
; GFX1200-NEXT: v_add_co_ci_u32_e64 v1, null, 6, v1, vcc_lo
; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v2
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_and_b32_e32 v3, 0x80, v3
; GFX1200-NEXT: v_lshlrev_b32_e32 v5, 3, v1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
; GFX1200-NEXT: v_cndmask_b32_e64 v6, 0, 8, vcc_lo
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v1
; GFX1200-NEXT: v_or3_b32 v4, v3, v5, v4
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_or3_b32 v2, v3, v6, v2
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc_lo
; GFX1200-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX1200-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v0, 0x7f, v1, vcc_lo
; GFX1200-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: to_fp8_f32_towardzero:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_frexp_mant_f32_e32 v2, v0
; GFX1250-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
; GFX1250-NEXT: s_mov_b32 s0, 0x7fffff
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_bfe_u32 v4, v2, 20, 3
; GFX1250-NEXT: v_sub_nc_u32_e32 v3, 15, v1
; GFX1250-NEXT: v_and_or_b32 v2, v2, s0, 0x800000
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v4
; GFX1250-NEXT: v_add_co_ci_u32_e64 v1, null, 6, v1, vcc_lo
; GFX1250-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo
; GFX1250-NEXT: v_lshlrev_b32_e32 v5, 3, v1
; GFX1250-NEXT: v_min_u32_e32 v3, 31, v3
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_dual_lshrrev_b32 v2, v3, v2 :: v_dual_lshrrev_b32 v3, 24, v0
; GFX1250-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v2
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1250-NEXT: v_and_b32_e32 v3, 0x80, v3
; GFX1250-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
; GFX1250-NEXT: v_cndmask_b32_e64 v6, 0, 8, vcc_lo
; GFX1250-NEXT: v_or3_b32 v4, v3, v5, v4
; GFX1250-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v1
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_or3_b32 v2, v3, v6, v2
; GFX1250-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc_lo
; GFX1250-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX1250-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
; GFX1250-NEXT: v_cndmask_b32_e32 v0, 0x7f, v1, vcc_lo
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1310-LABEL: to_fp8_f32_towardzero:
; GFX1310: ; %bb.0:
; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1310-NEXT: s_wait_expcnt 0x0
; GFX1310-NEXT: s_wait_samplecnt 0x0
; GFX1310-NEXT: s_wait_bvhcnt 0x0
; GFX1310-NEXT: s_wait_kmcnt 0x0
; GFX1310-NEXT: v_frexp_mant_f32_e32 v2, v0
; GFX1310-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
; GFX1310-NEXT: s_mov_b32 s0, 0x7fffff
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_bfe_u32 v4, v2, 20, 3
; GFX1310-NEXT: v_sub_nc_u32_e32 v3, 15, v1
; GFX1310-NEXT: v_and_or_b32 v2, v2, s0, 0x800000
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v4
; GFX1310-NEXT: v_add_co_ci_u32_e64 v1, null, 6, v1, vcc_lo
; GFX1310-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo
; GFX1310-NEXT: v_lshlrev_b32_e32 v5, 3, v1
; GFX1310-NEXT: v_min_u32_e32 v3, 31, v3
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1310-NEXT: v_dual_lshrrev_b32 v2, v3, v2 :: v_dual_lshrrev_b32 v3, 24, v0
; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v2
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1310-NEXT: v_and_b32_e32 v3, 0x80, v3
; GFX1310-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
; GFX1310-NEXT: v_cndmask_b32_e64 v6, 0, 8, vcc_lo
; GFX1310-NEXT: v_or3_b32 v4, v3, v5, v4
; GFX1310-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v1
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1310-NEXT: v_or3_b32 v2, v3, v6, v2
; GFX1310-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc_lo
; GFX1310-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX1310-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
; GFX1310-NEXT: v_cndmask_b32_e32 v0, 0x7f, v1, vcc_lo
; GFX1310-NEXT: s_set_pc_i64 s[30:31]
%r = call i8 @llvm.convert.to.arbitrary.fp.i8.f32(float %x, metadata !"Float8E4M3FN", metadata !"round.towardzero", i1 false)
ret i8 %r
}
; FP4 has no unscaled HW conversion, only the scalef32 family, so it uses the
; generic expansion.
define i4 @to_fp4_f32(float %x) {
; GFX950-LABEL: to_fp4_f32:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
; GFX950-NEXT: v_sub_u32_e32 v2, 23, v1
; GFX950-NEXT: v_frexp_mant_f32_e32 v3, v0
; GFX950-NEXT: v_min_u32_e32 v2, 31, v2
; GFX950-NEXT: v_and_b32_e32 v4, 0x7fffff, v3
; GFX950-NEXT: v_or_b32_e32 v4, 0x800000, v4
; GFX950-NEXT: v_sub_u32_e64 v6, v2, 1 clamp
; GFX950-NEXT: v_lshrrev_b32_e32 v7, v6, v4
; GFX950-NEXT: v_bfe_u32 v6, v4, 0, v6
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; GFX950-NEXT: v_bfe_u32 v5, v4, v2, 1
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX950-NEXT: v_bitop3_b32 v5, v7, v6, v5 bitop3:0xe0
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GFX950-NEXT: v_lshrrev_b32_e32 v2, v2, v4
; GFX950-NEXT: v_and_b32_e32 v6, 0x1fffff, v3
; GFX950-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
; GFX950-NEXT: v_add_u32_e32 v2, v2, v5
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 1, v2
; GFX950-NEXT: v_lshrrev_b32_e32 v5, 28, v0
; GFX950-NEXT: v_and_b32_e32 v5, 8, v5
; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 2, vcc
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; GFX950-NEXT: v_or3_b32 v2, v5, v4, v2
; GFX950-NEXT: v_lshrrev_b32_e32 v4, 21, v3
; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX950-NEXT: v_bfe_u32 v3, v3, 22, 1
; GFX950-NEXT: v_bitop3_b32 v4, v4, v6, v3 bitop3:0xe0
; GFX950-NEXT: v_add_u32_e32 v3, v3, v4
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 1, v3
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
; GFX950-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX950-NEXT: v_lshlrev_b32_e32 v4, 1, v1
; GFX950-NEXT: v_or3_b32 v3, v5, v4, v3
; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, 1, v1
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc
; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v0, v1, v5, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: to_fp4_f32:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT: s_wait_expcnt 0x0
; GFX1200-NEXT: s_wait_samplecnt 0x0
; GFX1200-NEXT: s_wait_bvhcnt 0x0
; GFX1200-NEXT: s_wait_kmcnt 0x0
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
; GFX1200-NEXT: v_frexp_mant_f32_e32 v3, v0
; GFX1200-NEXT: s_mov_b32 s0, 0x7fffff
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_sub_nc_u32_e32 v2, 23, v1
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_and_or_b32 v4, v3, s0, 0x800000
; GFX1200-NEXT: v_bfe_u32 v8, v3, 22, 1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_min_u32_e32 v2, 31, v2
; GFX1200-NEXT: v_sub_nc_u32_e64 v5, v2, 1 clamp
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_lshrrev_b32_e32 v9, v2, v4
; GFX1200-NEXT: v_bfe_u32 v6, v4, 0, v5
; GFX1200-NEXT: v_lshrrev_b32_e32 v4, v5, v4
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX1200-NEXT: v_and_or_b32 v5, v9, 1, v6
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_and_b32_e32 v4, v4, v5
; GFX1200-NEXT: v_and_b32_e32 v7, 0x1fffff, v3
; GFX1200-NEXT: v_lshrrev_b32_e32 v3, 21, v3
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v7
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_or_b32_e32 v6, v7, v8
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc_lo
; GFX1200-NEXT: v_lshrrev_b32_e32 v4, 28, v0
; GFX1200-NEXT: v_add_nc_u32_e32 v2, v9, v2
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_and_b32_e32 v4, 8, v4
; GFX1200-NEXT: v_and_b32_e32 v3, v3, v6
; GFX1200-NEXT: v_cmp_lt_i32_e64 s0, 1, v2
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_add_nc_u32_e32 v3, v8, v3
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v2, v2, 0, s0
; GFX1200-NEXT: v_cndmask_b32_e64 v5, 0, 2, s0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 1, v3
; GFX1200-NEXT: v_or3_b32 v2, v4, v5, v2
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX1200-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_lshlrev_b32_e32 v6, 1, v1
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v1
; GFX1200-NEXT: v_or3_b32 v3, v4, v6, v3
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo
; GFX1200-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v0, v1, v4, vcc_lo
; GFX1200-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: to_fp4_f32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
; GFX1250-NEXT: v_frexp_mant_f32_e32 v3, v0
; GFX1250-NEXT: s_mov_b32 s0, 0x7fffff
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX1250-NEXT: v_dual_sub_nc_u32 v2, 23, v1 :: v_dual_lshrrev_b32 v6, 21, v3
; GFX1250-NEXT: v_and_or_b32 v4, v3, s0, 0x800000
; GFX1250-NEXT: v_and_b32_e32 v8, 0x1fffff, v3
; GFX1250-NEXT: v_bfe_u32 v3, v3, 22, 1
; GFX1250-NEXT: v_min_u32_e32 v2, 31, v2
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_sub_nc_u32_e64 v5, v2, 1 clamp
; GFX1250-NEXT: v_bfe_u32 v9, v4, v2, 1
; GFX1250-NEXT: v_bfe_u32 v7, v4, 0, v5
; GFX1250-NEXT: v_dual_lshrrev_b32 v5, v5, v4 :: v_dual_lshrrev_b32 v4, v2, v4
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v7
; GFX1250-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX1250-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; GFX1250-NEXT: v_bitop3_b32 v5, v5, v7, v9 bitop3:0xe0
; GFX1250-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX1250-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_bitop3_b32 v6, v6, v8, v3 bitop3:0xe0
; GFX1250-NEXT: v_dual_cndmask_b32 v2, 0, v5 :: v_dual_add_nc_u32 v3, v3, v6
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_dual_add_nc_u32 v2, v4, v2 :: v_dual_lshrrev_b32 v4, 28, v0
; GFX1250-NEXT: v_cmp_lt_i32_e32 vcc_lo, 1, v3
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX1250-NEXT: v_cmp_lt_i32_e64 s0, 1, v2
; GFX1250-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX1250-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo
; GFX1250-NEXT: v_and_b32_e32 v4, 8, v4
; GFX1250-NEXT: v_cndmask_b32_e64 v2, v2, 0, s0
; GFX1250-NEXT: v_cndmask_b32_e64 v5, 0, 2, s0
; GFX1250-NEXT: v_lshlrev_b32_e32 v6, 1, v1
; GFX1250-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v1
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-NEXT: v_or3_b32 v2, v4, v5, v2
; GFX1250-NEXT: v_or3_b32 v3, v4, v6, v3
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo
; GFX1250-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0
; GFX1250-NEXT: v_cndmask_b32_e32 v0, v1, v4, vcc_lo
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1310-LABEL: to_fp4_f32:
; GFX1310: ; %bb.0:
; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1310-NEXT: s_wait_expcnt 0x0
; GFX1310-NEXT: s_wait_samplecnt 0x0
; GFX1310-NEXT: s_wait_bvhcnt 0x0
; GFX1310-NEXT: s_wait_kmcnt 0x0
; GFX1310-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
; GFX1310-NEXT: v_frexp_mant_f32_e32 v3, v0
; GFX1310-NEXT: s_mov_b32 s0, 0x7fffff
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX1310-NEXT: v_dual_sub_nc_u32 v2, 23, v1 :: v_dual_lshrrev_b32 v6, 21, v3
; GFX1310-NEXT: v_and_or_b32 v4, v3, s0, 0x800000
; GFX1310-NEXT: v_and_b32_e32 v8, 0x1fffff, v3
; GFX1310-NEXT: v_bfe_u32 v3, v3, 22, 1
; GFX1310-NEXT: v_min_u32_e32 v2, 31, v2
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_sub_nc_u32_e64 v5, v2, 1 clamp
; GFX1310-NEXT: v_bfe_u32 v9, v4, v2, 1
; GFX1310-NEXT: v_bfe_u32 v7, v4, 0, v5
; GFX1310-NEXT: v_dual_lshrrev_b32 v5, v5, v4 :: v_dual_lshrrev_b32 v4, v2, v4
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v7
; GFX1310-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; GFX1310-NEXT: v_bitop3_b32 v5, v5, v7, v9 bitop3:0xe0
; GFX1310-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1310-NEXT: v_bitop3_b32 v6, v6, v8, v3 bitop3:0xe0
; GFX1310-NEXT: v_dual_cndmask_b32 v2, 0, v5 :: v_dual_add_nc_u32 v3, v3, v6
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_dual_add_nc_u32 v2, v4, v2 :: v_dual_lshrrev_b32 v4, 28, v0
; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 1, v3
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX1310-NEXT: v_cmp_lt_i32_e64 s0, 1, v2
; GFX1310-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX1310-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo
; GFX1310-NEXT: v_and_b32_e32 v4, 8, v4
; GFX1310-NEXT: v_cndmask_b32_e64 v2, v2, 0, s0
; GFX1310-NEXT: v_cndmask_b32_e64 v5, 0, 2, s0
; GFX1310-NEXT: v_lshlrev_b32_e32 v6, 1, v1
; GFX1310-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v1
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1310-NEXT: v_or3_b32 v2, v4, v5, v2
; GFX1310-NEXT: v_or3_b32 v3, v4, v6, v3
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo
; GFX1310-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0
; GFX1310-NEXT: v_cndmask_b32_e32 v0, v1, v4, vcc_lo
; GFX1310-NEXT: s_set_pc_i64 s[30:31]
%r = call i4 @llvm.convert.to.arbitrary.fp.i4.f32(float %x, metadata !"Float4E2M1FN", metadata !"round.tonearest", i1 false)
ret i4 %r
}
; f64 source has no HW conversion, so it uses the generic expansion.
define i8 @to_fp8_f64(double %x) {
; GFX950-LABEL: to_fp8_f64:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_frexp_exp_i32_f64_e32 v2, v[0:1]
; GFX950-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX950-NEXT: v_sub_co_u32_e32 v4, vcc, 37, v2
; GFX950-NEXT: v_frexp_mant_f64_e32 v[10:11], v[0:1]
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_subb_co_u32_e32 v5, vcc, 0, v3, vcc
; GFX950-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[4:5]
; GFX950-NEXT: v_and_b32_e32 v14, 0xfffff, v11
; GFX950-NEXT: v_or_b32_e32 v13, 0x100000, v14
; GFX950-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
; GFX950-NEXT: v_cndmask_b32_e32 v4, 63, v4, vcc
; GFX950-NEXT: v_cmp_lt_u64_e32 vcc, 1, v[4:5]
; GFX950-NEXT: v_mov_b32_e32 v12, v10
; GFX950-NEXT: v_mov_b32_e32 v7, 0
; GFX950-NEXT: v_cndmask_b32_e32 v6, 1, v4, vcc
; GFX950-NEXT: v_add_u32_e32 v6, -1, v6
; GFX950-NEXT: v_lshlrev_b64 v[8:9], v6, 1
; GFX950-NEXT: v_lshl_add_u64 v[8:9], v[8:9], 0, -1
; GFX950-NEXT: v_and_b32_e32 v9, v13, v9
; GFX950-NEXT: v_and_b32_e32 v8, v10, v8
; GFX950-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9]
; GFX950-NEXT: v_lshrrev_b64 v[8:9], v4, v[12:13]
; GFX950-NEXT: v_and_b32_e32 v16, 1, v8
; GFX950-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; GFX950-NEXT: v_or_b32_e32 v15, v15, v16
; GFX950-NEXT: v_lshrrev_b64 v[12:13], v6, v[12:13]
; GFX950-NEXT: v_and_b32_e32 v6, v12, v15
; GFX950-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
; GFX950-NEXT: s_movk_i32 s1, 0x80
; GFX950-NEXT: s_mov_b32 s0, 0
; GFX950-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
; GFX950-NEXT: v_lshl_add_u64 v[4:5], v[8:9], 0, v[6:7]
; GFX950-NEXT: v_cmp_lt_i64_e32 vcc, 3, v[4:5]
; GFX950-NEXT: v_and_b32_sdwa v8, v1, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 4, vcc
; GFX950-NEXT: v_or3_b32 v9, v8, v5, v4
; GFX950-NEXT: v_and_b32_e32 v5, 0x1ffff, v11
; GFX950-NEXT: v_mov_b32_e32 v4, v10
; GFX950-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
; GFX950-NEXT: v_bfe_u32 v5, v14, 18, 1
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX950-NEXT: v_or_b32_e32 v4, v4, v5
; GFX950-NEXT: v_lshrrev_b32_e32 v5, 17, v11
; GFX950-NEXT: v_and_b32_e32 v6, v5, v4
; GFX950-NEXT: v_bfe_u32 v4, v11, 18, 2
; GFX950-NEXT: v_mov_b32_e32 v5, v7
; GFX950-NEXT: v_lshl_add_u64 v[4:5], v[4:5], 0, v[6:7]
; GFX950-NEXT: v_cmp_lt_i64_e32 vcc, 3, v[4:5]
; GFX950-NEXT: v_mov_b32_e32 v7, s0
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX950-NEXT: v_lshl_add_u64 v[2:3], v[2:3], 0, v[6:7]
; GFX950-NEXT: v_lshl_add_u64 v[2:3], v[2:3], 0, 14
; GFX950-NEXT: v_lshlrev_b64 v[6:7], 2, v[2:3]
; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
; GFX950-NEXT: v_or_b32_e32 v6, v6, v8
; GFX950-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
; GFX950-NEXT: v_or_b32_e32 v6, v6, v4
; GFX950-NEXT: v_cmp_gt_i64_e32 vcc, 1, v[2:3]
; GFX950-NEXT: v_cmp_eq_u64_e64 s[0:1], 30, v[2:3]
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc
; GFX950-NEXT: v_cmp_lt_i64_e32 vcc, 3, v[4:5]
; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], vcc
; GFX950-NEXT: v_cmp_lt_i64_e32 vcc, 30, v[2:3]
; GFX950-NEXT: v_or_b32_e32 v2, 0x7c, v8
; GFX950-NEXT: s_or_b64 vcc, vcc, s[0:1]
; GFX950-NEXT: v_cndmask_b32_e32 v3, v6, v2, vcc
; GFX950-NEXT: v_cmp_eq_f64_e32 vcc, 0, v[0:1]
; GFX950-NEXT: s_movk_i32 s0, 0x204
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
; GFX950-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], s0
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX950-NEXT: v_mov_b32_e32 v3, 0x7e
; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[0:1]
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: to_fp8_f64:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT: s_wait_expcnt 0x0
; GFX1200-NEXT: s_wait_samplecnt 0x0
; GFX1200-NEXT: s_wait_bvhcnt 0x0
; GFX1200-NEXT: s_wait_kmcnt 0x0
; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v12, v[0:1]
; GFX1200-NEXT: v_frexp_mant_f64_e32 v[2:3], v[0:1]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_ashrrev_i32_e32 v13, 31, v12
; GFX1200-NEXT: v_sub_co_u32 v4, vcc_lo, 37, v12
; GFX1200-NEXT: v_dual_mov_b32 v6, v2 :: v_dual_and_b32 v9, 0xfffff, v3
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX1200-NEXT: v_sub_co_ci_u32_e64 v5, null, 0, v13, vcc_lo
; GFX1200-NEXT: v_lshrrev_b32_e32 v15, 17, v3
; GFX1200-NEXT: v_bfe_u32 v17, v3, 18, 2
; GFX1200-NEXT: v_bfe_u32 v11, v9, 18, 1
; GFX1200-NEXT: v_cmp_gt_u64_e32 vcc_lo, 63, v[4:5]
; GFX1200-NEXT: v_or_b32_e32 v9, 0x100000, v9
; GFX1200-NEXT: v_and_b32_e32 v7, 0x1ffff, v3
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_dual_cndmask_b32 v5, 0, v5 :: v_dual_cndmask_b32 v4, 63, v4
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cmp_lt_u64_e32 vcc_lo, 1, v[4:5]
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v8, 1, v4, vcc_lo
; GFX1200-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[6:7]
; GFX1200-NEXT: v_add_nc_u32_e32 v14, -1, v8
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_lshlrev_b64_e64 v[6:7], v14, 1
; GFX1200-NEXT: v_or_b32_e32 v10, v10, v11
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_add_co_u32 v11, vcc_lo, v6, -1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_add_co_ci_u32_e64 v16, null, -1, v7, vcc_lo
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX1200-NEXT: v_and_b32_e32 v10, v15, v10
; GFX1200-NEXT: v_mov_b32_e32 v8, v2
; GFX1200-NEXT: v_and_b32_e32 v2, v2, v11
; GFX1200-NEXT: v_and_b32_e32 v3, v9, v16
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-NEXT: v_add_co_u32 v10, s0, v17, v10
; GFX1200-NEXT: v_lshrrev_b64 v[6:7], v4, v[8:9]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX1200-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[2:3]
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_add_co_ci_u32_e64 v11, null, 0, 0, s0
; GFX1200-NEXT: v_lshrrev_b64 v[2:3], v14, v[8:9]
; GFX1200-NEXT: v_and_b32_e32 v15, 1, v6
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo
; GFX1200-NEXT: v_cmp_lt_i64_e32 vcc_lo, 3, v[10:11]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT: v_or_b32_e32 v8, v16, v15
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
; GFX1200-NEXT: v_cndmask_b32_e64 v3, v11, 0, vcc_lo
; GFX1200-NEXT: v_lshrrev_b32_e32 v11, 24, v1
; GFX1200-NEXT: v_and_b32_e32 v2, v2, v8
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_add_co_u32 v8, s0, v12, v9
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v13, s0
; GFX1200-NEXT: v_cmp_ne_u64_e64 s0, 0, v[4:5]
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v2, 0, v2, s0
; GFX1200-NEXT: v_add_co_u32 v4, s0, v8, 14
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v9, s0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_add_co_u32 v6, s0, v6, v2
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, s0
; GFX1200-NEXT: v_lshlrev_b64_e32 v[8:9], 2, v[4:5]
; GFX1200-NEXT: v_and_b32_e32 v9, 0x80, v11
; GFX1200-NEXT: v_cndmask_b32_e64 v2, v10, 0, vcc_lo
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX1200-NEXT: v_cmp_lt_i64_e64 s0, 3, v[6:7]
; GFX1200-NEXT: v_cmp_gt_i64_e64 s2, 1, v[4:5]
; GFX1200-NEXT: v_cmp_lt_i64_e64 s1, 30, v[4:5]
; GFX1200-NEXT: v_or_b32_e32 v7, v8, v9
; GFX1200-NEXT: v_cmp_lt_i64_e32 vcc_lo, 3, v[2:3]
; GFX1200-NEXT: v_or_b32_e32 v3, 0x7c, v9
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v6, v6, 0, s0
; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 4, s0
; GFX1200-NEXT: v_or_b32_e32 v7, v7, v2
; GFX1200-NEXT: v_cmp_eq_u64_e64 s0, 30, v[4:5]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_or3_b32 v6, v9, v8, v6
; GFX1200-NEXT: s_and_b32 s0, s0, vcc_lo
; GFX1200-NEXT: v_cndmask_b32_e64 v2, v7, v6, s2
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_or_b32 vcc_lo, s1, s0
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX1200-NEXT: v_cmp_eq_f64_e32 vcc_lo, 0, v[0:1]
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
; GFX1200-NEXT: v_cmp_class_f64_e64 vcc_lo, v[0:1], 0x204
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX1200-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[0:1]
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v0, 0x7e, v2, vcc_lo
; GFX1200-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: to_fp8_f64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_frexp_exp_i32_f64_e32 v2, v[0:1]
; GFX1250-NEXT: v_frexp_mant_f64_e32 v[4:5], v[0:1]
; GFX1250-NEXT: s_mov_b32 s0, 0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX1250-NEXT: v_and_b32_e32 v15, 0xfffff, v5
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-NEXT: v_mov_b32_e32 v10, v4
; GFX1250-NEXT: v_sub_nc_u64_e32 v[6:7], 37, v[2:3]
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_or_b32_e32 v11, 0x100000, v15
; GFX1250-NEXT: v_cmp_gt_u64_e32 vcc_lo, 63, v[6:7]
; GFX1250-NEXT: v_dual_cndmask_b32 v7, 0, v7 :: v_dual_cndmask_b32 v6, 63, v6
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_cmp_lt_u64_e32 vcc_lo, 1, v[6:7]
; GFX1250-NEXT: v_cndmask_b32_e32 v8, 1, v6, vcc_lo
; GFX1250-NEXT: v_add_nc_u32_e32 v14, -1, v8
; GFX1250-NEXT: v_lshrrev_b64 v[12:13], v6, v[10:11]
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_lshlrev_b64_e64 v[8:9], v14, 1
; GFX1250-NEXT: v_and_b32_e32 v16, 1, v12
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_add_nc_u64_e32 v[8:9], -1, v[8:9]
; GFX1250-NEXT: v_and_b32_e32 v9, v11, v9
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1250-NEXT: v_and_b32_e32 v8, v4, v8
; GFX1250-NEXT: v_lshrrev_b64 v[10:11], v14, v[10:11]
; GFX1250-NEXT: v_lshrrev_b32_e32 v14, 17, v5
; GFX1250-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[8:9]
; GFX1250-NEXT: v_and_b32_e32 v9, 0x1ffff, v5
; GFX1250-NEXT: v_mov_b32_e32 v8, v4
; GFX1250-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[8:9]
; GFX1250-NEXT: v_dual_mov_b32 v9, 0 :: v_dual_bitop2_b32 v4, v17, v16 bitop3:0x54
; GFX1250-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
; GFX1250-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[6:7]
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_dual_mov_b32 v7, v9 :: v_dual_bitop2_b32 v4, v10, v4 bitop3:0x40
; GFX1250-NEXT: v_bfe_u32 v10, v15, 18, 1
; GFX1250-NEXT: v_bfe_u32 v6, v5, 18, 2
; GFX1250-NEXT: v_dual_cndmask_b32 v8, 0, v4, vcc_lo :: v_dual_bitop2_b32 v10, v11, v10 bitop3:0x54
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_add_nc_u64_e32 v[4:5], v[12:13], v[8:9]
; GFX1250-NEXT: v_dual_lshrrev_b32 v10, 24, v1 :: v_dual_bitop2_b32 v8, v14, v10 bitop3:0x40
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1250-NEXT: v_add_nc_u64_e32 v[6:7], v[6:7], v[8:9]
; GFX1250-NEXT: v_mov_b32_e32 v9, s0
; GFX1250-NEXT: v_cmp_lt_i64_e64 s0, 3, v[4:5]
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1250-NEXT: v_and_b32_e32 v5, 0x80, v10
; GFX1250-NEXT: v_cmp_lt_i64_e32 vcc_lo, 3, v[6:7]
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX1250-NEXT: v_cndmask_b32_e64 v4, v4, 0, s0
; GFX1250-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX1250-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc_lo
; GFX1250-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc_lo
; GFX1250-NEXT: v_add_nc_u64_e32 v[2:3], v[2:3], v[8:9]
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_cmp_lt_i64_e32 vcc_lo, 3, v[6:7]
; GFX1250-NEXT: v_add_nc_u64_e32 v[2:3], 14, v[2:3]
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_lshlrev_b64_e32 v[8:9], 2, v[2:3]
; GFX1250-NEXT: v_cndmask_b32_e64 v9, 0, 4, s0
; GFX1250-NEXT: v_cmp_eq_u64_e64 s0, 30, v[2:3]
; GFX1250-NEXT: v_cmp_lt_i64_e64 s1, 30, v[2:3]
; GFX1250-NEXT: v_cmp_gt_i64_e64 s2, 1, v[2:3]
; GFX1250-NEXT: v_or_b32_e32 v3, 0x7c, v5
; GFX1250-NEXT: v_or3_b32 v4, v5, v9, v4
; GFX1250-NEXT: s_and_b32 s0, s0, vcc_lo
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1250-NEXT: s_or_b32 vcc_lo, s1, s0
; GFX1250-NEXT: v_or_b32_e32 v8, v8, v5
; GFX1250-NEXT: v_or_b32_e32 v8, v8, v6
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_cndmask_b32_e64 v2, v8, v4, s2
; GFX1250-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX1250-NEXT: v_cmp_eq_f64_e32 vcc_lo, 0, v[0:1]
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
; GFX1250-NEXT: v_cmp_class_f64_e64 vcc_lo, v[0:1], 0x204
; GFX1250-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX1250-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[0:1]
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1250-NEXT: v_cndmask_b32_e32 v0, 0x7e, v2, vcc_lo
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1310-LABEL: to_fp8_f64:
; GFX1310: ; %bb.0:
; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1310-NEXT: s_wait_expcnt 0x0
; GFX1310-NEXT: s_wait_samplecnt 0x0
; GFX1310-NEXT: s_wait_bvhcnt 0x0
; GFX1310-NEXT: s_wait_kmcnt 0x0
; GFX1310-NEXT: v_frexp_exp_i32_f64_e32 v12, v[0:1]
; GFX1310-NEXT: v_frexp_mant_f64_e32 v[2:3], v[0:1]
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1310-NEXT: v_ashrrev_i32_e32 v13, 31, v12
; GFX1310-NEXT: v_sub_co_u32 v4, vcc_lo, 37, v12
; GFX1310-NEXT: v_and_b32_e32 v7, 0x1ffff, v3
; GFX1310-NEXT: v_and_b32_e32 v9, 0xfffff, v3
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX1310-NEXT: v_sub_co_ci_u32_e64 v5, null, 0, v13, vcc_lo
; GFX1310-NEXT: v_bfe_u32 v17, v3, 18, 2
; GFX1310-NEXT: v_mov_b32_e32 v6, v2
; GFX1310-NEXT: v_bfe_u32 v11, v9, 18, 1
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1310-NEXT: v_cmp_gt_u64_e32 vcc_lo, 63, v[4:5]
; GFX1310-NEXT: v_or_b32_e32 v9, 0x100000, v9
; GFX1310-NEXT: v_dual_lshrrev_b32 v15, 17, v3 :: v_dual_cndmask_b32 v5, 0, v5, vcc_lo
; GFX1310-NEXT: v_cndmask_b32_e32 v4, 63, v4, vcc_lo
; GFX1310-NEXT: v_cmp_lt_u64_e32 vcc_lo, 1, v[4:5]
; GFX1310-NEXT: v_cndmask_b32_e32 v8, 1, v4, vcc_lo
; GFX1310-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[6:7]
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_dual_add_nc_u32 v14, -1, v8 :: v_dual_mov_b32 v8, v2
; GFX1310-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
; GFX1310-NEXT: v_lshlrev_b64_e64 v[6:7], v14, 1
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_or_b32_e32 v10, v10, v11
; GFX1310-NEXT: v_add_co_u32 v11, vcc_lo, v6, -1
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1310-NEXT: v_add_co_ci_u32_e64 v16, null, -1, v7, vcc_lo
; GFX1310-NEXT: v_and_b32_e32 v10, v15, v10
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1310-NEXT: v_and_b32_e32 v2, v2, v11
; GFX1310-NEXT: v_lshrrev_b64 v[6:7], v4, v[8:9]
; GFX1310-NEXT: v_and_b32_e32 v3, v9, v16
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1310-NEXT: v_add_co_u32 v10, s0, v17, v10
; GFX1310-NEXT: v_add_co_ci_u32_e64 v11, null, 0, 0, s0
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[2:3]
; GFX1310-NEXT: v_and_b32_e32 v15, 1, v6
; GFX1310-NEXT: v_lshrrev_b64 v[2:3], v14, v[8:9]
; GFX1310-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo
; GFX1310-NEXT: v_cmp_lt_i64_e32 vcc_lo, 3, v[10:11]
; GFX1310-NEXT: v_or_b32_e32 v8, v16, v15
; GFX1310-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
; GFX1310-NEXT: v_cndmask_b32_e64 v3, v11, 0, vcc_lo
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1310-NEXT: v_dual_lshrrev_b32 v11, 24, v1 :: v_dual_bitop2_b32 v2, v2, v8 bitop3:0x40
; GFX1310-NEXT: v_add_co_u32 v8, s0, v12, v9
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1310-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v13, s0
; GFX1310-NEXT: v_cmp_ne_u64_e64 s0, 0, v[4:5]
; GFX1310-NEXT: v_cndmask_b32_e64 v2, 0, v2, s0
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1310-NEXT: v_add_co_u32 v4, s0, v8, 14
; GFX1310-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v9, s0
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1310-NEXT: v_add_co_u32 v6, s0, v6, v2
; GFX1310-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, s0
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX1310-NEXT: v_lshlrev_b64_e32 v[8:9], 2, v[4:5]
; GFX1310-NEXT: v_and_b32_e32 v9, 0x80, v11
; GFX1310-NEXT: v_cndmask_b32_e64 v2, v10, 0, vcc_lo
; GFX1310-NEXT: v_cmp_lt_i64_e64 s0, 3, v[6:7]
; GFX1310-NEXT: v_cmp_gt_i64_e64 s2, 1, v[4:5]
; GFX1310-NEXT: v_cmp_lt_i64_e64 s1, 30, v[4:5]
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX1310-NEXT: v_cmp_lt_i64_e32 vcc_lo, 3, v[2:3]
; GFX1310-NEXT: v_or_b32_e32 v3, 0x7c, v9
; GFX1310-NEXT: v_or_b32_e32 v7, v8, v9
; GFX1310-NEXT: v_cndmask_b32_e64 v6, v6, 0, s0
; GFX1310-NEXT: v_cndmask_b32_e64 v8, 0, 4, s0
; GFX1310-NEXT: v_cmp_eq_u64_e64 s0, 30, v[4:5]
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1310-NEXT: v_or_b32_e32 v7, v7, v2
; GFX1310-NEXT: v_or3_b32 v6, v9, v8, v6
; GFX1310-NEXT: s_and_b32 s0, s0, vcc_lo
; GFX1310-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1310-NEXT: s_or_b32 vcc_lo, s1, s0
; GFX1310-NEXT: v_cndmask_b32_e64 v2, v7, v6, s2
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX1310-NEXT: v_cmp_eq_f64_e32 vcc_lo, 0, v[0:1]
; GFX1310-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
; GFX1310-NEXT: v_cmp_class_f64_e64 vcc_lo, v[0:1], 0x204
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX1310-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[0:1]
; GFX1310-NEXT: v_cndmask_b32_e32 v0, 0x7e, v2, vcc_lo
; GFX1310-NEXT: s_set_pc_i64 s[30:31]
%r = call i8 @llvm.convert.to.arbitrary.fp.i8.f64(double %x, metadata !"Float8E5M2", metadata !"round.tonearest", i1 false)
ret i8 %r
}
; bf16 source has no HW conversion, so it uses the generic expansion.
define i8 @to_fp8_bf16(bfloat %x) {
; GFX950-LABEL: to_fp8_bf16:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_lshlrev_b32_e32 v1, 16, v0
; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v5, v1
; GFX950-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX950-NEXT: v_xor_b32_e32 v6, -1, v5
; GFX950-NEXT: v_cvt_pk_bf16_f32 v2, v2, s0
; GFX950-NEXT: s_movk_i32 s0, 0x80
; GFX950-NEXT: v_mov_b32_e32 v3, 0x7f
; GFX950-NEXT: v_min_u16_e32 v6, 15, v6
; GFX950-NEXT: v_bitop3_b16 v4, v2, s0, v3 bitop3:0xec
; GFX950-NEXT: v_sub_u16_e64 v9, v6, 1 clamp
; GFX950-NEXT: v_lshrrev_b16_e32 v7, v6, v4
; GFX950-NEXT: v_lshrrev_b16_e32 v4, v9, v4
; GFX950-NEXT: v_lshlrev_b16_e64 v9, v9, 1
; GFX950-NEXT: v_and_b32_e32 v10, 0x7f, v2
; GFX950-NEXT: v_add_u16_e32 v9, -1, v9
; GFX950-NEXT: v_bitop3_b16 v9, v10, v9, s0 bitop3:0xc8
; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
; GFX950-NEXT: v_and_b32_e32 v8, 1, v7
; GFX950-NEXT: v_and_b32_sdwa v0, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GFX950-NEXT: v_bitop3_b16 v4, v4, v9, v8 bitop3:0xe0
; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v6
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
; GFX950-NEXT: v_add_u16_e32 v4, v7, v4
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v4
; GFX950-NEXT: v_lshrrev_b16_e32 v7, 4, v10
; GFX950-NEXT: v_and_b32_e32 v8, 1, v7
; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 8, vcc
; GFX950-NEXT: v_bitop3_b16 v4, v0, v4, v6 bitop3:0xfe
; GFX950-NEXT: v_lshrrev_b16_e32 v6, 3, v2
; GFX950-NEXT: v_and_b32_e32 v2, 7, v2
; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v2
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX950-NEXT: v_bitop3_b16 v2, v6, v2, v8 bitop3:0xe0
; GFX950-NEXT: v_add_u16_e32 v2, v7, v2
; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v2
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX950-NEXT: v_add_u16_e32 v5, v5, v6
; GFX950-NEXT: v_add_u16_e32 v5, 6, v5
; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
; GFX950-NEXT: v_lshlrev_b16_e32 v6, 3, v5
; GFX950-NEXT: v_bitop3_b16 v2, v0, v2, v6 bitop3:0xfe
; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v5
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v1, v1
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: to_fp8_bf16:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT: s_wait_expcnt 0x0
; GFX1200-NEXT: s_wait_samplecnt 0x0
; GFX1200-NEXT: s_wait_bvhcnt 0x0
; GFX1200-NEXT: s_wait_kmcnt 0x0
; GFX1200-NEXT: v_lshlrev_b32_e32 v5, 16, v0
; GFX1200-NEXT: v_lshrrev_b16 v0.l, 8, v0.l
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_frexp_mant_f32_e32 v2, v5
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v6, v5
; GFX1200-NEXT: v_and_b16 v0.l, 0x80, v0.l
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_bfe_u32 v3, v2, 16, 1
; GFX1200-NEXT: v_xor_b16 v1.l, v6.l, -1
; GFX1200-NEXT: v_or_b32_e32 v4, 0x400000, v2
; GFX1200-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
; GFX1200-NEXT: v_min_u16 v1.l, v1.l, 15
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cndmask_b32_e32 v7, v3, v4, vcc_lo
; GFX1200-NEXT: v_sub_nc_u16 v1.h, v1.l, 1 clamp
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_lshrrev_b32_e32 v3, 16, v7
; GFX1200-NEXT: v_lshlrev_b16 v2.l, v1.h, 1
; GFX1200-NEXT: v_lshrrev_b32_e32 v7, 19, v7
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1200-NEXT: v_and_b16 v2.h, 0x7f, v3.l
; GFX1200-NEXT: v_and_b16 v3.l, v3.l, 7
; GFX1200-NEXT: v_add_nc_u16 v2.l, v2.l, -1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1200-NEXT: v_or_b16 v3.h, 0x80, v2.h
; GFX1200-NEXT: v_lshrrev_b16 v2.h, 4, v2.h
; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v3.l
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_and_b16 v2.l, v3.h, v2.l
; GFX1200-NEXT: v_and_b16 v3.l, v2.h, 1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; GFX1200-NEXT: v_lshrrev_b16 v4.h, v1.l, v3.h
; GFX1200-NEXT: v_lshrrev_b16 v1.h, v1.h, v3.h
; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v2.l
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-NEXT: v_or_b16 v2.l, v4.l, v3.l
; GFX1200-NEXT: v_and_b16 v3.l, v4.h, 1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v1.l
; GFX1200-NEXT: v_and_b16 v2.l, v7.l, v2.l
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_mov_b16_e32 v4.l, v8.l
; GFX1200-NEXT: v_add_nc_u16 v2.l, v2.h, v2.l
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_or_b16 v3.l, v4.l, v3.l
; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v2.l
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_and_b16 v1.l, v1.h, v3.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, 0, s0
; GFX1200-NEXT: v_cmp_eq_f32_e64 s0, 0, v5
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b16 v1.l, 0, v1.l, vcc_lo
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_add_nc_u16 v0.h, v4.h, v1.l
; GFX1200-NEXT: v_add_nc_u16 v1.l, v6.l, v3.l
; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v0.h
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_add_nc_u16 v1.l, v1.l, 6
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b16 v1.h, 0, 8, vcc_lo
; GFX1200-NEXT: v_lshlrev_b16 v2.h, 3, v1.l
; GFX1200-NEXT: v_cndmask_b16 v0.h, v0.h, 0, vcc_lo
; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v1.l
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-NEXT: v_or_b16 v1.h, v0.l, v1.h
; GFX1200-NEXT: v_or_b16 v2.h, v0.l, v2.h
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_or_b16 v0.h, v1.h, v0.h
; GFX1200-NEXT: v_or_b16 v1.l, v2.h, v2.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cndmask_b16 v0.h, v1.l, v0.h, vcc_lo
; GFX1200-NEXT: v_cmp_o_f32_e32 vcc_lo, v5, v5
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b16 v0.l, v0.h, v0.l, s0
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b16 v0.l, 0x7f, v0.l, vcc_lo
; GFX1200-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-TRUE16-LABEL: to_fp8_bf16:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v4.l, 0x80
; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v0.l, 8, v0.l
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1250-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v7, v6
; GFX1250-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, v6
; GFX1250-TRUE16-NEXT: v_and_b16 v0.l, 0x80, v0.l
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-TRUE16-NEXT: v_xor_b16 v1.l, v7.l, -1
; GFX1250-TRUE16-NEXT: v_cvt_pk_bf16_f32 v2, v2, s0
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-TRUE16-NEXT: v_min_u16 v1.l, v1.l, 15
; GFX1250-TRUE16-NEXT: v_and_b16 v2.h, 0x7f, v2.l
; GFX1250-TRUE16-NEXT: v_and_b16 v3.l, v2.l, 7
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-TRUE16-NEXT: v_sub_nc_u16 v1.h, v1.l, 1 clamp
; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v4.h, 4, v2.h
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-TRUE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v3.l
; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v3.h, v1.h, 1
; GFX1250-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX1250-TRUE16-NEXT: v_add_nc_u16 v3.l, v3.h, -1
; GFX1250-TRUE16-NEXT: v_bitop3_b16 v3.h, v2.l, v4.l, 0x7f bitop3:0xec
; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v2.l, 3, v2.l
; GFX1250-TRUE16-NEXT: v_and_b16 v4.l, v4.h, 1
; GFX1250-TRUE16-NEXT: v_bitop3_b16 v2.h, v2.h, v3.l, 0x80 bitop3:0xc8
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v3.l, v1.l, v3.h
; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v1.h, v1.h, v3.h
; GFX1250-TRUE16-NEXT: v_bitop3_b16 v2.l, v2.l, v5.l, v4.l bitop3:0xe0
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1250-TRUE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v2.h
; GFX1250-TRUE16-NEXT: v_and_b16 v2.h, v3.l, 1
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1250-TRUE16-NEXT: v_add_nc_u16 v2.l, v4.h, v2.l
; GFX1250-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX1250-TRUE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v1.l
; GFX1250-TRUE16-NEXT: v_cmp_lt_i16_e64 s0, 7, v2.l
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v4.l, v5.l
; GFX1250-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX1250-TRUE16-NEXT: v_bitop3_b16 v1.l, v1.h, v4.l, v2.h bitop3:0xe0
; GFX1250-TRUE16-NEXT: v_cndmask_b16 v1.h, v2.l, 0, s0
; GFX1250-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v6
; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v4.l, v5.l
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-TRUE16-NEXT: v_cndmask_b16 v1.l, 0, v1.l, vcc_lo
; GFX1250-TRUE16-NEXT: v_add_nc_u16 v0.h, v7.l, v4.l
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-TRUE16-NEXT: v_add_nc_u16 v1.l, v3.l, v1.l
; GFX1250-TRUE16-NEXT: v_add_nc_u16 v0.h, v0.h, 6
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-TRUE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v1.l
; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v2.l, 3, v0.h
; GFX1250-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, 0, vcc_lo
; GFX1250-TRUE16-NEXT: v_cndmask_b16 v2.h, 0, 8, vcc_lo
; GFX1250-TRUE16-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v0.h
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.h, v0.l, v1.h, v2.l bitop3:0xfe
; GFX1250-TRUE16-NEXT: v_bitop3_b16 v1.l, v0.l, v1.l, v2.h bitop3:0xfe
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v1.l, vcc_lo
; GFX1250-TRUE16-NEXT: v_cmp_o_f32_e32 vcc_lo, v6, v6
; GFX1250-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.h, v0.l, s0
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7f, v0.l, vcc_lo
; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1250-FAKE16-LABEL: to_fp8_bf16:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0
; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v0, 8, v0
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v2, v1
; GFX1250-FAKE16-NEXT: v_and_b32_e32 v0, 0x80, v0
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-FAKE16-NEXT: v_xor_b32_e32 v3, -1, v2
; GFX1250-FAKE16-NEXT: v_frexp_mant_f32_e32 v4, v1
; GFX1250-FAKE16-NEXT: v_min_u16 v3, v3, 15
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-FAKE16-NEXT: v_cvt_pk_bf16_f32 v4, v4, s0
; GFX1250-FAKE16-NEXT: s_movk_i32 s0, 0x80
; GFX1250-FAKE16-NEXT: v_sub_nc_u16 v5, v3, 1 clamp
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1250-FAKE16-NEXT: v_and_b32_e32 v6, 0x7f, v4
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v9, v4, s0, 0x7f bitop3:0xec
; GFX1250-FAKE16-NEXT: v_cmp_ne_u16_e64 s0, 0, v3
; GFX1250-FAKE16-NEXT: v_and_b32_e32 v8, 7, v4
; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v7, v5, 1
; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v10, 4, v6
; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v4, 3, v4
; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v12, v3, v9
; GFX1250-FAKE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v8
; GFX1250-FAKE16-NEXT: v_add_nc_u16 v7, v7, -1
; GFX1250-FAKE16-NEXT: v_and_b32_e32 v11, 1, v10
; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v5, v5, v9
; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v6, v6, v7, 0x80 bitop3:0xc8
; GFX1250-FAKE16-NEXT: v_and_b32_e32 v7, 1, v12
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v4, v4, v8, v11 bitop3:0xe0
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-FAKE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v6
; GFX1250-FAKE16-NEXT: v_add_nc_u16 v4, v10, v4
; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-FAKE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v5, v5, v6, v7 bitop3:0xe0
; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, v5, s0
; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX1250-FAKE16-NEXT: v_add_nc_u16 v3, v12, v3
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-FAKE16-NEXT: v_add_nc_u16 v2, v2, v5
; GFX1250-FAKE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v3
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1250-FAKE16-NEXT: v_add_nc_u16 v2, v2, 6
; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo
; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 8, vcc_lo
; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v6, 3, v2
; GFX1250-FAKE16-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v2
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v3, v0, v3, v5 bitop3:0xfe
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v4, v0, v4, v6 bitop3:0xfe
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v3, vcc_lo
; GFX1250-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v1
; GFX1250-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX1250-FAKE16-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v1
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1250-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7f, v0, vcc_lo
; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1310-LABEL: to_fp8_bf16:
; GFX1310: ; %bb.0:
; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1310-NEXT: s_wait_expcnt 0x0
; GFX1310-NEXT: s_wait_samplecnt 0x0
; GFX1310-NEXT: s_wait_bvhcnt 0x0
; GFX1310-NEXT: s_wait_kmcnt 0x0
; GFX1310-NEXT: v_lshlrev_b32_e32 v1, 16, v0
; GFX1310-NEXT: v_lshrrev_b16 v0, 8, v0
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_frexp_exp_i32_f32_e32 v2, v1
; GFX1310-NEXT: v_and_b32_e32 v0, 0x80, v0
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_xor_b32_e32 v3, -1, v2
; GFX1310-NEXT: v_frexp_mant_f32_e32 v4, v1
; GFX1310-NEXT: v_min_u16 v3, v3, 15
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_cvt_pk_bf16_f32 v4, v4, s0
; GFX1310-NEXT: s_movk_i32 s0, 0x80
; GFX1310-NEXT: v_sub_nc_u16 v5, v3, 1 clamp
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1310-NEXT: v_and_b32_e32 v6, 0x7f, v4
; GFX1310-NEXT: v_bitop3_b16 v9, v4, s0, 0x7f bitop3:0xec
; GFX1310-NEXT: v_cmp_ne_u16_e64 s0, 0, v3
; GFX1310-NEXT: v_and_b32_e32 v8, 7, v4
; GFX1310-NEXT: v_lshlrev_b16 v7, v5, 1
; GFX1310-NEXT: v_lshrrev_b16 v10, 4, v6
; GFX1310-NEXT: v_lshrrev_b16 v4, 3, v4
; GFX1310-NEXT: v_lshrrev_b16 v12, v3, v9
; GFX1310-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v8
; GFX1310-NEXT: v_add_nc_u16 v7, v7, -1
; GFX1310-NEXT: v_and_b32_e32 v11, 1, v10
; GFX1310-NEXT: v_lshrrev_b16 v5, v5, v9
; GFX1310-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1310-NEXT: v_bitop3_b16 v6, v6, v7, 0x80 bitop3:0xc8
; GFX1310-NEXT: v_and_b32_e32 v7, 1, v12
; GFX1310-NEXT: v_bitop3_b16 v4, v4, v8, v11 bitop3:0xe0
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v6
; GFX1310-NEXT: v_add_nc_u16 v4, v10, v4
; GFX1310-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4
; GFX1310-NEXT: v_bitop3_b16 v5, v5, v6, v7 bitop3:0xe0
; GFX1310-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_cndmask_b32_e64 v3, 0, v5, s0
; GFX1310-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX1310-NEXT: v_add_nc_u16 v3, v12, v3
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_add_nc_u16 v2, v2, v5
; GFX1310-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v3
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1310-NEXT: v_add_nc_u16 v2, v2, 6
; GFX1310-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo
; GFX1310-NEXT: v_cndmask_b32_e64 v5, 0, 8, vcc_lo
; GFX1310-NEXT: v_lshlrev_b16 v6, 3, v2
; GFX1310-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v2
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1310-NEXT: v_bitop3_b16 v3, v0, v3, v5 bitop3:0xfe
; GFX1310-NEXT: v_bitop3_b16 v4, v0, v4, v6 bitop3:0xfe
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_cndmask_b32_e32 v2, v4, v3, vcc_lo
; GFX1310-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v1
; GFX1310-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX1310-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v1
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1310-NEXT: v_cndmask_b32_e32 v0, 0x7f, v0, vcc_lo
; GFX1310-NEXT: s_set_pc_i64 s[30:31]
%r = call i8 @llvm.convert.to.arbitrary.fp.i8.bf16(bfloat %x, metadata !"Float8E4M3FN", metadata !"round.tonearest", i1 false)
ret i8 %r
}
; The clamp modifier selects E5M3 for these instructions. The conversion's
; native clamping also implements the saturating form of the generic intrinsic.
define i8 @to_e5m3fnu_f32(float %x) {
; GFX950-LABEL: to_e5m3fnu_f32:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
; GFX950-NEXT: v_sub_u32_e32 v2, 7, v1
; GFX950-NEXT: v_frexp_mant_f32_e32 v3, v0
; GFX950-NEXT: v_min_u32_e32 v2, 31, v2
; GFX950-NEXT: v_and_b32_e32 v4, 0x7fffff, v3
; GFX950-NEXT: v_or_b32_e32 v5, 0x800000, v4
; GFX950-NEXT: v_sub_u32_e64 v7, v2, 1 clamp
; GFX950-NEXT: v_lshrrev_b32_e32 v8, v7, v5
; GFX950-NEXT: v_bfe_u32 v7, v5, 0, v7
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; GFX950-NEXT: v_bfe_u32 v6, v5, v2, 1
; GFX950-NEXT: v_bfe_u32 v4, v4, 20, 1
; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX950-NEXT: v_bitop3_b32 v6, v8, v7, v6 bitop3:0xe0
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GFX950-NEXT: v_lshrrev_b32_e32 v2, v2, v5
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
; GFX950-NEXT: v_add_u32_e32 v2, v2, v6
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v2
; GFX950-NEXT: v_and_b32_e32 v6, 0x7ffff, v3
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 8, vcc
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; GFX950-NEXT: v_or_b32_e32 v2, v5, v2
; GFX950-NEXT: v_lshrrev_b32_e32 v5, 19, v3
; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX950-NEXT: v_bitop3_b32 v4, v5, v6, v4 bitop3:0xe0
; GFX950-NEXT: v_bfe_u32 v3, v3, 20, 3
; GFX950-NEXT: v_add_u32_e32 v3, v3, v4
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v3
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
; GFX950-NEXT: v_addc_co_u32_e32 v1, vcc, 14, v1, vcc
; GFX950-NEXT: v_lshl_or_b32 v3, v1, 3, v3
; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, 1, v1
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc
; GFX950-NEXT: v_cmp_neq_f32_e32 vcc, 0, v0
; GFX950-NEXT: v_mov_b32_e32 v2, 0xff
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: to_e5m3fnu_f32:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT: s_wait_expcnt 0x0
; GFX1200-NEXT: s_wait_samplecnt 0x0
; GFX1200-NEXT: s_wait_bvhcnt 0x0
; GFX1200-NEXT: s_wait_kmcnt 0x0
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
; GFX1200-NEXT: v_frexp_mant_f32_e32 v3, v0
; GFX1200-NEXT: s_mov_b32 s0, 0x7fffff
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_sub_nc_u32_e32 v2, 7, v1
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_and_or_b32 v4, v3, s0, 0x800000
; GFX1200-NEXT: v_and_b32_e32 v8, 0x7ffff, v3
; GFX1200-NEXT: v_bfe_u32 v9, v3, 20, 3
; GFX1200-NEXT: v_lshrrev_b32_e32 v3, 19, v3
; GFX1200-NEXT: v_min_u32_e32 v2, 31, v2
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_sub_nc_u32_e64 v5, v2, 1 clamp
; GFX1200-NEXT: v_lshrrev_b32_e32 v7, v2, v4
; GFX1200-NEXT: v_bfe_u32 v6, v4, 0, v5
; GFX1200-NEXT: v_lshrrev_b32_e32 v4, v5, v4
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; GFX1200-NEXT: v_and_or_b32 v5, v7, 1, v6
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_and_b32_e32 v4, v4, v5
; GFX1200-NEXT: v_and_or_b32 v5, v9, 1, v6
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_dual_cndmask_b32 v2, 0, v4 :: v_dual_and_b32 v3, v3, v5
; GFX1200-NEXT: v_add_nc_u32_e32 v2, v7, v2
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_add_nc_u32_e32 v3, v9, v3
; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v2
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cmp_lt_i32_e64 s0, 7, v3
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v3, v3, 0, s0
; GFX1200-NEXT: v_cndmask_b32_e64 v4, 0, 8, vcc_lo
; GFX1200-NEXT: v_add_co_ci_u32_e64 v1, null, 14, v1, s0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_or_b32_e32 v2, v4, v2
; GFX1200-NEXT: v_lshl_or_b32 v3, v1, 3, v3
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo
; GFX1200-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v0
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo
; GFX1200-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT: v_cndmask_b32_e32 v0, 0xff, v1, vcc_lo
; GFX1200-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-TRUE16-LABEL: to_e5m3fnu_f32:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v0.l, v0, v0 clamp
; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1250-FAKE16-LABEL: to_e5m3fnu_f32:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v0, v0, v0 clamp
; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1310-LABEL: to_e5m3fnu_f32:
; GFX1310: ; %bb.0:
; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1310-NEXT: s_wait_expcnt 0x0
; GFX1310-NEXT: s_wait_samplecnt 0x0
; GFX1310-NEXT: s_wait_bvhcnt 0x0
; GFX1310-NEXT: s_wait_kmcnt 0x0
; GFX1310-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
; GFX1310-NEXT: v_frexp_mant_f32_e32 v2, v0
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX1310-NEXT: v_dual_sub_nc_u32 v3, 7, v1 :: v_dual_lshrrev_b32 v10, 19, v2
; GFX1310-NEXT: v_and_b32_e32 v4, 0x7fffff, v2
; GFX1310-NEXT: v_and_b32_e32 v9, 0x7ffff, v2
; GFX1310-NEXT: v_bfe_u32 v2, v2, 20, 3
; GFX1310-NEXT: v_min_u32_e32 v3, 31, v3
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1310-NEXT: v_or_b32_e32 v5, 0x800000, v4
; GFX1310-NEXT: v_bfe_u32 v4, v4, 20, 1
; GFX1310-NEXT: v_sub_nc_u32_e64 v6, v3, 1 clamp
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_bfe_u32 v8, v5, v3, 1
; GFX1310-NEXT: v_bfe_u32 v7, v5, 0, v6
; GFX1310-NEXT: v_dual_lshrrev_b32 v6, v6, v5 :: v_dual_lshrrev_b32 v5, v3, v5
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v7
; GFX1310-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v9
; GFX1310-NEXT: v_bitop3_b32 v6, v6, v7, v8 bitop3:0xe0
; GFX1310-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1310-NEXT: v_bitop3_b32 v4, v10, v7, v4 bitop3:0xe0
; GFX1310-NEXT: v_dual_cndmask_b32 v3, 0, v6 :: v_dual_add_nc_u32 v2, v2, v4
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_add_nc_u32_e32 v3, v5, v3
; GFX1310-NEXT: v_cmp_lt_i32_e64 s0, 7, v2
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v3
; GFX1310-NEXT: v_cndmask_b32_e64 v2, v2, 0, s0
; GFX1310-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo
; GFX1310-NEXT: v_cndmask_b32_e64 v4, 0, 8, vcc_lo
; GFX1310-NEXT: v_add_co_ci_u32_e64 v1, null, 14, v1, s0
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_or_b32_e32 v3, v4, v3
; GFX1310-NEXT: v_lshl_or_b32 v2, v1, 3, v2
; GFX1310-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v1
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo
; GFX1310-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v0
; GFX1310-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo
; GFX1310-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1310-NEXT: v_cndmask_b32_e32 v0, 0xff, v1, vcc_lo
; GFX1310-NEXT: s_set_pc_i64 s[30:31]
%r = call i8 @llvm.convert.to.arbitrary.fp.i8.f32(float %x, metadata !"Float8E5M3FNU", metadata !"round.tonearest", i1 false)
ret i8 %r
}
define <2 x i8> @to_e5m3fnu_v2f32(<2 x float> %x) {
; GFX950-LABEL: to_e5m3fnu_v2f32:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v2, v1
; GFX950-NEXT: v_sub_u32_e32 v3, 7, v2
; GFX950-NEXT: v_frexp_mant_f32_e32 v4, v1
; GFX950-NEXT: v_min_u32_e32 v3, 31, v3
; GFX950-NEXT: v_and_b32_e32 v5, 0x7fffff, v4
; GFX950-NEXT: v_or_b32_e32 v6, 0x800000, v5
; GFX950-NEXT: v_sub_u32_e64 v8, v3, 1 clamp
; GFX950-NEXT: v_lshrrev_b32_e32 v9, v8, v6
; GFX950-NEXT: v_bfe_u32 v8, v6, 0, v8
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX950-NEXT: v_bfe_u32 v7, v6, v3, 1
; GFX950-NEXT: v_bfe_u32 v5, v5, 20, 1
; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX950-NEXT: v_bitop3_b32 v7, v9, v8, v7 bitop3:0xe0
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GFX950-NEXT: v_lshrrev_b32_e32 v3, v3, v6
; GFX950-NEXT: s_movk_i32 s0, 0xff
; GFX950-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
; GFX950-NEXT: v_add_u32_e32 v3, v3, v7
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v3
; GFX950-NEXT: v_and_b32_e32 v7, 0x7ffff, v4
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 8, vcc
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; GFX950-NEXT: v_or_b32_e32 v3, v6, v3
; GFX950-NEXT: v_lshrrev_b32_e32 v6, 19, v4
; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX950-NEXT: v_bitop3_b32 v5, v6, v7, v5 bitop3:0xe0
; GFX950-NEXT: v_bfe_u32 v4, v4, 20, 3
; GFX950-NEXT: v_add_u32_e32 v4, v4, v5
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v4
; GFX950-NEXT: v_frexp_mant_f32_e32 v6, v0
; GFX950-NEXT: v_and_b32_e32 v7, 0x7fffff, v6
; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
; GFX950-NEXT: v_addc_co_u32_e32 v2, vcc, 14, v2, vcc
; GFX950-NEXT: v_lshl_or_b32 v4, v2, 3, v4
; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, 1, v2
; GFX950-NEXT: v_or_b32_e32 v8, 0x800000, v7
; GFX950-NEXT: v_bfe_u32 v7, v7, 20, 1
; GFX950-NEXT: v_cndmask_b32_e32 v2, v4, v3, vcc
; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v4, v0
; GFX950-NEXT: v_sub_u32_e32 v5, 7, v4
; GFX950-NEXT: v_min_u32_e32 v5, 31, v5
; GFX950-NEXT: v_cmp_neq_f32_e32 vcc, 0, v1
; GFX950-NEXT: v_sub_u32_e64 v10, v5, 1 clamp
; GFX950-NEXT: v_mov_b32_e32 v3, 0xff
; GFX950-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v1, v1
; GFX950-NEXT: v_lshrrev_b32_e32 v11, v10, v8
; GFX950-NEXT: v_bfe_u32 v10, v8, 0, v10
; GFX950-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; GFX950-NEXT: v_bfe_u32 v9, v8, v5, 1
; GFX950-NEXT: v_lshlrev_b16_e32 v2, 8, v1
; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GFX950-NEXT: v_bitop3_b32 v9, v11, v10, v9 bitop3:0xe0
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GFX950-NEXT: v_lshrrev_b32_e32 v5, v5, v8
; GFX950-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX950-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc
; GFX950-NEXT: v_add_u32_e32 v5, v5, v9
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v5
; GFX950-NEXT: v_and_b32_e32 v9, 0x7ffff, v6
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 8, vcc
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
; GFX950-NEXT: v_or_b32_e32 v5, v8, v5
; GFX950-NEXT: v_lshrrev_b32_e32 v8, 19, v6
; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GFX950-NEXT: v_bitop3_b32 v7, v8, v9, v7 bitop3:0xe0
; GFX950-NEXT: v_bfe_u32 v6, v6, 20, 3
; GFX950-NEXT: v_add_u32_e32 v6, v6, v7
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v6
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
; GFX950-NEXT: v_addc_co_u32_e32 v4, vcc, 14, v4, vcc
; GFX950-NEXT: v_lshl_or_b32 v6, v4, 3, v6
; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, 1, v4
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v4, v6, v5, vcc
; GFX950-NEXT: v_cmp_neq_f32_e32 vcc, 0, v0
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
; GFX950-NEXT: v_bitop3_b16 v0, v0, v2, s0 bitop3:0xec
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: to_e5m3fnu_v2f32:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT: s_wait_expcnt 0x0
; GFX1200-NEXT: s_wait_samplecnt 0x0
; GFX1200-NEXT: s_wait_bvhcnt 0x0
; GFX1200-NEXT: s_wait_kmcnt 0x0
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v3, v1
; GFX1200-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v5, v0
; GFX1200-NEXT: v_frexp_mant_f32_e32 v4, v0
; GFX1200-NEXT: s_mov_b32 s0, 0x7fffff
; GFX1200-NEXT: v_sub_nc_u32_e32 v7, 7, v3
; GFX1200-NEXT: v_and_b32_e32 v8, 0x7ffff, v2
; GFX1200-NEXT: v_sub_nc_u32_e32 v10, 7, v5
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_and_or_b32 v6, v2, s0, 0x800000
; GFX1200-NEXT: v_and_b32_e32 v12, 0x7ffff, v4
; GFX1200-NEXT: v_min_u32_e32 v7, 31, v7
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; GFX1200-NEXT: v_min_u32_e32 v10, 31, v10
; GFX1200-NEXT: v_and_or_b32 v11, v4, s0, 0x800000
; GFX1200-NEXT: v_bfe_u32 v9, v2, 20, 3
; GFX1200-NEXT: v_sub_nc_u32_e64 v14, v7, 1 clamp
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX1200-NEXT: v_sub_nc_u32_e64 v15, v10, 1 clamp
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12
; GFX1200-NEXT: v_lshrrev_b32_e32 v17, v7, v6
; GFX1200-NEXT: v_bfe_u32 v16, v6, 0, v14
; GFX1200-NEXT: v_lshrrev_b32_e32 v19, v10, v11
; GFX1200-NEXT: v_bfe_u32 v18, v11, 0, v15
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
; GFX1200-NEXT: v_lshrrev_b32_e32 v2, 19, v2
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v16
; GFX1200-NEXT: v_and_or_b32 v8, v9, 1, v8
; GFX1200-NEXT: v_lshrrev_b32_e32 v6, v14, v6
; GFX1200-NEXT: v_lshrrev_b32_e32 v11, v15, v11
; GFX1200-NEXT: v_bfe_u32 v13, v4, 20, 3
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v18
; GFX1200-NEXT: v_and_b32_e32 v2, v2, v8
; GFX1200-NEXT: v_lshrrev_b32_e32 v4, 19, v4
; GFX1200-NEXT: v_and_or_b32 v12, v13, 1, v12
; GFX1200-NEXT: v_and_or_b32 v14, v17, 1, v16
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc_lo
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v7
; GFX1200-NEXT: v_add_nc_u32_e32 v2, v9, v2
; GFX1200-NEXT: v_and_b32_e32 v4, v4, v12
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_and_or_b32 v15, v19, 1, v18
; GFX1200-NEXT: v_add_nc_u32_e32 v4, v13, v4
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_and_b32_e32 v8, v11, v15
; GFX1200-NEXT: v_and_b32_e32 v6, v6, v14
; GFX1200-NEXT: v_cmp_lt_i32_e64 s0, 7, v4
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc_lo
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v4, v4, 0, s0
; GFX1200-NEXT: v_add_co_ci_u32_e64 v5, null, 14, v5, s0
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v7, 0, v8, vcc_lo
; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v2
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_lshl_or_b32 v4, v5, 3, v4
; GFX1200-NEXT: v_add_nc_u32_e32 v7, v19, v7
; GFX1200-NEXT: v_add_nc_u32_e32 v6, v17, v6
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
; GFX1200-NEXT: v_add_co_ci_u32_e64 v3, null, 14, v3, vcc_lo
; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v7
; GFX1200-NEXT: v_cmp_lt_i32_e64 s1, 7, v6
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1200-NEXT: v_lshl_or_b32 v2, v3, 3, v2
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc_lo
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v6, v6, 0, s1
; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 8, s1
; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 8, vcc_lo
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v3
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_or_b32_e32 v6, v8, v6
; GFX1200-NEXT: v_or_b32_e32 v7, v9, v7
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v5
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v3, v4, v7, vcc_lo
; GFX1200-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc_lo
; GFX1200-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v0
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc_lo
; GFX1200-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v1, 0xff, v2, vcc_lo
; GFX1200-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_lshlrev_b16 v0.l, 8, v1.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v2, 0xff, v3, vcc_lo
; GFX1200-NEXT: v_and_b16 v1.l, 0xff, v1.l
; GFX1200-NEXT: v_and_b16 v0.h, 0xff, v2.l
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_or_b16 v0.l, v0.h, v0.l
; GFX1200-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-TRUE16-LABEL: to_e5m3fnu_v2f32:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v0.l, v0, v1 clamp
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v1.l, 8, v0.l
; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1250-FAKE16-LABEL: to_e5m3fnu_v2f32:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v0, v0, v1 clamp
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v1, 8, v0
; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1310-LABEL: to_e5m3fnu_v2f32:
; GFX1310: ; %bb.0:
; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1310-NEXT: s_wait_expcnt 0x0
; GFX1310-NEXT: s_wait_samplecnt 0x0
; GFX1310-NEXT: s_wait_bvhcnt 0x0
; GFX1310-NEXT: s_wait_kmcnt 0x0
; GFX1310-NEXT: v_frexp_exp_i32_f32_e32 v2, v1
; GFX1310-NEXT: v_frexp_mant_f32_e32 v3, v1
; GFX1310-NEXT: v_frexp_exp_i32_f32_e32 v4, v0
; GFX1310-NEXT: v_frexp_mant_f32_e32 v5, v0
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1310-NEXT: v_dual_sub_nc_u32 v6, 7, v2 :: v_dual_lshrrev_b32 v8, 19, v3
; GFX1310-NEXT: v_and_b32_e32 v7, 0x7fffff, v3
; GFX1310-NEXT: v_dual_sub_nc_u32 v10, 7, v4 :: v_dual_lshrrev_b32 v12, 19, v5
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1310-NEXT: v_min_u32_e32 v6, 31, v6
; GFX1310-NEXT: v_and_b32_e32 v11, 0x7fffff, v5
; GFX1310-NEXT: v_or_b32_e32 v14, 0x800000, v7
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX1310-NEXT: v_min_u32_e32 v10, 31, v10
; GFX1310-NEXT: v_and_b32_e32 v9, 0x7ffff, v3
; GFX1310-NEXT: v_sub_nc_u32_e64 v15, v6, 1 clamp
; GFX1310-NEXT: v_or_b32_e32 v16, 0x800000, v11
; GFX1310-NEXT: v_bfe_u32 v18, v14, v6, 1
; GFX1310-NEXT: v_sub_nc_u32_e64 v17, v10, 1 clamp
; GFX1310-NEXT: v_and_b32_e32 v13, 0x7ffff, v5
; GFX1310-NEXT: v_bfe_u32 v19, v14, 0, v15
; GFX1310-NEXT: v_lshrrev_b32_e32 v15, v15, v14
; GFX1310-NEXT: v_bfe_u32 v7, v7, 20, 1
; GFX1310-NEXT: v_bfe_u32 v21, v16, 0, v17
; GFX1310-NEXT: v_lshrrev_b32_e32 v17, v17, v16
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v19
; GFX1310-NEXT: v_bfe_u32 v20, v16, v10, 1
; GFX1310-NEXT: v_bfe_u32 v3, v3, 20, 3
; GFX1310-NEXT: v_bfe_u32 v11, v11, 20, 1
; GFX1310-NEXT: v_bfe_u32 v5, v5, 20, 3
; GFX1310-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc_lo
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v21
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_bitop3_b32 v15, v15, v19, v18 bitop3:0xe0
; GFX1310-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc_lo
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v9
; GFX1310-NEXT: v_bitop3_b32 v17, v17, v21, v20 bitop3:0xe0
; GFX1310-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
; GFX1310-NEXT: v_lshrrev_b32_e32 v14, v6, v14
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_bitop3_b32 v7, v8, v9, v7 bitop3:0xe0
; GFX1310-NEXT: v_cndmask_b32_e32 v6, 0, v15, vcc_lo
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v13
; GFX1310-NEXT: v_dual_add_nc_u32 v3, v3, v7 :: v_dual_add_nc_u32 v6, v14, v6
; GFX1310-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10
; GFX1310-NEXT: v_lshrrev_b32_e32 v10, v10, v16
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1310-NEXT: v_cmp_lt_i32_e64 s0, 7, v3
; GFX1310-NEXT: v_bitop3_b32 v9, v12, v13, v11 bitop3:0xe0
; GFX1310-NEXT: v_cndmask_b32_e32 v8, 0, v17, vcc_lo
; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v6
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1310-NEXT: v_cndmask_b32_e64 v3, v3, 0, s0
; GFX1310-NEXT: v_add_co_ci_u32_e64 v2, null, 14, v2, s0
; GFX1310-NEXT: v_dual_add_nc_u32 v5, v5, v9 :: v_dual_add_nc_u32 v7, v10, v8
; GFX1310-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc_lo
; GFX1310-NEXT: v_cndmask_b32_e64 v8, 0, 8, vcc_lo
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1310-NEXT: v_lshl_or_b32 v3, v2, 3, v3
; GFX1310-NEXT: v_cmp_lt_i32_e64 s0, 7, v5
; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v7
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX1310-NEXT: v_cndmask_b32_e64 v5, v5, 0, s0
; GFX1310-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc_lo
; GFX1310-NEXT: v_cndmask_b32_e64 v9, 0, 8, vcc_lo
; GFX1310-NEXT: v_add_co_ci_u32_e64 v4, null, 14, v4, s0
; GFX1310-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v2
; GFX1310-NEXT: v_or_b32_e32 v7, v9, v7
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1310-NEXT: v_lshl_or_b32 v5, v4, 3, v5
; GFX1310-NEXT: v_or_b32_e32 v6, v8, v6
; GFX1310-NEXT: v_cndmask_b32_e32 v2, v3, v6, vcc_lo
; GFX1310-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v4
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1310-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc_lo
; GFX1310-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v1
; GFX1310-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc_lo
; GFX1310-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v0
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1310-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc_lo
; GFX1310-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v1
; GFX1310-NEXT: v_cndmask_b32_e32 v1, 0xff, v2, vcc_lo
; GFX1310-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1310-NEXT: v_cndmask_b32_e32 v0, 0xff, v3, vcc_lo
; GFX1310-NEXT: v_lshlrev_b16 v2, 8, v1
; GFX1310-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1310-NEXT: v_bitop3_b16 v0, v0, v2, 0xff bitop3:0xec
; GFX1310-NEXT: s_set_pc_i64 s[30:31]
%r = call <2 x i8> @llvm.convert.to.arbitrary.fp.v2i8.v2f32(<2 x float> %x, metadata !"Float8E5M3FNU", metadata !"round.tonearest", i1 false)
ret <2 x i8> %r
}
define <4 x i8> @to_e5m3fnu_v4f32(<4 x float> %x) {
; GFX950-LABEL: to_e5m3fnu_v4f32:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v4, v1
; GFX950-NEXT: v_sub_u32_e32 v5, 7, v4
; GFX950-NEXT: v_frexp_mant_f32_e32 v6, v1
; GFX950-NEXT: v_min_u32_e32 v5, 31, v5
; GFX950-NEXT: v_and_b32_e32 v7, 0x7fffff, v6
; GFX950-NEXT: v_or_b32_e32 v8, 0x800000, v7
; GFX950-NEXT: v_sub_u32_e64 v10, v5, 1 clamp
; GFX950-NEXT: v_lshrrev_b32_e32 v11, v10, v8
; GFX950-NEXT: v_bfe_u32 v10, v8, 0, v10
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; GFX950-NEXT: v_bfe_u32 v9, v8, v5, 1
; GFX950-NEXT: v_bfe_u32 v7, v7, 20, 1
; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GFX950-NEXT: v_bitop3_b32 v9, v11, v10, v9 bitop3:0xe0
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GFX950-NEXT: v_lshrrev_b32_e32 v5, v5, v8
; GFX950-NEXT: s_movk_i32 s0, 0xff
; GFX950-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc
; GFX950-NEXT: v_add_u32_e32 v5, v5, v9
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v5
; GFX950-NEXT: v_and_b32_e32 v9, 0x7ffff, v6
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 8, vcc
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
; GFX950-NEXT: v_or_b32_e32 v5, v8, v5
; GFX950-NEXT: v_lshrrev_b32_e32 v8, 19, v6
; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GFX950-NEXT: v_bitop3_b32 v7, v8, v9, v7 bitop3:0xe0
; GFX950-NEXT: v_bfe_u32 v6, v6, 20, 3
; GFX950-NEXT: v_add_u32_e32 v6, v6, v7
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v6
; GFX950-NEXT: v_frexp_mant_f32_e32 v7, v0
; GFX950-NEXT: v_and_b32_e32 v8, 0x7fffff, v7
; GFX950-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
; GFX950-NEXT: v_addc_co_u32_e32 v4, vcc, 14, v4, vcc
; GFX950-NEXT: v_lshl_or_b32 v6, v4, 3, v6
; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, 1, v4
; GFX950-NEXT: v_or_b32_e32 v9, 0x800000, v8
; GFX950-NEXT: v_bfe_u32 v8, v8, 20, 1
; GFX950-NEXT: v_cndmask_b32_e32 v4, v6, v5, vcc
; GFX950-NEXT: v_cmp_neq_f32_e32 vcc, 0, v1
; GFX950-NEXT: v_mov_b32_e32 v5, 0xff
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v1, v1
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc
; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v4, v0
; GFX950-NEXT: v_sub_u32_e32 v6, 7, v4
; GFX950-NEXT: v_min_u32_e32 v6, 31, v6
; GFX950-NEXT: v_sub_u32_e64 v11, v6, 1 clamp
; GFX950-NEXT: v_lshrrev_b32_e32 v12, v11, v9
; GFX950-NEXT: v_bfe_u32 v11, v9, 0, v11
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; GFX950-NEXT: v_bfe_u32 v10, v9, v6, 1
; GFX950-NEXT: v_lshlrev_b16_e32 v1, 8, v1
; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GFX950-NEXT: v_bitop3_b32 v10, v12, v11, v10 bitop3:0xe0
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; GFX950-NEXT: v_lshrrev_b32_e32 v6, v6, v9
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
; GFX950-NEXT: v_add_u32_e32 v6, v6, v10
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v6
; GFX950-NEXT: v_and_b32_e32 v10, 0x7ffff, v7
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 8, vcc
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; GFX950-NEXT: v_or_b32_e32 v6, v9, v6
; GFX950-NEXT: v_lshrrev_b32_e32 v9, 19, v7
; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GFX950-NEXT: v_bitop3_b32 v8, v9, v10, v8 bitop3:0xe0
; GFX950-NEXT: v_bfe_u32 v7, v7, 20, 3
; GFX950-NEXT: v_add_u32_e32 v7, v7, v8
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v7
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc
; GFX950-NEXT: v_addc_co_u32_e32 v4, vcc, 14, v4, vcc
; GFX950-NEXT: v_lshl_or_b32 v7, v4, 3, v7
; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, 1, v4
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v4, v7, v6, vcc
; GFX950-NEXT: v_cmp_neq_f32_e32 vcc, 0, v0
; GFX950-NEXT: v_frexp_mant_f32_e32 v7, v3
; GFX950-NEXT: v_and_b32_e32 v8, 0x7fffff, v7
; GFX950-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
; GFX950-NEXT: v_or_b32_e32 v9, 0x800000, v8
; GFX950-NEXT: v_bfe_u32 v8, v8, 20, 1
; GFX950-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc
; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v4, v3
; GFX950-NEXT: v_sub_u32_e32 v6, 7, v4
; GFX950-NEXT: v_min_u32_e32 v6, 31, v6
; GFX950-NEXT: v_sub_u32_e64 v11, v6, 1 clamp
; GFX950-NEXT: v_lshrrev_b32_e32 v12, v11, v9
; GFX950-NEXT: v_bfe_u32 v11, v9, 0, v11
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; GFX950-NEXT: v_bfe_u32 v10, v9, v6, 1
; GFX950-NEXT: v_bitop3_b16 v0, v0, v1, s0 bitop3:0xec
; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GFX950-NEXT: v_bitop3_b32 v10, v12, v11, v10 bitop3:0xe0
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; GFX950-NEXT: v_lshrrev_b32_e32 v6, v6, v9
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
; GFX950-NEXT: v_add_u32_e32 v6, v6, v10
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v6
; GFX950-NEXT: v_and_b32_e32 v10, 0x7ffff, v7
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 8, vcc
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; GFX950-NEXT: v_or_b32_e32 v6, v9, v6
; GFX950-NEXT: v_lshrrev_b32_e32 v9, 19, v7
; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GFX950-NEXT: v_bitop3_b32 v8, v9, v10, v8 bitop3:0xe0
; GFX950-NEXT: v_bfe_u32 v7, v7, 20, 3
; GFX950-NEXT: v_add_u32_e32 v7, v7, v8
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v7
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc
; GFX950-NEXT: v_addc_co_u32_e32 v4, vcc, 14, v4, vcc
; GFX950-NEXT: v_lshl_or_b32 v7, v4, 3, v7
; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, 1, v4
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v4, v7, v6, vcc
; GFX950-NEXT: v_cmp_neq_f32_e32 vcc, 0, v3
; GFX950-NEXT: v_frexp_mant_f32_e32 v7, v2
; GFX950-NEXT: v_and_b32_e32 v8, 0x7fffff, v7
; GFX950-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v3, v3
; GFX950-NEXT: v_or_b32_e32 v9, 0x800000, v8
; GFX950-NEXT: v_bfe_u32 v8, v8, 20, 1
; GFX950-NEXT: v_cndmask_b32_e32 v3, v5, v4, vcc
; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v4, v2
; GFX950-NEXT: v_sub_u32_e32 v6, 7, v4
; GFX950-NEXT: v_min_u32_e32 v6, 31, v6
; GFX950-NEXT: v_sub_u32_e64 v11, v6, 1 clamp
; GFX950-NEXT: v_lshrrev_b32_e32 v12, v11, v9
; GFX950-NEXT: v_bfe_u32 v11, v9, 0, v11
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; GFX950-NEXT: v_bfe_u32 v10, v9, v6, 1
; GFX950-NEXT: v_lshlrev_b16_e32 v3, 8, v3
; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GFX950-NEXT: v_bitop3_b32 v10, v12, v11, v10 bitop3:0xe0
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; GFX950-NEXT: v_lshrrev_b32_e32 v6, v6, v9
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
; GFX950-NEXT: v_add_u32_e32 v6, v6, v10
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v6
; GFX950-NEXT: v_and_b32_e32 v10, 0x7ffff, v7
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 8, vcc
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; GFX950-NEXT: v_or_b32_e32 v6, v9, v6
; GFX950-NEXT: v_lshrrev_b32_e32 v9, 19, v7
; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GFX950-NEXT: v_bitop3_b32 v8, v9, v10, v8 bitop3:0xe0
; GFX950-NEXT: v_bfe_u32 v7, v7, 20, 3
; GFX950-NEXT: v_add_u32_e32 v7, v7, v8
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v7
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc
; GFX950-NEXT: v_addc_co_u32_e32 v4, vcc, 14, v4, vcc
; GFX950-NEXT: v_lshl_or_b32 v7, v4, 3, v7
; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, 1, v4
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v4, v7, v6, vcc
; GFX950-NEXT: v_cmp_neq_f32_e32 vcc, 0, v2
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v2, v2
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v2, v5, v4, vcc
; GFX950-NEXT: v_bitop3_b16 v2, v2, v3, s0 bitop3:0xec
; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v2
; GFX950-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX950-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX950-NEXT: v_lshrrev_b32_e32 v3, 24, v3
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: to_e5m3fnu_v4f32:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT: s_wait_expcnt 0x0
; GFX1200-NEXT: s_wait_samplecnt 0x0
; GFX1200-NEXT: s_wait_bvhcnt 0x0
; GFX1200-NEXT: s_wait_kmcnt 0x0
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v4, v1
; GFX1200-NEXT: v_frexp_mant_f32_e32 v5, v1
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v6, v0
; GFX1200-NEXT: s_mov_b32 s1, 0x7fffff
; GFX1200-NEXT: v_frexp_mant_f32_e32 v7, v0
; GFX1200-NEXT: v_sub_nc_u32_e32 v8, 7, v4
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_and_or_b32 v13, v5, s1, 0x800000
; GFX1200-NEXT: v_sub_nc_u32_e32 v11, 7, v6
; GFX1200-NEXT: v_and_b32_e32 v14, 0x7ffff, v5
; GFX1200-NEXT: v_and_or_b32 v17, v7, s1, 0x800000
; GFX1200-NEXT: v_min_u32_e32 v8, 31, v8
; GFX1200-NEXT: v_bfe_u32 v15, v5, 20, 3
; GFX1200-NEXT: v_min_u32_e32 v11, 31, v11
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX1200-NEXT: v_lshrrev_b32_e32 v5, 19, v5
; GFX1200-NEXT: v_sub_nc_u32_e64 v16, v8, 1 clamp
; GFX1200-NEXT: v_lshrrev_b32_e32 v22, v8, v13
; GFX1200-NEXT: v_sub_nc_u32_e64 v18, v11, 1 clamp
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc_lo
; GFX1200-NEXT: v_lshrrev_b32_e32 v23, v11, v17
; GFX1200-NEXT: v_bfe_u32 v20, v13, 0, v16
; GFX1200-NEXT: v_lshrrev_b32_e32 v13, v16, v13
; GFX1200-NEXT: v_bfe_u32 v21, v17, 0, v18
; GFX1200-NEXT: v_and_or_b32 v14, v15, 1, v14
; GFX1200-NEXT: v_lshrrev_b32_e32 v17, v18, v17
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v20
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v10, v3
; GFX1200-NEXT: v_frexp_mant_f32_e32 v9, v3
; GFX1200-NEXT: v_and_b32_e32 v5, v5, v14
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v12, v2
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc_lo
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v21
; GFX1200-NEXT: v_sub_nc_u32_e32 v14, 7, v10
; GFX1200-NEXT: v_add_nc_u32_e32 v5, v15, v5
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX1200-NEXT: v_and_or_b32 v16, v22, 1, v20
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc_lo
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; GFX1200-NEXT: v_min_u32_e32 v14, 31, v14
; GFX1200-NEXT: v_and_or_b32 v20, v9, s1, 0x800000
; GFX1200-NEXT: v_and_b32_e32 v13, v13, v16
; GFX1200-NEXT: v_and_b32_e32 v19, 0x7ffff, v7
; GFX1200-NEXT: v_and_or_b32 v18, v23, 1, v21
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_cndmask_b32_e32 v8, 0, v13, vcc_lo
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v11
; GFX1200-NEXT: v_and_b32_e32 v16, v17, v18
; GFX1200-NEXT: v_sub_nc_u32_e32 v13, 7, v12
; GFX1200-NEXT: v_lshrrev_b32_e32 v18, v14, v20
; GFX1200-NEXT: v_add_nc_u32_e32 v8, v22, v8
; GFX1200-NEXT: v_bfe_u32 v22, v9, 20, 3
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v11, 0, v16, vcc_lo
; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v5
; GFX1200-NEXT: v_sub_nc_u32_e64 v16, v14, 1 clamp
; GFX1200-NEXT: v_cmp_lt_i32_e64 s0, 7, v8
; GFX1200-NEXT: v_min_u32_e32 v13, 31, v13
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc_lo
; GFX1200-NEXT: v_add_co_ci_u32_e64 v4, null, 14, v4, vcc_lo
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v8, v8, 0, s0
; GFX1200-NEXT: v_cndmask_b32_e64 v15, 0, 8, s0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_lshl_or_b32 v5, v4, 3, v5
; GFX1200-NEXT: v_or_b32_e32 v8, v15, v8
; GFX1200-NEXT: v_add_nc_u32_e32 v11, v23, v11
; GFX1200-NEXT: v_bfe_u32 v15, v20, 0, v16
; GFX1200-NEXT: v_lshrrev_b32_e32 v16, v16, v20
; GFX1200-NEXT: v_sub_nc_u32_e64 v20, v13, 1 clamp
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v11
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v11, v11, 0, vcc_lo
; GFX1200-NEXT: v_cndmask_b32_e64 v17, 0, 8, vcc_lo
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v4
; GFX1200-NEXT: v_or_b32_e32 v11, v17, v11
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v4, v5, v8, vcc_lo
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15
; GFX1200-NEXT: v_frexp_mant_f32_e32 v15, v2
; GFX1200-NEXT: v_and_b32_e32 v21, 0x7ffff, v9
; GFX1200-NEXT: v_bfe_u32 v17, v7, 20, 3
; GFX1200-NEXT: v_lshrrev_b32_e32 v7, 19, v7
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v19
; GFX1200-NEXT: v_and_or_b32 v19, v15, s1, 0x800000
; GFX1200-NEXT: v_lshrrev_b32_e32 v9, 19, v9
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX1200-NEXT: v_and_or_b32 v5, v18, 1, v5
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v21
; GFX1200-NEXT: v_lshrrev_b32_e32 v23, v13, v19
; GFX1200-NEXT: v_and_b32_e32 v5, v16, v5
; GFX1200-NEXT: v_bfe_u32 v16, v19, 0, v20
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc_lo
; GFX1200-NEXT: v_and_or_b32 v8, v17, 1, v8
; GFX1200-NEXT: v_lshrrev_b32_e32 v19, v20, v19
; GFX1200-NEXT: v_bfe_u32 v20, v15, 20, 3
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v16
; GFX1200-NEXT: v_and_or_b32 v21, v22, 1, v21
; GFX1200-NEXT: v_and_b32_e32 v7, v7, v8
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX1200-NEXT: v_and_b32_e32 v14, 0x7ffff, v15
; GFX1200-NEXT: v_and_b32_e32 v9, v9, v21
; GFX1200-NEXT: v_lshrrev_b32_e32 v15, 19, v15
; GFX1200-NEXT: v_and_or_b32 v16, v23, 1, v16
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc_lo
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX1200-NEXT: v_add_nc_u32_e32 v9, v22, v9
; GFX1200-NEXT: v_add_nc_u32_e32 v7, v17, v7
; GFX1200-NEXT: v_and_b32_e32 v8, v19, v16
; GFX1200-NEXT: v_add_nc_u32_e32 v5, v18, v5
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc_lo
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v13
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_and_or_b32 v14, v20, 1, v14
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc_lo
; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v5
; GFX1200-NEXT: v_and_b32_e32 v13, v15, v14
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1200-NEXT: v_add_nc_u32_e32 v8, v23, v8
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc_lo
; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 8, vcc_lo
; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v9
; GFX1200-NEXT: v_add_nc_u32_e32 v13, v20, v13
; GFX1200-NEXT: v_cmp_lt_i32_e64 s0, 7, v8
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX1200-NEXT: v_or_b32_e32 v5, v14, v5
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v9, v9, 0, vcc_lo
; GFX1200-NEXT: v_add_co_ci_u32_e64 v10, null, 14, v10, vcc_lo
; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v13
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v8, v8, 0, s0
; GFX1200-NEXT: v_cndmask_b32_e64 v15, 0, 8, s0
; GFX1200-NEXT: v_lshl_or_b32 v9, v10, 3, v9
; GFX1200-NEXT: v_cmp_gt_i32_e64 s0, 1, v10
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v13, v13, 0, vcc_lo
; GFX1200-NEXT: v_add_co_ci_u32_e64 v12, null, 14, v12, vcc_lo
; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v7
; GFX1200-NEXT: v_or_b32_e32 v8, v15, v8
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v5, v9, v5, s0
; GFX1200-NEXT: v_lshl_or_b32 v13, v12, 3, v13
; GFX1200-NEXT: v_cmp_gt_i32_e64 s0, 1, v12
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc_lo
; GFX1200-NEXT: v_add_co_ci_u32_e64 v6, null, 14, v6, vcc_lo
; GFX1200-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v3
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v8, v13, v8, s0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1200-NEXT: v_lshl_or_b32 v7, v6, 3, v7
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc_lo
; GFX1200-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v2
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc_lo
; GFX1200-NEXT: v_cmp_o_f32_e32 vcc_lo, v3, v3
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v3, 0xff, v5, vcc_lo
; GFX1200-NEXT: v_cmp_o_f32_e32 vcc_lo, v2, v2
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v3.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v5, 0xff, v8, vcc_lo
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v6
; GFX1200-NEXT: v_and_b16 v2.h, 0xff, v5.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v6, v7, v11, vcc_lo
; GFX1200-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1200-NEXT: v_or_b16 v2.h, v2.h, v2.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc_lo
; GFX1200-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v0
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v3, 0, v6, vcc_lo
; GFX1200-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v1, 0xff, v4, vcc_lo
; GFX1200-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v1.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v0, 0xff, v3, vcc_lo
; GFX1200-NEXT: v_mov_b16_e32 v3.l, v2.h
; GFX1200-NEXT: v_lshrrev_b32_e32 v1, 8, v2
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX1200-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_or_b16 v0.l, v0.l, v2.l
; GFX1200-NEXT: v_lshrrev_b32_e32 v3, 24, v3
; GFX1200-NEXT: v_mov_b16_e32 v2.l, v2.h
; GFX1200-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-TRUE16-LABEL: to_e5m3fnu_v4f32:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v2.l, v2, v3 clamp
; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v0.l, v0, v1 clamp
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GFX1250-TRUE16-NEXT: v_bfe_u32 v3, v2, 8, 8
; GFX1250-TRUE16-NEXT: v_and_or_b32 v1, 0xff00, v0, v1
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1250-FAKE16-LABEL: to_e5m3fnu_v4f32:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v2, v2, v3 clamp
; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v0, v0, v1 clamp
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GFX1250-FAKE16-NEXT: v_bfe_u32 v3, v2, 8, 8
; GFX1250-FAKE16-NEXT: v_and_or_b32 v1, 0xff00, v0, v1
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1310-LABEL: to_e5m3fnu_v4f32:
; GFX1310: ; %bb.0:
; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1310-NEXT: s_wait_expcnt 0x0
; GFX1310-NEXT: s_wait_samplecnt 0x0
; GFX1310-NEXT: s_wait_bvhcnt 0x0
; GFX1310-NEXT: s_wait_kmcnt 0x0
; GFX1310-NEXT: v_frexp_exp_i32_f32_e32 v4, v1
; GFX1310-NEXT: v_frexp_mant_f32_e32 v5, v1
; GFX1310-NEXT: v_frexp_exp_i32_f32_e32 v6, v0
; GFX1310-NEXT: v_frexp_mant_f32_e32 v8, v0
; GFX1310-NEXT: v_frexp_exp_i32_f32_e32 v9, v3
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX1310-NEXT: v_dual_sub_nc_u32 v7, 7, v4 :: v_dual_lshrrev_b32 v12, 19, v5
; GFX1310-NEXT: v_and_b32_e32 v11, 0x7fffff, v5
; GFX1310-NEXT: v_and_b32_e32 v13, 0x7ffff, v5
; GFX1310-NEXT: v_dual_sub_nc_u32 v16, 7, v6 :: v_dual_sub_nc_u32 v18, 7, v9
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1310-NEXT: v_min_u32_e32 v7, 31, v7
; GFX1310-NEXT: v_or_b32_e32 v14, 0x800000, v11
; GFX1310-NEXT: v_bfe_u32 v11, v11, 20, 1
; GFX1310-NEXT: v_bfe_u32 v5, v5, 20, 3
; GFX1310-NEXT: v_and_b32_e32 v17, 0x7fffff, v8
; GFX1310-NEXT: v_sub_nc_u32_e64 v15, v7, 1 clamp
; GFX1310-NEXT: v_min_u32_e32 v16, 31, v16
; GFX1310-NEXT: v_bfe_u32 v21, v14, v7, 1
; GFX1310-NEXT: v_frexp_mant_f32_e32 v10, v3
; GFX1310-NEXT: v_or_b32_e32 v22, 0x800000, v17
; GFX1310-NEXT: v_bfe_u32 v20, v14, 0, v15
; GFX1310-NEXT: v_min_u32_e32 v18, 31, v18
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1310-NEXT: v_and_b32_e32 v19, 0x7fffff, v10
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v20
; GFX1310-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc_lo
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v13
; GFX1310-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v7
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1310-NEXT: v_bitop3_b32 v11, v12, v13, v11 bitop3:0xe0
; GFX1310-NEXT: v_lshrrev_b32_e32 v15, v15, v14
; GFX1310-NEXT: v_bfe_u32 v13, v22, v16, 1
; GFX1310-NEXT: v_add_nc_u32_e32 v5, v5, v11
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_bitop3_b32 v15, v15, v20, v21 bitop3:0xe0
; GFX1310-NEXT: v_sub_nc_u32_e64 v20, v16, 1 clamp
; GFX1310-NEXT: v_dual_cndmask_b32 v7, 0, v15 :: v_dual_lshrrev_b32 v14, v7, v14
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX1310-NEXT: v_bfe_u32 v12, v22, 0, v20
; GFX1310-NEXT: v_lshrrev_b32_e32 v11, v20, v22
; GFX1310-NEXT: v_sub_nc_u32_e64 v15, v18, 1 clamp
; GFX1310-NEXT: v_add_nc_u32_e32 v7, v14, v7
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12
; GFX1310-NEXT: v_cmp_lt_i32_e64 s0, 7, v7
; GFX1310-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v5
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1310-NEXT: v_cndmask_b32_e64 v7, v7, 0, s0
; GFX1310-NEXT: v_bitop3_b32 v11, v11, v12, v13 bitop3:0xe0
; GFX1310-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc_lo
; GFX1310-NEXT: v_add_co_ci_u32_e64 v4, null, 14, v4, vcc_lo
; GFX1310-NEXT: v_cndmask_b32_e64 v12, 0, 8, s0
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v16
; GFX1310-NEXT: v_lshrrev_b32_e32 v14, v16, v22
; GFX1310-NEXT: v_or_b32_e32 v13, 0x800000, v19
; GFX1310-NEXT: v_lshl_or_b32 v5, v4, 3, v5
; GFX1310-NEXT: v_or_b32_e32 v7, v12, v7
; GFX1310-NEXT: v_cndmask_b32_e32 v11, 0, v11, vcc_lo
; GFX1310-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v4
; GFX1310-NEXT: v_cmp_neq_f32_e64 s0, 0, v1
; GFX1310-NEXT: v_bfe_u32 v12, v13, v18, 1
; GFX1310-NEXT: v_bfe_u32 v19, v19, 20, 1
; GFX1310-NEXT: v_dual_add_nc_u32 v11, v14, v11 :: v_dual_lshrrev_b32 v14, v15, v13
; GFX1310-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc_lo
; GFX1310-NEXT: v_bfe_u32 v5, v13, 0, v15
; GFX1310-NEXT: v_lshrrev_b32_e32 v13, v18, v13
; GFX1310-NEXT: v_frexp_mant_f32_e32 v15, v2
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX1310-NEXT: v_cndmask_b32_e64 v4, 0, v4, s0
; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v11
; GFX1310-NEXT: v_cndmask_b32_e64 v7, v11, 0, vcc_lo
; GFX1310-NEXT: v_cndmask_b32_e64 v11, 0, 8, vcc_lo
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v5
; GFX1310-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX1310-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v1
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1310-NEXT: v_bitop3_b32 v5, v14, v5, v12 bitop3:0xe0
; GFX1310-NEXT: v_and_b32_e32 v12, 0x7ffff, v8
; GFX1310-NEXT: v_frexp_exp_i32_f32_e32 v14, v2
; GFX1310-NEXT: v_cndmask_b32_e32 v1, 0xff, v4, vcc_lo
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v18
; GFX1310-NEXT: v_or_b32_e32 v4, v11, v7
; GFX1310-NEXT: v_bfe_u32 v11, v17, 20, 1
; GFX1310-NEXT: v_and_b32_e32 v17, 0x7ffff, v10
; GFX1310-NEXT: v_dual_lshrrev_b32 v7, 19, v8 :: v_dual_cndmask_b32 v5, 0, v5, vcc_lo
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12
; GFX1310-NEXT: v_sub_nc_u32_e32 v16, 7, v14
; GFX1310-NEXT: v_lshrrev_b32_e32 v18, 19, v10
; GFX1310-NEXT: v_bfe_u32 v10, v10, 20, 3
; GFX1310-NEXT: v_bfe_u32 v8, v8, 20, 3
; GFX1310-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v17
; GFX1310-NEXT: v_min_u32_e32 v16, 31, v16
; GFX1310-NEXT: v_lshlrev_b16 v1, 8, v1
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1310-NEXT: v_bitop3_b32 v7, v7, v12, v11 bitop3:0xe0
; GFX1310-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo
; GFX1310-NEXT: v_sub_nc_u32_e64 v21, v16, 1 clamp
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1310-NEXT: v_bitop3_b32 v12, v18, v17, v19 bitop3:0xe0
; GFX1310-NEXT: v_add_nc_u32_e32 v5, v13, v5
; GFX1310-NEXT: v_and_b32_e32 v13, 0x7fffff, v15
; GFX1310-NEXT: v_add_nc_u32_e32 v10, v10, v12
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v5
; GFX1310-NEXT: v_or_b32_e32 v20, 0x800000, v13
; GFX1310-NEXT: v_lshrrev_b32_e32 v12, 19, v15
; GFX1310-NEXT: v_bfe_u32 v13, v13, 20, 1
; GFX1310-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc_lo
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX1310-NEXT: v_bfe_u32 v11, v20, 0, v21
; GFX1310-NEXT: v_lshrrev_b32_e32 v18, v21, v20
; GFX1310-NEXT: v_and_b32_e32 v21, 0x7ffff, v15
; GFX1310-NEXT: v_bfe_u32 v17, v20, v16, 1
; GFX1310-NEXT: v_cndmask_b32_e64 v19, 0, 8, vcc_lo
; GFX1310-NEXT: v_cmp_ne_u32_e64 s0, 0, v11
; GFX1310-NEXT: v_add_nc_u32_e32 v7, v8, v7
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v21
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1310-NEXT: v_or_b32_e32 v5, v19, v5
; GFX1310-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX1310-NEXT: v_bitop3_b32 v11, v18, v11, v17 bitop3:0xe0
; GFX1310-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v16
; GFX1310-NEXT: v_lshrrev_b32_e32 v16, v16, v20
; GFX1310-NEXT: v_bitop3_b32 v12, v12, v17, v13 bitop3:0xe0
; GFX1310-NEXT: v_cndmask_b32_e32 v11, 0, v11, vcc_lo
; GFX1310-NEXT: v_bfe_u32 v13, v15, 20, 3
; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v10
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1310-NEXT: v_dual_add_nc_u32 v11, v16, v11 :: v_dual_add_nc_u32 v12, v13, v12
; GFX1310-NEXT: v_cndmask_b32_e64 v10, v10, 0, vcc_lo
; GFX1310-NEXT: v_add_co_ci_u32_e64 v9, null, 14, v9, vcc_lo
; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v11
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1310-NEXT: v_cmp_lt_i32_e64 s0, 7, v12
; GFX1310-NEXT: v_lshl_or_b32 v8, v9, 3, v10
; GFX1310-NEXT: v_cndmask_b32_e64 v10, v11, 0, vcc_lo
; GFX1310-NEXT: v_cndmask_b32_e64 v11, 0, 8, vcc_lo
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX1310-NEXT: v_cndmask_b32_e64 v12, v12, 0, s0
; GFX1310-NEXT: v_add_co_ci_u32_e64 v13, null, 14, v14, s0
; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v7
; GFX1310-NEXT: v_cmp_gt_i32_e64 s0, 1, v9
; GFX1310-NEXT: v_lshl_or_b32 v9, v13, 3, v12
; GFX1310-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc_lo
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_dual_cndmask_b32 v5, v8, v5, s0 :: v_dual_bitop2_b32 v8, v11, v10 bitop3:0x54
; GFX1310-NEXT: v_add_co_ci_u32_e64 v6, null, 14, v6, vcc_lo
; GFX1310-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v3
; GFX1310-NEXT: v_lshl_or_b32 v7, v6, 3, v7
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX1310-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc_lo
; GFX1310-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v13
; GFX1310-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc_lo
; GFX1310-NEXT: v_cmp_o_f32_e32 vcc_lo, v3, v3
; GFX1310-NEXT: v_cndmask_b32_e32 v3, 0xff, v5, vcc_lo
; GFX1310-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v2
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX1310-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc_lo
; GFX1310-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v6
; GFX1310-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc_lo
; GFX1310-NEXT: v_cmp_o_f32_e32 vcc_lo, v2, v2
; GFX1310-NEXT: v_lshlrev_b16 v3, 8, v3
; GFX1310-NEXT: v_cndmask_b32_e32 v2, 0xff, v5, vcc_lo
; GFX1310-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v0
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_bitop3_b16 v2, v2, v3, 0xff bitop3:0xec
; GFX1310-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc_lo
; GFX1310-NEXT: v_and_b32_e32 v3, 0xffff, v1
; GFX1310-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
; GFX1310-NEXT: v_lshl_or_b32 v3, v2, 16, v3
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_cndmask_b32_e32 v0, 0xff, v4, vcc_lo
; GFX1310-NEXT: v_lshlrev_b32_e32 v4, 16, v2
; GFX1310-NEXT: v_bitop3_b16 v0, v0, v1, 0xff bitop3:0xec
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1310-NEXT: v_dual_lshrrev_b32 v1, 8, v3 :: v_dual_lshrrev_b32 v3, 24, v4
; GFX1310-NEXT: s_set_pc_i64 s[30:31]
%r = call <4 x i8> @llvm.convert.to.arbitrary.fp.v4i8.v4f32(<4 x float> %x, metadata !"Float8E5M3FNU", metadata !"round.tonearest", i1 false)
ret <4 x i8> %r
}
define i8 @to_e5m3fnu_f32_sat(float %x) {
; GFX950-LABEL: to_e5m3fnu_f32_sat:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
; GFX950-NEXT: v_sub_u32_e32 v2, 7, v1
; GFX950-NEXT: v_frexp_mant_f32_e32 v3, v0
; GFX950-NEXT: v_min_u32_e32 v2, 31, v2
; GFX950-NEXT: v_and_b32_e32 v4, 0x7fffff, v3
; GFX950-NEXT: v_or_b32_e32 v5, 0x800000, v4
; GFX950-NEXT: v_sub_u32_e64 v7, v2, 1 clamp
; GFX950-NEXT: v_lshrrev_b32_e32 v8, v7, v5
; GFX950-NEXT: v_bfe_u32 v7, v5, 0, v7
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; GFX950-NEXT: v_bfe_u32 v6, v5, v2, 1
; GFX950-NEXT: v_bfe_u32 v4, v4, 20, 1
; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX950-NEXT: v_bitop3_b32 v6, v8, v7, v6 bitop3:0xe0
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GFX950-NEXT: v_lshrrev_b32_e32 v2, v2, v5
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
; GFX950-NEXT: v_add_u32_e32 v2, v2, v6
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v2
; GFX950-NEXT: v_and_b32_e32 v6, 0x7ffff, v3
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 8, vcc
; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; GFX950-NEXT: v_or_b32_e32 v2, v5, v2
; GFX950-NEXT: v_lshrrev_b32_e32 v5, 19, v3
; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX950-NEXT: v_bitop3_b32 v4, v5, v6, v4 bitop3:0xe0
; GFX950-NEXT: v_bfe_u32 v3, v3, 20, 3
; GFX950-NEXT: v_add_u32_e32 v3, v3, v4
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v3
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
; GFX950-NEXT: v_addc_co_u32_e32 v1, vcc, 14, v1, vcc
; GFX950-NEXT: v_lshl_or_b32 v4, v1, 3, v3
; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, 1, v1
; GFX950-NEXT: v_cmp_eq_u32_e64 s[0:1], 31, v1
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 6, v3
; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], vcc
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 31, v1
; GFX950-NEXT: v_mov_b32_e32 v1, 0xfe
; GFX950-NEXT: s_or_b64 vcc, vcc, s[0:1]
; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v1, vcc
; GFX950-NEXT: v_cmp_neq_f32_e32 vcc, 0, v0
; GFX950-NEXT: s_mov_b32 s0, 0x7f800000
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
; GFX950-NEXT: v_cmp_neq_f32_e64 vcc, |v0|, s0
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX950-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0
; GFX950-NEXT: v_mov_b32_e32 v2, 0xff
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: to_e5m3fnu_f32_sat:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT: s_wait_expcnt 0x0
; GFX1200-NEXT: s_wait_samplecnt 0x0
; GFX1200-NEXT: s_wait_bvhcnt 0x0
; GFX1200-NEXT: s_wait_kmcnt 0x0
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
; GFX1200-NEXT: v_frexp_mant_f32_e32 v3, v0
; GFX1200-NEXT: s_mov_b32 s0, 0x7fffff
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_sub_nc_u32_e32 v2, 7, v1
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_and_or_b32 v4, v3, s0, 0x800000
; GFX1200-NEXT: v_and_b32_e32 v8, 0x7ffff, v3
; GFX1200-NEXT: v_bfe_u32 v9, v3, 20, 3
; GFX1200-NEXT: v_lshrrev_b32_e32 v3, 19, v3
; GFX1200-NEXT: v_min_u32_e32 v2, 31, v2
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_sub_nc_u32_e64 v5, v2, 1 clamp
; GFX1200-NEXT: v_lshrrev_b32_e32 v7, v2, v4
; GFX1200-NEXT: v_bfe_u32 v6, v4, 0, v5
; GFX1200-NEXT: v_lshrrev_b32_e32 v4, v5, v4
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; GFX1200-NEXT: v_and_or_b32 v5, v7, 1, v6
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_and_b32_e32 v4, v4, v5
; GFX1200-NEXT: v_and_or_b32 v5, v9, 1, v6
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_dual_cndmask_b32 v2, 0, v4 :: v_dual_and_b32 v3, v3, v5
; GFX1200-NEXT: v_add_nc_u32_e32 v2, v7, v2
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_add_nc_u32_e32 v3, v9, v3
; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v2
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cmp_lt_i32_e64 s0, 7, v3
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v3, v3, 0, s0
; GFX1200-NEXT: v_cndmask_b32_e64 v4, 0, 8, vcc_lo
; GFX1200-NEXT: v_add_co_ci_u32_e64 v1, null, 14, v1, s0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 6, v3
; GFX1200-NEXT: v_or_b32_e32 v2, v4, v2
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_lshl_or_b32 v4, v1, 3, v3
; GFX1200-NEXT: v_cmp_gt_i32_e64 s2, 1, v1
; GFX1200-NEXT: v_cmp_eq_u32_e64 s0, 31, v1
; GFX1200-NEXT: v_cmp_lt_i32_e64 s1, 31, v1
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v1, v4, v2, s2
; GFX1200-NEXT: s_and_b32 s0, s0, vcc_lo
; GFX1200-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v0
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_or_b32 s0, s1, s0
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v1, v1, 0xfe, s0
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo
; GFX1200-NEXT: v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v1, 0xfe, v1, vcc_lo
; GFX1200-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v0
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo
; GFX1200-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v0, 0xff, v1, vcc_lo
; GFX1200-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-TRUE16-LABEL: to_e5m3fnu_f32_sat:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v0.l, v0, v0 clamp
; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1250-FAKE16-LABEL: to_e5m3fnu_f32_sat:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v0, v0, v0 clamp
; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1310-LABEL: to_e5m3fnu_f32_sat:
; GFX1310: ; %bb.0:
; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1310-NEXT: s_wait_expcnt 0x0
; GFX1310-NEXT: s_wait_samplecnt 0x0
; GFX1310-NEXT: s_wait_bvhcnt 0x0
; GFX1310-NEXT: s_wait_kmcnt 0x0
; GFX1310-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
; GFX1310-NEXT: v_frexp_mant_f32_e32 v2, v0
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX1310-NEXT: v_dual_sub_nc_u32 v3, 7, v1 :: v_dual_lshrrev_b32 v10, 19, v2
; GFX1310-NEXT: v_and_b32_e32 v4, 0x7fffff, v2
; GFX1310-NEXT: v_and_b32_e32 v9, 0x7ffff, v2
; GFX1310-NEXT: v_bfe_u32 v2, v2, 20, 3
; GFX1310-NEXT: v_min_u32_e32 v3, 31, v3
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1310-NEXT: v_or_b32_e32 v5, 0x800000, v4
; GFX1310-NEXT: v_bfe_u32 v4, v4, 20, 1
; GFX1310-NEXT: v_sub_nc_u32_e64 v6, v3, 1 clamp
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_bfe_u32 v8, v5, v3, 1
; GFX1310-NEXT: v_bfe_u32 v7, v5, 0, v6
; GFX1310-NEXT: v_dual_lshrrev_b32 v6, v6, v5 :: v_dual_lshrrev_b32 v5, v3, v5
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v7
; GFX1310-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v9
; GFX1310-NEXT: v_bitop3_b32 v6, v6, v7, v8 bitop3:0xe0
; GFX1310-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1310-NEXT: v_bitop3_b32 v4, v10, v7, v4 bitop3:0xe0
; GFX1310-NEXT: v_dual_cndmask_b32 v3, 0, v6 :: v_dual_add_nc_u32 v2, v2, v4
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_add_nc_u32_e32 v3, v5, v3
; GFX1310-NEXT: v_cmp_lt_i32_e64 s0, 7, v2
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v3
; GFX1310-NEXT: v_cndmask_b32_e64 v2, v2, 0, s0
; GFX1310-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo
; GFX1310-NEXT: v_cndmask_b32_e64 v4, 0, 8, vcc_lo
; GFX1310-NEXT: v_add_co_ci_u32_e64 v1, null, 14, v1, s0
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 6, v2
; GFX1310-NEXT: v_or_b32_e32 v3, v4, v3
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX1310-NEXT: v_lshl_or_b32 v4, v1, 3, v2
; GFX1310-NEXT: v_cmp_gt_i32_e64 s2, 1, v1
; GFX1310-NEXT: v_cmp_eq_u32_e64 s0, 31, v1
; GFX1310-NEXT: v_cmp_lt_i32_e64 s1, 31, v1
; GFX1310-NEXT: v_cndmask_b32_e64 v1, v4, v3, s2
; GFX1310-NEXT: s_and_b32 s0, s0, vcc_lo
; GFX1310-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v0
; GFX1310-NEXT: s_or_b32 s0, s1, s0
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
; GFX1310-NEXT: v_cndmask_b32_e64 v1, v1, 0xfe, s0
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo
; GFX1310-NEXT: v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1310-NEXT: v_cndmask_b32_e32 v1, 0xfe, v1, vcc_lo
; GFX1310-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v0
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo
; GFX1310-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
; GFX1310-NEXT: v_cndmask_b32_e32 v0, 0xff, v1, vcc_lo
; GFX1310-NEXT: s_set_pc_i64 s[30:31]
%r = call i8 @llvm.convert.to.arbitrary.fp.i8.f32(float %x, metadata !"Float8E5M3FNU", metadata !"round.tonearest", i1 true)
ret i8 %r
}
define i8 @to_e5m3fnu_f32_rtz(float %x) {
; GFX950-LABEL: to_e5m3fnu_f32_rtz:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_frexp_mant_f32_e32 v1, v0
; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v3, v0
; GFX950-NEXT: v_and_b32_e32 v2, 0x7fffff, v1
; GFX950-NEXT: v_sub_u32_e32 v4, 7, v3
; GFX950-NEXT: v_or_b32_e32 v2, 0x800000, v2
; GFX950-NEXT: v_min_u32_e32 v4, 31, v4
; GFX950-NEXT: v_lshrrev_b32_e32 v2, v4, v2
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v2
; GFX950-NEXT: v_bfe_u32 v1, v1, 20, 3
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 8, vcc
; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v1
; GFX950-NEXT: v_or_b32_e32 v2, v4, v2
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
; GFX950-NEXT: v_addc_co_u32_e32 v3, vcc, 14, v3, vcc
; GFX950-NEXT: v_lshl_or_b32 v1, v3, 3, v1
; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX950-NEXT: v_cmp_neq_f32_e32 vcc, 0, v0
; GFX950-NEXT: v_mov_b32_e32 v2, 0xff
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-LABEL: to_e5m3fnu_f32_rtz:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT: s_wait_expcnt 0x0
; GFX1200-NEXT: s_wait_samplecnt 0x0
; GFX1200-NEXT: s_wait_bvhcnt 0x0
; GFX1200-NEXT: s_wait_kmcnt 0x0
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
; GFX1200-NEXT: v_frexp_mant_f32_e32 v2, v0
; GFX1200-NEXT: s_mov_b32 s0, 0x7fffff
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_sub_nc_u32_e32 v3, 7, v1
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_and_or_b32 v4, v2, s0, 0x800000
; GFX1200-NEXT: v_bfe_u32 v2, v2, 20, 3
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_min_u32_e32 v3, 31, v3
; GFX1200-NEXT: v_cmp_lt_i32_e64 s0, 7, v2
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_lshrrev_b32_e32 v3, v3, v4
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v2, v2, 0, s0
; GFX1200-NEXT: v_add_co_ci_u32_e64 v1, null, 14, v1, s0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v3
; GFX1200-NEXT: v_lshl_or_b32 v2, v1, 3, v2
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo
; GFX1200-NEXT: v_cndmask_b32_e64 v4, 0, 8, vcc_lo
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_or_b32_e32 v3, v4, v3
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo
; GFX1200-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v0
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo
; GFX1200-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v0, 0xff, v1, vcc_lo
; GFX1200-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: to_e5m3fnu_f32_rtz:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
; GFX1250-NEXT: v_frexp_mant_f32_e32 v2, v0
; GFX1250-NEXT: s_mov_b32 s0, 0x7fffff
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_sub_nc_u32_e32 v3, 7, v1
; GFX1250-NEXT: v_and_or_b32 v4, v2, s0, 0x800000
; GFX1250-NEXT: v_bfe_u32 v2, v2, 20, 3
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_min_u32_e32 v3, 31, v3
; GFX1250-NEXT: v_cmp_lt_i32_e64 s0, 7, v2
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_lshrrev_b32_e32 v3, v3, v4
; GFX1250-NEXT: v_cndmask_b32_e64 v2, v2, 0, s0
; GFX1250-NEXT: v_add_co_ci_u32_e64 v1, null, 14, v1, s0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v3
; GFX1250-NEXT: v_lshl_or_b32 v2, v1, 3, v2
; GFX1250-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo
; GFX1250-NEXT: v_cndmask_b32_e64 v4, 0, 8, vcc_lo
; GFX1250-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v1
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_or_b32_e32 v3, v4, v3
; GFX1250-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo
; GFX1250-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo
; GFX1250-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
; GFX1250-NEXT: v_cndmask_b32_e32 v0, 0xff, v1, vcc_lo
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1310-LABEL: to_e5m3fnu_f32_rtz:
; GFX1310: ; %bb.0:
; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1310-NEXT: s_wait_expcnt 0x0
; GFX1310-NEXT: s_wait_samplecnt 0x0
; GFX1310-NEXT: s_wait_bvhcnt 0x0
; GFX1310-NEXT: s_wait_kmcnt 0x0
; GFX1310-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
; GFX1310-NEXT: v_frexp_mant_f32_e32 v2, v0
; GFX1310-NEXT: s_mov_b32 s0, 0x7fffff
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_sub_nc_u32_e32 v3, 7, v1
; GFX1310-NEXT: v_and_or_b32 v4, v2, s0, 0x800000
; GFX1310-NEXT: v_bfe_u32 v2, v2, 20, 3
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_min_u32_e32 v3, 31, v3
; GFX1310-NEXT: v_cmp_lt_i32_e64 s0, 7, v2
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_lshrrev_b32_e32 v3, v3, v4
; GFX1310-NEXT: v_cndmask_b32_e64 v2, v2, 0, s0
; GFX1310-NEXT: v_add_co_ci_u32_e64 v1, null, 14, v1, s0
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v3
; GFX1310-NEXT: v_lshl_or_b32 v2, v1, 3, v2
; GFX1310-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo
; GFX1310-NEXT: v_cndmask_b32_e64 v4, 0, 8, vcc_lo
; GFX1310-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v1
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1310-NEXT: v_or_b32_e32 v3, v4, v3
; GFX1310-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo
; GFX1310-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v0
; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1310-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo
; GFX1310-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
; GFX1310-NEXT: v_cndmask_b32_e32 v0, 0xff, v1, vcc_lo
; GFX1310-NEXT: s_set_pc_i64 s[30:31]
%r = call i8 @llvm.convert.to.arbitrary.fp.i8.f32(float %x, metadata !"Float8E5M3FNU", metadata !"round.towardzero", i1 false)
ret i8 %r
}