blob: a178c5ab24b3d931ee7617dfaf15ac7a93e1a199 [file] [log] [blame] [edit]
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-simplifylib %s | FileCheck %s
define float @test_tdo_scalar_f32_atan() {
; CHECK-LABEL: define float @test_tdo_scalar_f32_atan() {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: ret float 0.000000e+00
;
entry:
%c = call float @_Z4atanf(float 0.000000e+00)
ret float %c
}
define <4 x float> @test_tdo_v2_f32_atan() {
; CHECK-LABEL: define <4 x float> @test_tdo_v2_f32_atan() {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: ret <4 x float> <float 0.000000e+00, float -0.000000e+00, float 0x3FE921FB60000000, float 0xBFE921FB60000000>
;
entry:
%c = call <4 x float> @_Z4atanDv4_f(<4 x float> <float 0.000000e+00, float -0.000000e+00, float 1.000000e+00, float -1.000000e+00>)
ret <4 x float> %c
}
define half @test_tdo_scalar_f16_atan() {
; CHECK-LABEL: define half @test_tdo_scalar_f16_atan() {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: ret half 0xH0000
;
entry:
%c = call half @_Z4atanDh(half 0.000000e+00)
ret half %c
}
define <4 x half> @test_tdo_v2_f16_atan() {
; CHECK-LABEL: define <4 x half> @test_tdo_v2_f16_atan() {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: ret <4 x half> <half 0xH0000, half 0xH8000, half 0xH3A48, half 0xHBA48>
;
entry:
%c = call <4 x half> @_Z4atanDv4_Dh(<4 x half> <half 0.000000e+00, half -0.000000e+00, half 1.000000e+00, half -1.000000e+00>)
ret <4 x half> %c
}
define double @test_tdo_scalar_f64_atan() {
; CHECK-LABEL: define double @test_tdo_scalar_f64_atan() {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: ret double 0.000000e+00
;
entry:
%c = call double @_Z4atand(double 0.000000e+00)
ret double %c
}
define <4 x double> @test_tdo_v2_f64_atan() {
; CHECK-LABEL: define <4 x double> @test_tdo_v2_f64_atan() {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: ret <4 x double> <double 0.000000e+00, double -0.000000e+00, double 0x3FE921FB54442D18, double 0xBFE921FB54442D18>
;
entry:
%c = call <4 x double> @_Z4atanDv4_d(<4 x double> <double 0.000000e+00, double -0.000000e+00, double 1.000000e+00, double -1.000000e+00>)
ret <4 x double> %c
}
declare float @_Z4atanf(float)
declare <4 x float> @_Z4atanDv4_f(<4 x float>)
declare half @_Z4atanDh(half)
declare <4 x half> @_Z4atanDv4_Dh(<4 x half>)
declare double @_Z4atand(double)
declare <4 x double> @_Z4atanDv4_d(<4 x double>)