llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ptr.s.buffer.load.ll - llvm-project - Git at Google

 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
 ; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgpu7.00-mesa-mesa3d -simplify-mir -stop-after=amdgpu-regbanklegalize -o - %s | FileCheck %s -check-prefix=GFX7
 ; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -simplify-mir -stop-after=amdgpu-regbanklegalize -o - %s | FileCheck %s -check-prefixes=GFX1200_1250,GFX1200
 ; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgpu12.50-mesa-mesa3d -simplify-mir -stop-after=amdgpu-regbanklegalize -o - %s | FileCheck %s -check-prefixes=GFX1200_1250,GFX1250

 ; Natural mapping
 define amdgpu_ps i32 @ptr_s_buffer_load_i32(ptr addrspace(8) inreg %rsrc, i32 inreg %soffset) {
   ; GFX7-LABEL: name: ptr_s_buffer_load_i32
   ; GFX7: bb.1 (%ir-block.0):
   ; GFX7-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
   ; GFX7-NEXT: {{  $}}
   ; GFX7-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX7-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX7-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX7-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX7-NEXT:   [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
   ; GFX7-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX7-NEXT:   [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(i32) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[COPY4]](i32), 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8)
   ; GFX7-NEXT:   [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[AMDGPU_S_BUFFER_LOAD]](i32)
   ; GFX7-NEXT:   [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](i32)
   ; GFX7-NEXT:   $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](i32)
   ; GFX7-NEXT:   SI_RETURN_TO_EPILOG implicit $sgpr0
   ;
   ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32
   ; GFX1200_1250: bb.1 (%ir-block.0):
   ; GFX1200_1250-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
   ; GFX1200_1250-NEXT: {{  $}}
   ; GFX1200_1250-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX1200_1250-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX1200_1250-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX1200_1250-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX1200_1250-NEXT:   [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
   ; GFX1200_1250-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX1200_1250-NEXT:   [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(i32) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[COPY4]](i32), 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8)
   ; GFX1200_1250-NEXT:   [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[AMDGPU_S_BUFFER_LOAD]](i32)
   ; GFX1200_1250-NEXT:   [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](i32)
   ; GFX1200_1250-NEXT:   $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](i32)
   ; GFX1200_1250-NEXT:   SI_RETURN_TO_EPILOG implicit $sgpr0
   %val = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0
   ret i32 %val
 }

 define amdgpu_ps <2 x i32> @ptr_s_buffer_load_v2i32(ptr addrspace(8) inreg %rsrc, i32 inreg %soffset) {
   ; GFX7-LABEL: name: ptr_s_buffer_load_v2i32
   ; GFX7: bb.1 (%ir-block.0):
   ; GFX7-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
   ; GFX7-NEXT: {{  $}}
   ; GFX7-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX7-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX7-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX7-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX7-NEXT:   [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
   ; GFX7-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX7-NEXT:   [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<2 x i32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[COPY4]](i32), 0 :: (dereferenceable invariant load (<2 x i32>) from %ir.rsrc, align 1, addrspace 8)
   ; GFX7-NEXT:   [[UV:%[0-9]+]]:sgpr(i32), [[UV1:%[0-9]+]]:sgpr(i32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<2 x i32>)
   ; GFX7-NEXT:   [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[UV]](i32)
   ; GFX7-NEXT:   [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](i32)
   ; GFX7-NEXT:   $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](i32)
   ; GFX7-NEXT:   [[COPY6:%[0-9]+]]:vgpr(i32) = COPY [[UV1]](i32)
   ; GFX7-NEXT:   [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32)
   ; GFX7-NEXT:   $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](i32)
   ; GFX7-NEXT:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
   ;
   ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v2i32
   ; GFX1200_1250: bb.1 (%ir-block.0):
   ; GFX1200_1250-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
   ; GFX1200_1250-NEXT: {{  $}}
   ; GFX1200_1250-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX1200_1250-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX1200_1250-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX1200_1250-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX1200_1250-NEXT:   [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
   ; GFX1200_1250-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX1200_1250-NEXT:   [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<2 x i32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[COPY4]](i32), 0 :: (dereferenceable invariant load (<2 x i32>) from %ir.rsrc, align 1, addrspace 8)
   ; GFX1200_1250-NEXT:   [[UV:%[0-9]+]]:sgpr(i32), [[UV1:%[0-9]+]]:sgpr(i32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<2 x i32>)
   ; GFX1200_1250-NEXT:   [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[UV]](i32)
   ; GFX1200_1250-NEXT:   [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](i32)
   ; GFX1200_1250-NEXT:   $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](i32)
   ; GFX1200_1250-NEXT:   [[COPY6:%[0-9]+]]:vgpr(i32) = COPY [[UV1]](i32)
   ; GFX1200_1250-NEXT:   [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32)
   ; GFX1200_1250-NEXT:   $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](i32)
   ; GFX1200_1250-NEXT:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
   %val = call <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0
   ret <2 x i32> %val
 }

 define amdgpu_ps <3 x i32> @ptr_s_buffer_load_v3i32(ptr addrspace(8) inreg %rsrc, i32 inreg %soffset) {
   ; GFX7-LABEL: name: ptr_s_buffer_load_v3i32
   ; GFX7: bb.1 (%ir-block.0):
   ; GFX7-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
   ; GFX7-NEXT: {{  $}}
   ; GFX7-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX7-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX7-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX7-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX7-NEXT:   [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
   ; GFX7-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX7-NEXT:   [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<4 x i32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[COPY4]](i32), 0 :: (dereferenceable invariant load (<3 x i32>) from %ir.rsrc, align 1, addrspace 8)
   ; GFX7-NEXT:   [[UV:%[0-9]+]]:sgpr(i32), [[UV1:%[0-9]+]]:sgpr(i32), [[UV2:%[0-9]+]]:sgpr(i32), [[UV3:%[0-9]+]]:sgpr(i32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<4 x i32>)
   ; GFX7-NEXT:   [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[UV]](i32)
   ; GFX7-NEXT:   [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](i32)
   ; GFX7-NEXT:   $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](i32)
   ; GFX7-NEXT:   [[COPY6:%[0-9]+]]:vgpr(i32) = COPY [[UV1]](i32)
   ; GFX7-NEXT:   [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32)
   ; GFX7-NEXT:   $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](i32)
   ; GFX7-NEXT:   [[COPY7:%[0-9]+]]:vgpr(i32) = COPY [[UV2]](i32)
   ; GFX7-NEXT:   [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY7]](i32)
   ; GFX7-NEXT:   $sgpr2 = COPY [[INTRINSIC_CONVERGENT2]](i32)
   ; GFX7-NEXT:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2
   ;
   ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v3i32
   ; GFX1200_1250: bb.1 (%ir-block.0):
   ; GFX1200_1250-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
   ; GFX1200_1250-NEXT: {{  $}}
   ; GFX1200_1250-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX1200_1250-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX1200_1250-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX1200_1250-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX1200_1250-NEXT:   [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
   ; GFX1200_1250-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX1200_1250-NEXT:   [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<3 x i32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[COPY4]](i32), 0 :: (dereferenceable invariant load (<3 x i32>) from %ir.rsrc, align 1, addrspace 8)
   ; GFX1200_1250-NEXT:   [[UV:%[0-9]+]]:sgpr(i32), [[UV1:%[0-9]+]]:sgpr(i32), [[UV2:%[0-9]+]]:sgpr(i32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<3 x i32>)
   ; GFX1200_1250-NEXT:   [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[UV]](i32)
   ; GFX1200_1250-NEXT:   [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](i32)
   ; GFX1200_1250-NEXT:   $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](i32)
   ; GFX1200_1250-NEXT:   [[COPY6:%[0-9]+]]:vgpr(i32) = COPY [[UV1]](i32)
   ; GFX1200_1250-NEXT:   [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32)
   ; GFX1200_1250-NEXT:   $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](i32)
   ; GFX1200_1250-NEXT:   [[COPY7:%[0-9]+]]:vgpr(i32) = COPY [[UV2]](i32)
   ; GFX1200_1250-NEXT:   [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY7]](i32)
   ; GFX1200_1250-NEXT:   $sgpr2 = COPY [[INTRINSIC_CONVERGENT2]](i32)
   ; GFX1200_1250-NEXT:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2
   %val = call <3 x i32> @llvm.amdgcn.ptr.s.buffer.load.v3i32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0
   ret <3 x i32> %val
 }

 define amdgpu_ps <8 x i32> @ptr_s_buffer_load_v8i32(ptr addrspace(8) inreg %rsrc, i32 inreg %soffset) {
   ; GFX7-LABEL: name: ptr_s_buffer_load_v8i32
   ; GFX7: bb.1 (%ir-block.0):
   ; GFX7-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
   ; GFX7-NEXT: {{  $}}
   ; GFX7-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX7-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX7-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX7-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX7-NEXT:   [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
   ; GFX7-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX7-NEXT:   [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<8 x i32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[COPY4]](i32), 0 :: (dereferenceable invariant load (<8 x i32>) from %ir.rsrc, align 1, addrspace 8)
   ; GFX7-NEXT:   [[UV:%[0-9]+]]:sgpr(i32), [[UV1:%[0-9]+]]:sgpr(i32), [[UV2:%[0-9]+]]:sgpr(i32), [[UV3:%[0-9]+]]:sgpr(i32), [[UV4:%[0-9]+]]:sgpr(i32), [[UV5:%[0-9]+]]:sgpr(i32), [[UV6:%[0-9]+]]:sgpr(i32), [[UV7:%[0-9]+]]:sgpr(i32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<8 x i32>)
   ; GFX7-NEXT:   [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[UV]](i32)
   ; GFX7-NEXT:   [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](i32)
   ; GFX7-NEXT:   $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](i32)
   ; GFX7-NEXT:   [[COPY6:%[0-9]+]]:vgpr(i32) = COPY [[UV1]](i32)
   ; GFX7-NEXT:   [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32)
   ; GFX7-NEXT:   $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](i32)
   ; GFX7-NEXT:   [[COPY7:%[0-9]+]]:vgpr(i32) = COPY [[UV2]](i32)
   ; GFX7-NEXT:   [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY7]](i32)
   ; GFX7-NEXT:   $sgpr2 = COPY [[INTRINSIC_CONVERGENT2]](i32)
   ; GFX7-NEXT:   [[COPY8:%[0-9]+]]:vgpr(i32) = COPY [[UV3]](i32)
   ; GFX7-NEXT:   [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY8]](i32)
   ; GFX7-NEXT:   $sgpr3 = COPY [[INTRINSIC_CONVERGENT3]](i32)
   ; GFX7-NEXT:   [[COPY9:%[0-9]+]]:vgpr(i32) = COPY [[UV4]](i32)
   ; GFX7-NEXT:   [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY9]](i32)
   ; GFX7-NEXT:   $sgpr4 = COPY [[INTRINSIC_CONVERGENT4]](i32)
   ; GFX7-NEXT:   [[COPY10:%[0-9]+]]:vgpr(i32) = COPY [[UV5]](i32)
   ; GFX7-NEXT:   [[INTRINSIC_CONVERGENT5:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY10]](i32)
   ; GFX7-NEXT:   $sgpr5 = COPY [[INTRINSIC_CONVERGENT5]](i32)
   ; GFX7-NEXT:   [[COPY11:%[0-9]+]]:vgpr(i32) = COPY [[UV6]](i32)
   ; GFX7-NEXT:   [[INTRINSIC_CONVERGENT6:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY11]](i32)
   ; GFX7-NEXT:   $sgpr6 = COPY [[INTRINSIC_CONVERGENT6]](i32)
   ; GFX7-NEXT:   [[COPY12:%[0-9]+]]:vgpr(i32) = COPY [[UV7]](i32)
   ; GFX7-NEXT:   [[INTRINSIC_CONVERGENT7:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY12]](i32)
   ; GFX7-NEXT:   $sgpr7 = COPY [[INTRINSIC_CONVERGENT7]](i32)
   ; GFX7-NEXT:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7
   ;
   ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v8i32
   ; GFX1200_1250: bb.1 (%ir-block.0):
   ; GFX1200_1250-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
   ; GFX1200_1250-NEXT: {{  $}}
   ; GFX1200_1250-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX1200_1250-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX1200_1250-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX1200_1250-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX1200_1250-NEXT:   [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
   ; GFX1200_1250-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX1200_1250-NEXT:   [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<8 x i32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[COPY4]](i32), 0 :: (dereferenceable invariant load (<8 x i32>) from %ir.rsrc, align 1, addrspace 8)
   ; GFX1200_1250-NEXT:   [[UV:%[0-9]+]]:sgpr(i32), [[UV1:%[0-9]+]]:sgpr(i32), [[UV2:%[0-9]+]]:sgpr(i32), [[UV3:%[0-9]+]]:sgpr(i32), [[UV4:%[0-9]+]]:sgpr(i32), [[UV5:%[0-9]+]]:sgpr(i32), [[UV6:%[0-9]+]]:sgpr(i32), [[UV7:%[0-9]+]]:sgpr(i32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<8 x i32>)
   ; GFX1200_1250-NEXT:   [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[UV]](i32)
   ; GFX1200_1250-NEXT:   [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](i32)
   ; GFX1200_1250-NEXT:   $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](i32)
   ; GFX1200_1250-NEXT:   [[COPY6:%[0-9]+]]:vgpr(i32) = COPY [[UV1]](i32)
   ; GFX1200_1250-NEXT:   [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32)
   ; GFX1200_1250-NEXT:   $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](i32)
   ; GFX1200_1250-NEXT:   [[COPY7:%[0-9]+]]:vgpr(i32) = COPY [[UV2]](i32)
   ; GFX1200_1250-NEXT:   [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY7]](i32)
   ; GFX1200_1250-NEXT:   $sgpr2 = COPY [[INTRINSIC_CONVERGENT2]](i32)
   ; GFX1200_1250-NEXT:   [[COPY8:%[0-9]+]]:vgpr(i32) = COPY [[UV3]](i32)
   ; GFX1200_1250-NEXT:   [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY8]](i32)
   ; GFX1200_1250-NEXT:   $sgpr3 = COPY [[INTRINSIC_CONVERGENT3]](i32)
   ; GFX1200_1250-NEXT:   [[COPY9:%[0-9]+]]:vgpr(i32) = COPY [[UV4]](i32)
   ; GFX1200_1250-NEXT:   [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY9]](i32)
   ; GFX1200_1250-NEXT:   $sgpr4 = COPY [[INTRINSIC_CONVERGENT4]](i32)
   ; GFX1200_1250-NEXT:   [[COPY10:%[0-9]+]]:vgpr(i32) = COPY [[UV5]](i32)
   ; GFX1200_1250-NEXT:   [[INTRINSIC_CONVERGENT5:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY10]](i32)
   ; GFX1200_1250-NEXT:   $sgpr5 = COPY [[INTRINSIC_CONVERGENT5]](i32)
   ; GFX1200_1250-NEXT:   [[COPY11:%[0-9]+]]:vgpr(i32) = COPY [[UV6]](i32)
   ; GFX1200_1250-NEXT:   [[INTRINSIC_CONVERGENT6:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY11]](i32)
   ; GFX1200_1250-NEXT:   $sgpr6 = COPY [[INTRINSIC_CONVERGENT6]](i32)
   ; GFX1200_1250-NEXT:   [[COPY12:%[0-9]+]]:vgpr(i32) = COPY [[UV7]](i32)
   ; GFX1200_1250-NEXT:   [[INTRINSIC_CONVERGENT7:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY12]](i32)
   ; GFX1200_1250-NEXT:   $sgpr7 = COPY [[INTRINSIC_CONVERGENT7]](i32)
   ; GFX1200_1250-NEXT:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7
   %val = call <8 x i32> @llvm.amdgcn.ptr.s.buffer.load.v8i32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0
   ret <8 x i32> %val
 }

 define amdgpu_ps <16 x i32> @ptr_s_buffer_load_v16i32(ptr addrspace(8) inreg %rsrc, i32 inreg %soffset) {
   ; GFX7-LABEL: name: ptr_s_buffer_load_v16i32
   ; GFX7: bb.1 (%ir-block.0):
   ; GFX7-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
   ; GFX7-NEXT: {{  $}}
   ; GFX7-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX7-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX7-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX7-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX7-NEXT:   [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
   ; GFX7-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX7-NEXT:   [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<16 x i32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[COPY4]](i32), 0 :: (dereferenceable invariant load (<16 x i32>) from %ir.rsrc, align 1, addrspace 8)
   ; GFX7-NEXT:   [[UV:%[0-9]+]]:sgpr(i32), [[UV1:%[0-9]+]]:sgpr(i32), [[UV2:%[0-9]+]]:sgpr(i32), [[UV3:%[0-9]+]]:sgpr(i32), [[UV4:%[0-9]+]]:sgpr(i32), [[UV5:%[0-9]+]]:sgpr(i32), [[UV6:%[0-9]+]]:sgpr(i32), [[UV7:%[0-9]+]]:sgpr(i32), [[UV8:%[0-9]+]]:sgpr(i32), [[UV9:%[0-9]+]]:sgpr(i32), [[UV10:%[0-9]+]]:sgpr(i32), [[UV11:%[0-9]+]]:sgpr(i32), [[UV12:%[0-9]+]]:sgpr(i32), [[UV13:%[0-9]+]]:sgpr(i32), [[UV14:%[0-9]+]]:sgpr(i32), [[UV15:%[0-9]+]]:sgpr(i32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<16 x i32>)
   ; GFX7-NEXT:   [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[UV]](i32)
   ; GFX7-NEXT:   [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](i32)
   ; GFX7-NEXT:   $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](i32)
   ; GFX7-NEXT:   [[COPY6:%[0-9]+]]:vgpr(i32) = COPY [[UV1]](i32)
   ; GFX7-NEXT:   [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32)
   ; GFX7-NEXT:   $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](i32)
   ; GFX7-NEXT:   [[COPY7:%[0-9]+]]:vgpr(i32) = COPY [[UV2]](i32)
   ; GFX7-NEXT:   [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY7]](i32)
   ; GFX7-NEXT:   $sgpr2 = COPY [[INTRINSIC_CONVERGENT2]](i32)
   ; GFX7-NEXT:   [[COPY8:%[0-9]+]]:vgpr(i32) = COPY [[UV3]](i32)
   ; GFX7-NEXT:   [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY8]](i32)
   ; GFX7-NEXT:   $sgpr3 = COPY [[INTRINSIC_CONVERGENT3]](i32)
   ; GFX7-NEXT:   [[COPY9:%[0-9]+]]:vgpr(i32) = COPY [[UV4]](i32)
   ; GFX7-NEXT:   [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY9]](i32)
   ; GFX7-NEXT:   $sgpr4 = COPY [[INTRINSIC_CONVERGENT4]](i32)
   ; GFX7-NEXT:   [[COPY10:%[0-9]+]]:vgpr(i32) = COPY [[UV5]](i32)
   ; GFX7-NEXT:   [[INTRINSIC_CONVERGENT5:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY10]](i32)
   ; GFX7-NEXT:   $sgpr5 = COPY [[INTRINSIC_CONVERGENT5]](i32)
   ; GFX7-NEXT:   [[COPY11:%[0-9]+]]:vgpr(i32) = COPY [[UV6]](i32)
   ; GFX7-NEXT:   [[INTRINSIC_CONVERGENT6:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY11]](i32)
   ; GFX7-NEXT:   $sgpr6 = COPY [[INTRINSIC_CONVERGENT6]](i32)
   ; GFX7-NEXT:   [[COPY12:%[0-9]+]]:vgpr(i32) = COPY [[UV7]](i32)
   ; GFX7-NEXT:   [[INTRINSIC_CONVERGENT7:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY12]](i32)
   ; GFX7-NEXT:   $sgpr7 = COPY [[INTRINSIC_CONVERGENT7]](i32)
   ; GFX7-NEXT:   [[COPY13:%[0-9]+]]:vgpr(i32) = COPY [[UV8]](i32)
   ; GFX7-NEXT:   [[INTRINSIC_CONVERGENT8:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY13]](i32)
   ; GFX7-NEXT:   $sgpr8 = COPY [[INTRINSIC_CONVERGENT8]](i32)
   ; GFX7-NEXT:   [[COPY14:%[0-9]+]]:vgpr(i32) = COPY [[UV9]](i32)
   ; GFX7-NEXT:   [[INTRINSIC_CONVERGENT9:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY14]](i32)
   ; GFX7-NEXT:   $sgpr9 = COPY [[INTRINSIC_CONVERGENT9]](i32)
   ; GFX7-NEXT:   [[COPY15:%[0-9]+]]:vgpr(i32) = COPY [[UV10]](i32)
   ; GFX7-NEXT:   [[INTRINSIC_CONVERGENT10:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY15]](i32)
   ; GFX7-NEXT:   $sgpr10 = COPY [[INTRINSIC_CONVERGENT10]](i32)
   ; GFX7-NEXT:   [[COPY16:%[0-9]+]]:vgpr(i32) = COPY [[UV11]](i32)
   ; GFX7-NEXT:   [[INTRINSIC_CONVERGENT11:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY16]](i32)
   ; GFX7-NEXT:   $sgpr11 = COPY [[INTRINSIC_CONVERGENT11]](i32)
   ; GFX7-NEXT:   [[COPY17:%[0-9]+]]:vgpr(i32) = COPY [[UV12]](i32)
   ; GFX7-NEXT:   [[INTRINSIC_CONVERGENT12:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY17]](i32)
   ; GFX7-NEXT:   $sgpr12 = COPY [[INTRINSIC_CONVERGENT12]](i32)
   ; GFX7-NEXT:   [[COPY18:%[0-9]+]]:vgpr(i32) = COPY [[UV13]](i32)
   ; GFX7-NEXT:   [[INTRINSIC_CONVERGENT13:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY18]](i32)
   ; GFX7-NEXT:   $sgpr13 = COPY [[INTRINSIC_CONVERGENT13]](i32)
   ; GFX7-NEXT:   [[COPY19:%[0-9]+]]:vgpr(i32) = COPY [[UV14]](i32)
   ; GFX7-NEXT:   [[INTRINSIC_CONVERGENT14:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY19]](i32)
   ; GFX7-NEXT:   $sgpr14 = COPY [[INTRINSIC_CONVERGENT14]](i32)
   ; GFX7-NEXT:   [[COPY20:%[0-9]+]]:vgpr(i32) = COPY [[UV15]](i32)
   ; GFX7-NEXT:   [[INTRINSIC_CONVERGENT15:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY20]](i32)
   ; GFX7-NEXT:   $sgpr15 = COPY [[INTRINSIC_CONVERGENT15]](i32)
   ; GFX7-NEXT:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15
   ;
   ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v16i32
   ; GFX1200_1250: bb.1 (%ir-block.0):
   ; GFX1200_1250-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
   ; GFX1200_1250-NEXT: {{  $}}
   ; GFX1200_1250-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX1200_1250-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX1200_1250-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX1200_1250-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX1200_1250-NEXT:   [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr6
   ; GFX1200_1250-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX1200_1250-NEXT:   [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<16 x i32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[COPY4]](i32), 0 :: (dereferenceable invariant load (<16 x i32>) from %ir.rsrc, align 1, addrspace 8)
   ; GFX1200_1250-NEXT:   [[UV:%[0-9]+]]:sgpr(i32), [[UV1:%[0-9]+]]:sgpr(i32), [[UV2:%[0-9]+]]:sgpr(i32), [[UV3:%[0-9]+]]:sgpr(i32), [[UV4:%[0-9]+]]:sgpr(i32), [[UV5:%[0-9]+]]:sgpr(i32), [[UV6:%[0-9]+]]:sgpr(i32), [[UV7:%[0-9]+]]:sgpr(i32), [[UV8:%[0-9]+]]:sgpr(i32), [[UV9:%[0-9]+]]:sgpr(i32), [[UV10:%[0-9]+]]:sgpr(i32), [[UV11:%[0-9]+]]:sgpr(i32), [[UV12:%[0-9]+]]:sgpr(i32), [[UV13:%[0-9]+]]:sgpr(i32), [[UV14:%[0-9]+]]:sgpr(i32), [[UV15:%[0-9]+]]:sgpr(i32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<16 x i32>)
   ; GFX1200_1250-NEXT:   [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[UV]](i32)
   ; GFX1200_1250-NEXT:   [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](i32)
   ; GFX1200_1250-NEXT:   $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](i32)
   ; GFX1200_1250-NEXT:   [[COPY6:%[0-9]+]]:vgpr(i32) = COPY [[UV1]](i32)
   ; GFX1200_1250-NEXT:   [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](i32)
   ; GFX1200_1250-NEXT:   $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](i32)
   ; GFX1200_1250-NEXT:   [[COPY7:%[0-9]+]]:vgpr(i32) = COPY [[UV2]](i32)
   ; GFX1200_1250-NEXT:   [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY7]](i32)
   ; GFX1200_1250-NEXT:   $sgpr2 = COPY [[INTRINSIC_CONVERGENT2]](i32)
   ; GFX1200_1250-NEXT:   [[COPY8:%[0-9]+]]:vgpr(i32) = COPY [[UV3]](i32)
   ; GFX1200_1250-NEXT:   [[INTRINSIC_CONVERGENT3:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY8]](i32)
   ; GFX1200_1250-NEXT:   $sgpr3 = COPY [[INTRINSIC_CONVERGENT3]](i32)
   ; GFX1200_1250-NEXT:   [[COPY9:%[0-9]+]]:vgpr(i32) = COPY [[UV4]](i32)
   ; GFX1200_1250-NEXT:   [[INTRINSIC_CONVERGENT4:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY9]](i32)
   ; GFX1200_1250-NEXT:   $sgpr4 = COPY [[INTRINSIC_CONVERGENT4]](i32)
   ; GFX1200_1250-NEXT:   [[COPY10:%[0-9]+]]:vgpr(i32) = COPY [[UV5]](i32)
   ; GFX1200_1250-NEXT:   [[INTRINSIC_CONVERGENT5:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY10]](i32)
   ; GFX1200_1250-NEXT:   $sgpr5 = COPY [[INTRINSIC_CONVERGENT5]](i32)
   ; GFX1200_1250-NEXT:   [[COPY11:%[0-9]+]]:vgpr(i32) = COPY [[UV6]](i32)
   ; GFX1200_1250-NEXT:   [[INTRINSIC_CONVERGENT6:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY11]](i32)
   ; GFX1200_1250-NEXT:   $sgpr6 = COPY [[INTRINSIC_CONVERGENT6]](i32)
   ; GFX1200_1250-NEXT:   [[COPY12:%[0-9]+]]:vgpr(i32) = COPY [[UV7]](i32)
   ; GFX1200_1250-NEXT:   [[INTRINSIC_CONVERGENT7:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY12]](i32)
   ; GFX1200_1250-NEXT:   $sgpr7 = COPY [[INTRINSIC_CONVERGENT7]](i32)
   ; GFX1200_1250-NEXT:   [[COPY13:%[0-9]+]]:vgpr(i32) = COPY [[UV8]](i32)
   ; GFX1200_1250-NEXT:   [[INTRINSIC_CONVERGENT8:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY13]](i32)
   ; GFX1200_1250-NEXT:   $sgpr8 = COPY [[INTRINSIC_CONVERGENT8]](i32)
   ; GFX1200_1250-NEXT:   [[COPY14:%[0-9]+]]:vgpr(i32) = COPY [[UV9]](i32)
   ; GFX1200_1250-NEXT:   [[INTRINSIC_CONVERGENT9:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY14]](i32)
   ; GFX1200_1250-NEXT:   $sgpr9 = COPY [[INTRINSIC_CONVERGENT9]](i32)
   ; GFX1200_1250-NEXT:   [[COPY15:%[0-9]+]]:vgpr(i32) = COPY [[UV10]](i32)
   ; GFX1200_1250-NEXT:   [[INTRINSIC_CONVERGENT10:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY15]](i32)
   ; GFX1200_1250-NEXT:   $sgpr10 = COPY [[INTRINSIC_CONVERGENT10]](i32)
   ; GFX1200_1250-NEXT:   [[COPY16:%[0-9]+]]:vgpr(i32) = COPY [[UV11]](i32)
   ; GFX1200_1250-NEXT:   [[INTRINSIC_CONVERGENT11:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY16]](i32)
   ; GFX1200_1250-NEXT:   $sgpr11 = COPY [[INTRINSIC_CONVERGENT11]](i32)
   ; GFX1200_1250-NEXT:   [[COPY17:%[0-9]+]]:vgpr(i32) = COPY [[UV12]](i32)
   ; GFX1200_1250-NEXT:   [[INTRINSIC_CONVERGENT12:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY17]](i32)
   ; GFX1200_1250-NEXT:   $sgpr12 = COPY [[INTRINSIC_CONVERGENT12]](i32)
   ; GFX1200_1250-NEXT:   [[COPY18:%[0-9]+]]:vgpr(i32) = COPY [[UV13]](i32)
   ; GFX1200_1250-NEXT:   [[INTRINSIC_CONVERGENT13:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY18]](i32)
   ; GFX1200_1250-NEXT:   $sgpr13 = COPY [[INTRINSIC_CONVERGENT13]](i32)
   ; GFX1200_1250-NEXT:   [[COPY19:%[0-9]+]]:vgpr(i32) = COPY [[UV14]](i32)
   ; GFX1200_1250-NEXT:   [[INTRINSIC_CONVERGENT14:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY19]](i32)
   ; GFX1200_1250-NEXT:   $sgpr14 = COPY [[INTRINSIC_CONVERGENT14]](i32)
   ; GFX1200_1250-NEXT:   [[COPY20:%[0-9]+]]:vgpr(i32) = COPY [[UV15]](i32)
   ; GFX1200_1250-NEXT:   [[INTRINSIC_CONVERGENT15:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY20]](i32)
   ; GFX1200_1250-NEXT:   $sgpr15 = COPY [[INTRINSIC_CONVERGENT15]](i32)
   ; GFX1200_1250-NEXT:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15
   %val = call <16 x i32> @llvm.amdgcn.ptr.s.buffer.load.v16i32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0
   ret <16 x i32> %val
 }

 ; Check cases that need to be converted to MUBUF due to the offset being a VGPR.
 define amdgpu_ps float @ptr_s_buffer_load_f32_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %soffset) {
   ; GFX7-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset
   ; GFX7: bb.1 (%ir-block.0):
   ; GFX7-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
   ; GFX7-NEXT: {{  $}}
   ; GFX7-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX7-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX7-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX7-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX7-NEXT:   [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
   ; GFX7-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX7-NEXT:   [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0
   ; GFX7-NEXT:   [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
   ; GFX7-NEXT:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(f32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C1]](i32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8)
   ; GFX7-NEXT:   [[COPY5:%[0-9]+]]:vgpr(f32) = COPY [[AMDGPU_BUFFER_LOAD]](f32)
   ; GFX7-NEXT:   $vgpr0 = COPY [[COPY5]](f32)
   ; GFX7-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0
   ;
   ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset
   ; GFX1200_1250: bb.1 (%ir-block.0):
   ; GFX1200_1250-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
   ; GFX1200_1250-NEXT: {{  $}}
   ; GFX1200_1250-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX1200_1250-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX1200_1250-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX1200_1250-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX1200_1250-NEXT:   [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
   ; GFX1200_1250-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX1200_1250-NEXT:   [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0
   ; GFX1200_1250-NEXT:   [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
   ; GFX1200_1250-NEXT:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(f32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C1]](i32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8)
   ; GFX1200_1250-NEXT:   [[COPY5:%[0-9]+]]:vgpr(f32) = COPY [[AMDGPU_BUFFER_LOAD]](f32)
   ; GFX1200_1250-NEXT:   $vgpr0 = COPY [[COPY5]](f32)
   ; GFX1200_1250-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0
   %val = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0
   ret float %val
 }

 define amdgpu_ps <2 x float> @ptr_s_buffer_load_v2f32_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %soffset) {
   ; GFX7-LABEL: name: ptr_s_buffer_load_v2f32_vgpr_offset
   ; GFX7: bb.1 (%ir-block.0):
   ; GFX7-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
   ; GFX7-NEXT: {{  $}}
   ; GFX7-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX7-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX7-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX7-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX7-NEXT:   [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
   ; GFX7-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX7-NEXT:   [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0
   ; GFX7-NEXT:   [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
   ; GFX7-NEXT:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C1]](i32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s64) from %ir.rsrc, align 1, addrspace 8)
   ; GFX7-NEXT:   [[COPY5:%[0-9]+]]:vgpr(<2 x f32>) = COPY [[AMDGPU_BUFFER_LOAD]](<2 x f32>)
   ; GFX7-NEXT:   [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[COPY5]](<2 x f32>)
   ; GFX7-NEXT:   $vgpr0 = COPY [[UV]](f32)
   ; GFX7-NEXT:   $vgpr1 = COPY [[UV1]](f32)
   ; GFX7-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
   ;
   ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v2f32_vgpr_offset
   ; GFX1200_1250: bb.1 (%ir-block.0):
   ; GFX1200_1250-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
   ; GFX1200_1250-NEXT: {{  $}}
   ; GFX1200_1250-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX1200_1250-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX1200_1250-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX1200_1250-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX1200_1250-NEXT:   [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
   ; GFX1200_1250-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX1200_1250-NEXT:   [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0
   ; GFX1200_1250-NEXT:   [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
   ; GFX1200_1250-NEXT:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C1]](i32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s64) from %ir.rsrc, align 1, addrspace 8)
   ; GFX1200_1250-NEXT:   [[COPY5:%[0-9]+]]:vgpr(<2 x f32>) = COPY [[AMDGPU_BUFFER_LOAD]](<2 x f32>)
   ; GFX1200_1250-NEXT:   [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[COPY5]](<2 x f32>)
   ; GFX1200_1250-NEXT:   $vgpr0 = COPY [[UV]](f32)
   ; GFX1200_1250-NEXT:   $vgpr1 = COPY [[UV1]](f32)
   ; GFX1200_1250-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
   %val = call <2 x float> @llvm.amdgcn.ptr.s.buffer.load.v2f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0
   ret <2 x float> %val
 }

 define amdgpu_ps <3 x float> @ptr_s_buffer_load_v3f32_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %soffset) {
   ; GFX7-LABEL: name: ptr_s_buffer_load_v3f32_vgpr_offset
   ; GFX7: bb.1 (%ir-block.0):
   ; GFX7-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
   ; GFX7-NEXT: {{  $}}
   ; GFX7-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX7-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX7-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX7-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX7-NEXT:   [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
   ; GFX7-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX7-NEXT:   [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0
   ; GFX7-NEXT:   [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
   ; GFX7-NEXT:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C1]](i32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s96) from %ir.rsrc, align 1, addrspace 8)
   ; GFX7-NEXT:   [[COPY5:%[0-9]+]]:vgpr(<4 x f32>) = COPY [[AMDGPU_BUFFER_LOAD]](<4 x f32>)
   ; GFX7-NEXT:   [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[COPY5]](<4 x f32>)
   ; GFX7-NEXT:   $vgpr0 = COPY [[UV]](f32)
   ; GFX7-NEXT:   $vgpr1 = COPY [[UV1]](f32)
   ; GFX7-NEXT:   $vgpr2 = COPY [[UV2]](f32)
   ; GFX7-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
   ;
   ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v3f32_vgpr_offset
   ; GFX1200_1250: bb.1 (%ir-block.0):
   ; GFX1200_1250-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
   ; GFX1200_1250-NEXT: {{  $}}
   ; GFX1200_1250-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX1200_1250-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX1200_1250-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX1200_1250-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX1200_1250-NEXT:   [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
   ; GFX1200_1250-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX1200_1250-NEXT:   [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0
   ; GFX1200_1250-NEXT:   [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
   ; GFX1200_1250-NEXT:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<3 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C1]](i32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s96) from %ir.rsrc, align 1, addrspace 8)
   ; GFX1200_1250-NEXT:   [[COPY5:%[0-9]+]]:vgpr(<3 x f32>) = COPY [[AMDGPU_BUFFER_LOAD]](<3 x f32>)
   ; GFX1200_1250-NEXT:   [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[COPY5]](<3 x f32>)
   ; GFX1200_1250-NEXT:   $vgpr0 = COPY [[UV]](f32)
   ; GFX1200_1250-NEXT:   $vgpr1 = COPY [[UV1]](f32)
   ; GFX1200_1250-NEXT:   $vgpr2 = COPY [[UV2]](f32)
   ; GFX1200_1250-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
   %val = call <3 x float> @llvm.amdgcn.ptr.s.buffer.load.v3f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0
   ret <3 x float> %val
 }

 define amdgpu_ps <4 x float> @ptr_s_buffer_load_v4f32_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %soffset) {
   ; GFX7-LABEL: name: ptr_s_buffer_load_v4f32_vgpr_offset
   ; GFX7: bb.1 (%ir-block.0):
   ; GFX7-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
   ; GFX7-NEXT: {{  $}}
   ; GFX7-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX7-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX7-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX7-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX7-NEXT:   [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
   ; GFX7-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX7-NEXT:   [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0
   ; GFX7-NEXT:   [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
   ; GFX7-NEXT:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C1]](i32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8)
   ; GFX7-NEXT:   [[COPY5:%[0-9]+]]:vgpr(<4 x f32>) = COPY [[AMDGPU_BUFFER_LOAD]](<4 x f32>)
   ; GFX7-NEXT:   [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[COPY5]](<4 x f32>)
   ; GFX7-NEXT:   $vgpr0 = COPY [[UV]](f32)
   ; GFX7-NEXT:   $vgpr1 = COPY [[UV1]](f32)
   ; GFX7-NEXT:   $vgpr2 = COPY [[UV2]](f32)
   ; GFX7-NEXT:   $vgpr3 = COPY [[UV3]](f32)
   ; GFX7-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
   ;
   ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v4f32_vgpr_offset
   ; GFX1200_1250: bb.1 (%ir-block.0):
   ; GFX1200_1250-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
   ; GFX1200_1250-NEXT: {{  $}}
   ; GFX1200_1250-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX1200_1250-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX1200_1250-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX1200_1250-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX1200_1250-NEXT:   [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
   ; GFX1200_1250-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX1200_1250-NEXT:   [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0
   ; GFX1200_1250-NEXT:   [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
   ; GFX1200_1250-NEXT:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C1]](i32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8)
   ; GFX1200_1250-NEXT:   [[COPY5:%[0-9]+]]:vgpr(<4 x f32>) = COPY [[AMDGPU_BUFFER_LOAD]](<4 x f32>)
   ; GFX1200_1250-NEXT:   [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[COPY5]](<4 x f32>)
   ; GFX1200_1250-NEXT:   $vgpr0 = COPY [[UV]](f32)
   ; GFX1200_1250-NEXT:   $vgpr1 = COPY [[UV1]](f32)
   ; GFX1200_1250-NEXT:   $vgpr2 = COPY [[UV2]](f32)
   ; GFX1200_1250-NEXT:   $vgpr3 = COPY [[UV3]](f32)
   ; GFX1200_1250-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
   %val = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0
   ret <4 x float> %val
 }

 define amdgpu_ps <8 x float> @ptr_s_buffer_load_v8f32_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %soffset) {
   ; GFX7-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset
   ; GFX7: bb.1 (%ir-block.0):
   ; GFX7-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
   ; GFX7-NEXT: {{  $}}
   ; GFX7-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX7-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX7-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX7-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX7-NEXT:   [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
   ; GFX7-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX7-NEXT:   [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0
   ; GFX7-NEXT:   [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
   ; GFX7-NEXT:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C1]](i32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8)
   ; GFX7-NEXT:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C1]](i32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8)
   ; GFX7-NEXT:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x f32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x f32>), [[AMDGPU_BUFFER_LOAD1]](<4 x f32>)
   ; GFX7-NEXT:   [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32), [[UV4:%[0-9]+]]:vgpr(f32), [[UV5:%[0-9]+]]:vgpr(f32), [[UV6:%[0-9]+]]:vgpr(f32), [[UV7:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x f32>)
   ; GFX7-NEXT:   $vgpr0 = COPY [[UV]](f32)
   ; GFX7-NEXT:   $vgpr1 = COPY [[UV1]](f32)
   ; GFX7-NEXT:   $vgpr2 = COPY [[UV2]](f32)
   ; GFX7-NEXT:   $vgpr3 = COPY [[UV3]](f32)
   ; GFX7-NEXT:   $vgpr4 = COPY [[UV4]](f32)
   ; GFX7-NEXT:   $vgpr5 = COPY [[UV5]](f32)
   ; GFX7-NEXT:   $vgpr6 = COPY [[UV6]](f32)
   ; GFX7-NEXT:   $vgpr7 = COPY [[UV7]](f32)
   ; GFX7-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
   ;
   ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset
   ; GFX1200_1250: bb.1 (%ir-block.0):
   ; GFX1200_1250-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
   ; GFX1200_1250-NEXT: {{  $}}
   ; GFX1200_1250-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX1200_1250-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX1200_1250-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX1200_1250-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX1200_1250-NEXT:   [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
   ; GFX1200_1250-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX1200_1250-NEXT:   [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0
   ; GFX1200_1250-NEXT:   [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
   ; GFX1200_1250-NEXT:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C1]](i32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8)
   ; GFX1200_1250-NEXT:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C1]](i32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8)
   ; GFX1200_1250-NEXT:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x f32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x f32>), [[AMDGPU_BUFFER_LOAD1]](<4 x f32>)
   ; GFX1200_1250-NEXT:   [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32), [[UV4:%[0-9]+]]:vgpr(f32), [[UV5:%[0-9]+]]:vgpr(f32), [[UV6:%[0-9]+]]:vgpr(f32), [[UV7:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x f32>)
   ; GFX1200_1250-NEXT:   $vgpr0 = COPY [[UV]](f32)
   ; GFX1200_1250-NEXT:   $vgpr1 = COPY [[UV1]](f32)
   ; GFX1200_1250-NEXT:   $vgpr2 = COPY [[UV2]](f32)
   ; GFX1200_1250-NEXT:   $vgpr3 = COPY [[UV3]](f32)
   ; GFX1200_1250-NEXT:   $vgpr4 = COPY [[UV4]](f32)
   ; GFX1200_1250-NEXT:   $vgpr5 = COPY [[UV5]](f32)
   ; GFX1200_1250-NEXT:   $vgpr6 = COPY [[UV6]](f32)
   ; GFX1200_1250-NEXT:   $vgpr7 = COPY [[UV7]](f32)
   ; GFX1200_1250-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
   %val = call <8 x float> @llvm.amdgcn.ptr.s.buffer.load.v8f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0
   ret <8 x float> %val
 }

 define amdgpu_ps <16 x float> @ptr_s_buffer_load_v16f32_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %soffset) {
   ; GFX7-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset
   ; GFX7: bb.1 (%ir-block.0):
   ; GFX7-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
   ; GFX7-NEXT: {{  $}}
   ; GFX7-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX7-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX7-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX7-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX7-NEXT:   [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
   ; GFX7-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX7-NEXT:   [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0
   ; GFX7-NEXT:   [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
   ; GFX7-NEXT:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C1]](i32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8)
   ; GFX7-NEXT:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C1]](i32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8)
   ; GFX7-NEXT:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C1]](i32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8)
   ; GFX7-NEXT:   [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C1]](i32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8)
   ; GFX7-NEXT:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x f32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x f32>), [[AMDGPU_BUFFER_LOAD1]](<4 x f32>), [[AMDGPU_BUFFER_LOAD2]](<4 x f32>), [[AMDGPU_BUFFER_LOAD3]](<4 x f32>)
   ; GFX7-NEXT:   [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32), [[UV4:%[0-9]+]]:vgpr(f32), [[UV5:%[0-9]+]]:vgpr(f32), [[UV6:%[0-9]+]]:vgpr(f32), [[UV7:%[0-9]+]]:vgpr(f32), [[UV8:%[0-9]+]]:vgpr(f32), [[UV9:%[0-9]+]]:vgpr(f32), [[UV10:%[0-9]+]]:vgpr(f32), [[UV11:%[0-9]+]]:vgpr(f32), [[UV12:%[0-9]+]]:vgpr(f32), [[UV13:%[0-9]+]]:vgpr(f32), [[UV14:%[0-9]+]]:vgpr(f32), [[UV15:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x f32>)
   ; GFX7-NEXT:   $vgpr0 = COPY [[UV]](f32)
   ; GFX7-NEXT:   $vgpr1 = COPY [[UV1]](f32)
   ; GFX7-NEXT:   $vgpr2 = COPY [[UV2]](f32)
   ; GFX7-NEXT:   $vgpr3 = COPY [[UV3]](f32)
   ; GFX7-NEXT:   $vgpr4 = COPY [[UV4]](f32)
   ; GFX7-NEXT:   $vgpr5 = COPY [[UV5]](f32)
   ; GFX7-NEXT:   $vgpr6 = COPY [[UV6]](f32)
   ; GFX7-NEXT:   $vgpr7 = COPY [[UV7]](f32)
   ; GFX7-NEXT:   $vgpr8 = COPY [[UV8]](f32)
   ; GFX7-NEXT:   $vgpr9 = COPY [[UV9]](f32)
   ; GFX7-NEXT:   $vgpr10 = COPY [[UV10]](f32)
   ; GFX7-NEXT:   $vgpr11 = COPY [[UV11]](f32)
   ; GFX7-NEXT:   $vgpr12 = COPY [[UV12]](f32)
   ; GFX7-NEXT:   $vgpr13 = COPY [[UV13]](f32)
   ; GFX7-NEXT:   $vgpr14 = COPY [[UV14]](f32)
   ; GFX7-NEXT:   $vgpr15 = COPY [[UV15]](f32)
   ; GFX7-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15
   ;
   ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset
   ; GFX1200_1250: bb.1 (%ir-block.0):
   ; GFX1200_1250-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
   ; GFX1200_1250-NEXT: {{  $}}
   ; GFX1200_1250-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX1200_1250-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX1200_1250-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX1200_1250-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX1200_1250-NEXT:   [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
   ; GFX1200_1250-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX1200_1250-NEXT:   [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0
   ; GFX1200_1250-NEXT:   [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
   ; GFX1200_1250-NEXT:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C1]](i32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8)
   ; GFX1200_1250-NEXT:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C1]](i32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8)
   ; GFX1200_1250-NEXT:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C1]](i32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8)
   ; GFX1200_1250-NEXT:   [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C1]](i32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8)
   ; GFX1200_1250-NEXT:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x f32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x f32>), [[AMDGPU_BUFFER_LOAD1]](<4 x f32>), [[AMDGPU_BUFFER_LOAD2]](<4 x f32>), [[AMDGPU_BUFFER_LOAD3]](<4 x f32>)
   ; GFX1200_1250-NEXT:   [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32), [[UV4:%[0-9]+]]:vgpr(f32), [[UV5:%[0-9]+]]:vgpr(f32), [[UV6:%[0-9]+]]:vgpr(f32), [[UV7:%[0-9]+]]:vgpr(f32), [[UV8:%[0-9]+]]:vgpr(f32), [[UV9:%[0-9]+]]:vgpr(f32), [[UV10:%[0-9]+]]:vgpr(f32), [[UV11:%[0-9]+]]:vgpr(f32), [[UV12:%[0-9]+]]:vgpr(f32), [[UV13:%[0-9]+]]:vgpr(f32), [[UV14:%[0-9]+]]:vgpr(f32), [[UV15:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x f32>)
   ; GFX1200_1250-NEXT:   $vgpr0 = COPY [[UV]](f32)
   ; GFX1200_1250-NEXT:   $vgpr1 = COPY [[UV1]](f32)
   ; GFX1200_1250-NEXT:   $vgpr2 = COPY [[UV2]](f32)
   ; GFX1200_1250-NEXT:   $vgpr3 = COPY [[UV3]](f32)
   ; GFX1200_1250-NEXT:   $vgpr4 = COPY [[UV4]](f32)
   ; GFX1200_1250-NEXT:   $vgpr5 = COPY [[UV5]](f32)
   ; GFX1200_1250-NEXT:   $vgpr6 = COPY [[UV6]](f32)
   ; GFX1200_1250-NEXT:   $vgpr7 = COPY [[UV7]](f32)
   ; GFX1200_1250-NEXT:   $vgpr8 = COPY [[UV8]](f32)
   ; GFX1200_1250-NEXT:   $vgpr9 = COPY [[UV9]](f32)
   ; GFX1200_1250-NEXT:   $vgpr10 = COPY [[UV10]](f32)
   ; GFX1200_1250-NEXT:   $vgpr11 = COPY [[UV11]](f32)
   ; GFX1200_1250-NEXT:   $vgpr12 = COPY [[UV12]](f32)
   ; GFX1200_1250-NEXT:   $vgpr13 = COPY [[UV13]](f32)
   ; GFX1200_1250-NEXT:   $vgpr14 = COPY [[UV14]](f32)
   ; GFX1200_1250-NEXT:   $vgpr15 = COPY [[UV15]](f32)
   ; GFX1200_1250-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15
   %val = call <16 x float> @llvm.amdgcn.ptr.s.buffer.load.v16f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0
   ret <16 x float> %val
 }

 define amdgpu_ps float @ptr_s_buffer_load_f32_vgpr_offset_add_4092(ptr addrspace(8) inreg %rsrc, i32 %soffset.base) {
   ; GFX7-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4092
   ; GFX7: bb.1 (%ir-block.0):
   ; GFX7-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
   ; GFX7-NEXT: {{  $}}
   ; GFX7-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX7-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX7-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX7-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX7-NEXT:   [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
   ; GFX7-NEXT:   [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4092
   ; GFX7-NEXT:   [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32)
   ; GFX7-NEXT:   [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]]
   ; GFX7-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX7-NEXT:   [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0
   ; GFX7-NEXT:   [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
   ; GFX7-NEXT:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(f32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[COPY4]], [[C1]], 4092, 0, 0 :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8)
   ; GFX7-NEXT:   [[COPY6:%[0-9]+]]:vgpr(f32) = COPY [[AMDGPU_BUFFER_LOAD]](f32)
   ; GFX7-NEXT:   $vgpr0 = COPY [[COPY6]](f32)
   ; GFX7-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0
   ;
   ; GFX1200-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4092
   ; GFX1200: bb.1 (%ir-block.0):
   ; GFX1200-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
   ; GFX1200-NEXT: {{  $}}
   ; GFX1200-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX1200-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX1200-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX1200-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX1200-NEXT:   [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
   ; GFX1200-NEXT:   [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4092
   ; GFX1200-NEXT:   [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32)
   ; GFX1200-NEXT:   [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]]
   ; GFX1200-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX1200-NEXT:   [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0
   ; GFX1200-NEXT:   [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
   ; GFX1200-NEXT:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(f32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[COPY4]], [[C1]], 4092, 0, 0 :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8)
   ; GFX1200-NEXT:   [[COPY6:%[0-9]+]]:vgpr(f32) = COPY [[AMDGPU_BUFFER_LOAD]](f32)
   ; GFX1200-NEXT:   $vgpr0 = COPY [[COPY6]](f32)
   ; GFX1200-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0
   ;
   ; GFX1250-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4092
   ; GFX1250: bb.1 (%ir-block.0):
   ; GFX1250-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
   ; GFX1250-NEXT: {{  $}}
   ; GFX1250-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX1250-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX1250-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX1250-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX1250-NEXT:   [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
   ; GFX1250-NEXT:   [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4092
   ; GFX1250-NEXT:   [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32)
   ; GFX1250-NEXT:   [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]]
   ; GFX1250-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX1250-NEXT:   [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0
   ; GFX1250-NEXT:   [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
   ; GFX1250-NEXT:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(f32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[ADD]], [[C1]], 0, 0, 0 :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8)
   ; GFX1250-NEXT:   [[COPY6:%[0-9]+]]:vgpr(f32) = COPY [[AMDGPU_BUFFER_LOAD]](f32)
   ; GFX1250-NEXT:   $vgpr0 = COPY [[COPY6]](f32)
   ; GFX1250-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0
   %soffset = add i32 %soffset.base, 4092
   %val = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0
   ret float %val
 }

 define amdgpu_ps float @ptr_s_buffer_load_f32_vgpr_offset_add_4095(ptr addrspace(8) inreg %rsrc, i32 %soffset.base) {
   ; GFX7-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4095
   ; GFX7: bb.1 (%ir-block.0):
   ; GFX7-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
   ; GFX7-NEXT: {{  $}}
   ; GFX7-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX7-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX7-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX7-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX7-NEXT:   [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
   ; GFX7-NEXT:   [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4095
   ; GFX7-NEXT:   [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32)
   ; GFX7-NEXT:   [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]]
   ; GFX7-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX7-NEXT:   [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0
   ; GFX7-NEXT:   [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
   ; GFX7-NEXT:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(f32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[COPY4]], [[C1]], 4095, 0, 0 :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8)
   ; GFX7-NEXT:   [[COPY6:%[0-9]+]]:vgpr(f32) = COPY [[AMDGPU_BUFFER_LOAD]](f32)
   ; GFX7-NEXT:   $vgpr0 = COPY [[COPY6]](f32)
   ; GFX7-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0
   ;
   ; GFX1200-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4095
   ; GFX1200: bb.1 (%ir-block.0):
   ; GFX1200-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
   ; GFX1200-NEXT: {{  $}}
   ; GFX1200-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX1200-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX1200-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX1200-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX1200-NEXT:   [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
   ; GFX1200-NEXT:   [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4095
   ; GFX1200-NEXT:   [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32)
   ; GFX1200-NEXT:   [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]]
   ; GFX1200-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX1200-NEXT:   [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0
   ; GFX1200-NEXT:   [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
   ; GFX1200-NEXT:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(f32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[COPY4]], [[C1]], 4095, 0, 0 :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8)
   ; GFX1200-NEXT:   [[COPY6:%[0-9]+]]:vgpr(f32) = COPY [[AMDGPU_BUFFER_LOAD]](f32)
   ; GFX1200-NEXT:   $vgpr0 = COPY [[COPY6]](f32)
   ; GFX1200-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0
   ;
   ; GFX1250-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4095
   ; GFX1250: bb.1 (%ir-block.0):
   ; GFX1250-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
   ; GFX1250-NEXT: {{  $}}
   ; GFX1250-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX1250-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX1250-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX1250-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX1250-NEXT:   [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
   ; GFX1250-NEXT:   [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4095
   ; GFX1250-NEXT:   [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32)
   ; GFX1250-NEXT:   [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]]
   ; GFX1250-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX1250-NEXT:   [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0
   ; GFX1250-NEXT:   [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
   ; GFX1250-NEXT:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(f32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[ADD]], [[C1]], 0, 0, 0 :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8)
   ; GFX1250-NEXT:   [[COPY6:%[0-9]+]]:vgpr(f32) = COPY [[AMDGPU_BUFFER_LOAD]](f32)
   ; GFX1250-NEXT:   $vgpr0 = COPY [[COPY6]](f32)
   ; GFX1250-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0
   %soffset = add i32 %soffset.base, 4095
   %val = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0
   ret float %val
 }

 define amdgpu_ps float @ptr_s_buffer_load_f32_vgpr_offset_add_4096(ptr addrspace(8) inreg %rsrc, i32 %soffset.base) {
   ; GFX7-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4096
   ; GFX7: bb.1 (%ir-block.0):
   ; GFX7-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
   ; GFX7-NEXT: {{  $}}
   ; GFX7-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX7-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX7-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX7-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX7-NEXT:   [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
   ; GFX7-NEXT:   [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4096
   ; GFX7-NEXT:   [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32)
   ; GFX7-NEXT:   [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]]
   ; GFX7-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX7-NEXT:   [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
   ; GFX7-NEXT:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(f32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C1]](i32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8)
   ; GFX7-NEXT:   [[COPY6:%[0-9]+]]:vgpr(f32) = COPY [[AMDGPU_BUFFER_LOAD]](f32)
   ; GFX7-NEXT:   $vgpr0 = COPY [[COPY6]](f32)
   ; GFX7-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0
   ;
   ; GFX1200-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4096
   ; GFX1200: bb.1 (%ir-block.0):
   ; GFX1200-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
   ; GFX1200-NEXT: {{  $}}
   ; GFX1200-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX1200-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX1200-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX1200-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX1200-NEXT:   [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
   ; GFX1200-NEXT:   [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4096
   ; GFX1200-NEXT:   [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32)
   ; GFX1200-NEXT:   [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]]
   ; GFX1200-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX1200-NEXT:   [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0
   ; GFX1200-NEXT:   [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
   ; GFX1200-NEXT:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(f32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[COPY4]], [[C1]], 4096, 0, 0 :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8)
   ; GFX1200-NEXT:   [[COPY6:%[0-9]+]]:vgpr(f32) = COPY [[AMDGPU_BUFFER_LOAD]](f32)
   ; GFX1200-NEXT:   $vgpr0 = COPY [[COPY6]](f32)
   ; GFX1200-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0
   ;
   ; GFX1250-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4096
   ; GFX1250: bb.1 (%ir-block.0):
   ; GFX1250-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
   ; GFX1250-NEXT: {{  $}}
   ; GFX1250-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX1250-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX1250-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX1250-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX1250-NEXT:   [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
   ; GFX1250-NEXT:   [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4096
   ; GFX1250-NEXT:   [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32)
   ; GFX1250-NEXT:   [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]]
   ; GFX1250-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX1250-NEXT:   [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0
   ; GFX1250-NEXT:   [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
   ; GFX1250-NEXT:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(f32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[ADD]], [[C1]], 0, 0, 0 :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8)
   ; GFX1250-NEXT:   [[COPY6:%[0-9]+]]:vgpr(f32) = COPY [[AMDGPU_BUFFER_LOAD]](f32)
   ; GFX1250-NEXT:   $vgpr0 = COPY [[COPY6]](f32)
   ; GFX1250-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0
   %soffset = add i32 %soffset.base, 4096
   %val = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0
   ret float %val
 }

 ; Make sure the base offset is added to each split load.
 define amdgpu_ps <8 x float> @ptr_s_buffer_load_v8f32_vgpr_offset_add_4064(ptr addrspace(8) inreg %rsrc, i32 %soffset.base) {
   ; GFX7-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4064
   ; GFX7: bb.1 (%ir-block.0):
   ; GFX7-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
   ; GFX7-NEXT: {{  $}}
   ; GFX7-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX7-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX7-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX7-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX7-NEXT:   [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
   ; GFX7-NEXT:   [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4064
   ; GFX7-NEXT:   [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32)
   ; GFX7-NEXT:   [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]]
   ; GFX7-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX7-NEXT:   [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0
   ; GFX7-NEXT:   [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
   ; GFX7-NEXT:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[COPY4]], [[C1]], 4064, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8)
   ; GFX7-NEXT:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[COPY4]], [[C1]], 4080, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8)
   ; GFX7-NEXT:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x f32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x f32>), [[AMDGPU_BUFFER_LOAD1]](<4 x f32>)
   ; GFX7-NEXT:   [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32), [[UV4:%[0-9]+]]:vgpr(f32), [[UV5:%[0-9]+]]:vgpr(f32), [[UV6:%[0-9]+]]:vgpr(f32), [[UV7:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x f32>)
   ; GFX7-NEXT:   $vgpr0 = COPY [[UV]](f32)
   ; GFX7-NEXT:   $vgpr1 = COPY [[UV1]](f32)
   ; GFX7-NEXT:   $vgpr2 = COPY [[UV2]](f32)
   ; GFX7-NEXT:   $vgpr3 = COPY [[UV3]](f32)
   ; GFX7-NEXT:   $vgpr4 = COPY [[UV4]](f32)
   ; GFX7-NEXT:   $vgpr5 = COPY [[UV5]](f32)
   ; GFX7-NEXT:   $vgpr6 = COPY [[UV6]](f32)
   ; GFX7-NEXT:   $vgpr7 = COPY [[UV7]](f32)
   ; GFX7-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
   ;
   ; GFX1200-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4064
   ; GFX1200: bb.1 (%ir-block.0):
   ; GFX1200-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
   ; GFX1200-NEXT: {{  $}}
   ; GFX1200-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX1200-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX1200-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX1200-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX1200-NEXT:   [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
   ; GFX1200-NEXT:   [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4064
   ; GFX1200-NEXT:   [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32)
   ; GFX1200-NEXT:   [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]]
   ; GFX1200-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX1200-NEXT:   [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0
   ; GFX1200-NEXT:   [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
   ; GFX1200-NEXT:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[COPY4]], [[C1]], 4064, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8)
   ; GFX1200-NEXT:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[COPY4]], [[C1]], 4080, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8)
   ; GFX1200-NEXT:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x f32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x f32>), [[AMDGPU_BUFFER_LOAD1]](<4 x f32>)
   ; GFX1200-NEXT:   [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32), [[UV4:%[0-9]+]]:vgpr(f32), [[UV5:%[0-9]+]]:vgpr(f32), [[UV6:%[0-9]+]]:vgpr(f32), [[UV7:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x f32>)
   ; GFX1200-NEXT:   $vgpr0 = COPY [[UV]](f32)
   ; GFX1200-NEXT:   $vgpr1 = COPY [[UV1]](f32)
   ; GFX1200-NEXT:   $vgpr2 = COPY [[UV2]](f32)
   ; GFX1200-NEXT:   $vgpr3 = COPY [[UV3]](f32)
   ; GFX1200-NEXT:   $vgpr4 = COPY [[UV4]](f32)
   ; GFX1200-NEXT:   $vgpr5 = COPY [[UV5]](f32)
   ; GFX1200-NEXT:   $vgpr6 = COPY [[UV6]](f32)
   ; GFX1200-NEXT:   $vgpr7 = COPY [[UV7]](f32)
   ; GFX1200-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
   ;
   ; GFX1250-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4064
   ; GFX1250: bb.1 (%ir-block.0):
   ; GFX1250-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
   ; GFX1250-NEXT: {{  $}}
   ; GFX1250-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX1250-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX1250-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX1250-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX1250-NEXT:   [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
   ; GFX1250-NEXT:   [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4064
   ; GFX1250-NEXT:   [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32)
   ; GFX1250-NEXT:   [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]]
   ; GFX1250-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX1250-NEXT:   [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0
   ; GFX1250-NEXT:   [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
   ; GFX1250-NEXT:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[ADD]], [[C1]], 0, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8)
   ; GFX1250-NEXT:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[ADD]], [[C1]], 16, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8)
   ; GFX1250-NEXT:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x f32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x f32>), [[AMDGPU_BUFFER_LOAD1]](<4 x f32>)
   ; GFX1250-NEXT:   [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32), [[UV4:%[0-9]+]]:vgpr(f32), [[UV5:%[0-9]+]]:vgpr(f32), [[UV6:%[0-9]+]]:vgpr(f32), [[UV7:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x f32>)
   ; GFX1250-NEXT:   $vgpr0 = COPY [[UV]](f32)
   ; GFX1250-NEXT:   $vgpr1 = COPY [[UV1]](f32)
   ; GFX1250-NEXT:   $vgpr2 = COPY [[UV2]](f32)
   ; GFX1250-NEXT:   $vgpr3 = COPY [[UV3]](f32)
   ; GFX1250-NEXT:   $vgpr4 = COPY [[UV4]](f32)
   ; GFX1250-NEXT:   $vgpr5 = COPY [[UV5]](f32)
   ; GFX1250-NEXT:   $vgpr6 = COPY [[UV6]](f32)
   ; GFX1250-NEXT:   $vgpr7 = COPY [[UV7]](f32)
   ; GFX1250-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
   %soffset = add i32 %soffset.base, 4064
   %val = call <8 x float> @llvm.amdgcn.ptr.s.buffer.load.v8f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0
   ret <8 x float> %val
 }

 ; Make sure the maximum offset isn't exeeded when splitting this
 define amdgpu_ps <8 x float> @ptr_s_buffer_load_v8f32_vgpr_offset_add_4068(ptr addrspace(8) inreg %rsrc, i32 %soffset.base) {
   ; GFX7-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4068
   ; GFX7: bb.1 (%ir-block.0):
   ; GFX7-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
   ; GFX7-NEXT: {{  $}}
   ; GFX7-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX7-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX7-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX7-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX7-NEXT:   [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
   ; GFX7-NEXT:   [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4068
   ; GFX7-NEXT:   [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32)
   ; GFX7-NEXT:   [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]]
   ; GFX7-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX7-NEXT:   [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0
   ; GFX7-NEXT:   [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
   ; GFX7-NEXT:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[COPY4]], [[C1]], 4068, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8)
   ; GFX7-NEXT:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[COPY4]], [[C1]], 4084, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8)
   ; GFX7-NEXT:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x f32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x f32>), [[AMDGPU_BUFFER_LOAD1]](<4 x f32>)
   ; GFX7-NEXT:   [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32), [[UV4:%[0-9]+]]:vgpr(f32), [[UV5:%[0-9]+]]:vgpr(f32), [[UV6:%[0-9]+]]:vgpr(f32), [[UV7:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x f32>)
   ; GFX7-NEXT:   $vgpr0 = COPY [[UV]](f32)
   ; GFX7-NEXT:   $vgpr1 = COPY [[UV1]](f32)
   ; GFX7-NEXT:   $vgpr2 = COPY [[UV2]](f32)
   ; GFX7-NEXT:   $vgpr3 = COPY [[UV3]](f32)
   ; GFX7-NEXT:   $vgpr4 = COPY [[UV4]](f32)
   ; GFX7-NEXT:   $vgpr5 = COPY [[UV5]](f32)
   ; GFX7-NEXT:   $vgpr6 = COPY [[UV6]](f32)
   ; GFX7-NEXT:   $vgpr7 = COPY [[UV7]](f32)
   ; GFX7-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
   ;
   ; GFX1200-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4068
   ; GFX1200: bb.1 (%ir-block.0):
   ; GFX1200-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
   ; GFX1200-NEXT: {{  $}}
   ; GFX1200-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX1200-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX1200-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX1200-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX1200-NEXT:   [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
   ; GFX1200-NEXT:   [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4068
   ; GFX1200-NEXT:   [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32)
   ; GFX1200-NEXT:   [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]]
   ; GFX1200-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX1200-NEXT:   [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0
   ; GFX1200-NEXT:   [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
   ; GFX1200-NEXT:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[COPY4]], [[C1]], 4068, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8)
   ; GFX1200-NEXT:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[COPY4]], [[C1]], 4084, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8)
   ; GFX1200-NEXT:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x f32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x f32>), [[AMDGPU_BUFFER_LOAD1]](<4 x f32>)
   ; GFX1200-NEXT:   [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32), [[UV4:%[0-9]+]]:vgpr(f32), [[UV5:%[0-9]+]]:vgpr(f32), [[UV6:%[0-9]+]]:vgpr(f32), [[UV7:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x f32>)
   ; GFX1200-NEXT:   $vgpr0 = COPY [[UV]](f32)
   ; GFX1200-NEXT:   $vgpr1 = COPY [[UV1]](f32)
   ; GFX1200-NEXT:   $vgpr2 = COPY [[UV2]](f32)
   ; GFX1200-NEXT:   $vgpr3 = COPY [[UV3]](f32)
   ; GFX1200-NEXT:   $vgpr4 = COPY [[UV4]](f32)
   ; GFX1200-NEXT:   $vgpr5 = COPY [[UV5]](f32)
   ; GFX1200-NEXT:   $vgpr6 = COPY [[UV6]](f32)
   ; GFX1200-NEXT:   $vgpr7 = COPY [[UV7]](f32)
   ; GFX1200-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
   ;
   ; GFX1250-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4068
   ; GFX1250: bb.1 (%ir-block.0):
   ; GFX1250-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
   ; GFX1250-NEXT: {{  $}}
   ; GFX1250-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX1250-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX1250-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX1250-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX1250-NEXT:   [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
   ; GFX1250-NEXT:   [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4068
   ; GFX1250-NEXT:   [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32)
   ; GFX1250-NEXT:   [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]]
   ; GFX1250-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX1250-NEXT:   [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0
   ; GFX1250-NEXT:   [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
   ; GFX1250-NEXT:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[ADD]], [[C1]], 0, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8)
   ; GFX1250-NEXT:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[ADD]], [[C1]], 16, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8)
   ; GFX1250-NEXT:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x f32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x f32>), [[AMDGPU_BUFFER_LOAD1]](<4 x f32>)
   ; GFX1250-NEXT:   [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32), [[UV4:%[0-9]+]]:vgpr(f32), [[UV5:%[0-9]+]]:vgpr(f32), [[UV6:%[0-9]+]]:vgpr(f32), [[UV7:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x f32>)
   ; GFX1250-NEXT:   $vgpr0 = COPY [[UV]](f32)
   ; GFX1250-NEXT:   $vgpr1 = COPY [[UV1]](f32)
   ; GFX1250-NEXT:   $vgpr2 = COPY [[UV2]](f32)
   ; GFX1250-NEXT:   $vgpr3 = COPY [[UV3]](f32)
   ; GFX1250-NEXT:   $vgpr4 = COPY [[UV4]](f32)
   ; GFX1250-NEXT:   $vgpr5 = COPY [[UV5]](f32)
   ; GFX1250-NEXT:   $vgpr6 = COPY [[UV6]](f32)
   ; GFX1250-NEXT:   $vgpr7 = COPY [[UV7]](f32)
   ; GFX1250-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
   %soffset = add i32 %soffset.base, 4068
   %val = call <8 x float> @llvm.amdgcn.ptr.s.buffer.load.v8f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0
   ret <8 x float> %val
 }

 define amdgpu_ps <16 x float> @ptr_s_buffer_load_v16f32_vgpr_offset_add_4032(ptr addrspace(8) inreg %rsrc, i32 %soffset.base) {
   ; GFX7-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4032
   ; GFX7: bb.1 (%ir-block.0):
   ; GFX7-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
   ; GFX7-NEXT: {{  $}}
   ; GFX7-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX7-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX7-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX7-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX7-NEXT:   [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
   ; GFX7-NEXT:   [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4032
   ; GFX7-NEXT:   [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32)
   ; GFX7-NEXT:   [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]]
   ; GFX7-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX7-NEXT:   [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0
   ; GFX7-NEXT:   [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
   ; GFX7-NEXT:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[COPY4]], [[C1]], 4032, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8)
   ; GFX7-NEXT:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[COPY4]], [[C1]], 4048, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8)
   ; GFX7-NEXT:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[COPY4]], [[C1]], 4064, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8)
   ; GFX7-NEXT:   [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[COPY4]], [[C1]], 4080, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8)
   ; GFX7-NEXT:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x f32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x f32>), [[AMDGPU_BUFFER_LOAD1]](<4 x f32>), [[AMDGPU_BUFFER_LOAD2]](<4 x f32>), [[AMDGPU_BUFFER_LOAD3]](<4 x f32>)
   ; GFX7-NEXT:   [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32), [[UV4:%[0-9]+]]:vgpr(f32), [[UV5:%[0-9]+]]:vgpr(f32), [[UV6:%[0-9]+]]:vgpr(f32), [[UV7:%[0-9]+]]:vgpr(f32), [[UV8:%[0-9]+]]:vgpr(f32), [[UV9:%[0-9]+]]:vgpr(f32), [[UV10:%[0-9]+]]:vgpr(f32), [[UV11:%[0-9]+]]:vgpr(f32), [[UV12:%[0-9]+]]:vgpr(f32), [[UV13:%[0-9]+]]:vgpr(f32), [[UV14:%[0-9]+]]:vgpr(f32), [[UV15:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x f32>)
   ; GFX7-NEXT:   $vgpr0 = COPY [[UV]](f32)
   ; GFX7-NEXT:   $vgpr1 = COPY [[UV1]](f32)
   ; GFX7-NEXT:   $vgpr2 = COPY [[UV2]](f32)
   ; GFX7-NEXT:   $vgpr3 = COPY [[UV3]](f32)
   ; GFX7-NEXT:   $vgpr4 = COPY [[UV4]](f32)
   ; GFX7-NEXT:   $vgpr5 = COPY [[UV5]](f32)
   ; GFX7-NEXT:   $vgpr6 = COPY [[UV6]](f32)
   ; GFX7-NEXT:   $vgpr7 = COPY [[UV7]](f32)
   ; GFX7-NEXT:   $vgpr8 = COPY [[UV8]](f32)
   ; GFX7-NEXT:   $vgpr9 = COPY [[UV9]](f32)
   ; GFX7-NEXT:   $vgpr10 = COPY [[UV10]](f32)
   ; GFX7-NEXT:   $vgpr11 = COPY [[UV11]](f32)
   ; GFX7-NEXT:   $vgpr12 = COPY [[UV12]](f32)
   ; GFX7-NEXT:   $vgpr13 = COPY [[UV13]](f32)
   ; GFX7-NEXT:   $vgpr14 = COPY [[UV14]](f32)
   ; GFX7-NEXT:   $vgpr15 = COPY [[UV15]](f32)
   ; GFX7-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15
   ;
   ; GFX1200-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4032
   ; GFX1200: bb.1 (%ir-block.0):
   ; GFX1200-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
   ; GFX1200-NEXT: {{  $}}
   ; GFX1200-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX1200-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX1200-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX1200-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX1200-NEXT:   [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
   ; GFX1200-NEXT:   [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4032
   ; GFX1200-NEXT:   [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32)
   ; GFX1200-NEXT:   [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]]
   ; GFX1200-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX1200-NEXT:   [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0
   ; GFX1200-NEXT:   [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
   ; GFX1200-NEXT:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[COPY4]], [[C1]], 4032, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8)
   ; GFX1200-NEXT:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[COPY4]], [[C1]], 4048, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8)
   ; GFX1200-NEXT:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[COPY4]], [[C1]], 4064, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8)
   ; GFX1200-NEXT:   [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[COPY4]], [[C1]], 4080, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8)
   ; GFX1200-NEXT:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x f32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x f32>), [[AMDGPU_BUFFER_LOAD1]](<4 x f32>), [[AMDGPU_BUFFER_LOAD2]](<4 x f32>), [[AMDGPU_BUFFER_LOAD3]](<4 x f32>)
   ; GFX1200-NEXT:   [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32), [[UV4:%[0-9]+]]:vgpr(f32), [[UV5:%[0-9]+]]:vgpr(f32), [[UV6:%[0-9]+]]:vgpr(f32), [[UV7:%[0-9]+]]:vgpr(f32), [[UV8:%[0-9]+]]:vgpr(f32), [[UV9:%[0-9]+]]:vgpr(f32), [[UV10:%[0-9]+]]:vgpr(f32), [[UV11:%[0-9]+]]:vgpr(f32), [[UV12:%[0-9]+]]:vgpr(f32), [[UV13:%[0-9]+]]:vgpr(f32), [[UV14:%[0-9]+]]:vgpr(f32), [[UV15:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x f32>)
   ; GFX1200-NEXT:   $vgpr0 = COPY [[UV]](f32)
   ; GFX1200-NEXT:   $vgpr1 = COPY [[UV1]](f32)
   ; GFX1200-NEXT:   $vgpr2 = COPY [[UV2]](f32)
   ; GFX1200-NEXT:   $vgpr3 = COPY [[UV3]](f32)
   ; GFX1200-NEXT:   $vgpr4 = COPY [[UV4]](f32)
   ; GFX1200-NEXT:   $vgpr5 = COPY [[UV5]](f32)
   ; GFX1200-NEXT:   $vgpr6 = COPY [[UV6]](f32)
   ; GFX1200-NEXT:   $vgpr7 = COPY [[UV7]](f32)
   ; GFX1200-NEXT:   $vgpr8 = COPY [[UV8]](f32)
   ; GFX1200-NEXT:   $vgpr9 = COPY [[UV9]](f32)
   ; GFX1200-NEXT:   $vgpr10 = COPY [[UV10]](f32)
   ; GFX1200-NEXT:   $vgpr11 = COPY [[UV11]](f32)
   ; GFX1200-NEXT:   $vgpr12 = COPY [[UV12]](f32)
   ; GFX1200-NEXT:   $vgpr13 = COPY [[UV13]](f32)
   ; GFX1200-NEXT:   $vgpr14 = COPY [[UV14]](f32)
   ; GFX1200-NEXT:   $vgpr15 = COPY [[UV15]](f32)
   ; GFX1200-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15
   ;
   ; GFX1250-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4032
   ; GFX1250: bb.1 (%ir-block.0):
   ; GFX1250-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
   ; GFX1250-NEXT: {{  $}}
   ; GFX1250-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX1250-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX1250-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX1250-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX1250-NEXT:   [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
   ; GFX1250-NEXT:   [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4032
   ; GFX1250-NEXT:   [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32)
   ; GFX1250-NEXT:   [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]]
   ; GFX1250-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX1250-NEXT:   [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0
   ; GFX1250-NEXT:   [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
   ; GFX1250-NEXT:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[ADD]], [[C1]], 0, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8)
   ; GFX1250-NEXT:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[ADD]], [[C1]], 16, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8)
   ; GFX1250-NEXT:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[ADD]], [[C1]], 32, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8)
   ; GFX1250-NEXT:   [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[ADD]], [[C1]], 48, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8)
   ; GFX1250-NEXT:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x f32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x f32>), [[AMDGPU_BUFFER_LOAD1]](<4 x f32>), [[AMDGPU_BUFFER_LOAD2]](<4 x f32>), [[AMDGPU_BUFFER_LOAD3]](<4 x f32>)
   ; GFX1250-NEXT:   [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32), [[UV4:%[0-9]+]]:vgpr(f32), [[UV5:%[0-9]+]]:vgpr(f32), [[UV6:%[0-9]+]]:vgpr(f32), [[UV7:%[0-9]+]]:vgpr(f32), [[UV8:%[0-9]+]]:vgpr(f32), [[UV9:%[0-9]+]]:vgpr(f32), [[UV10:%[0-9]+]]:vgpr(f32), [[UV11:%[0-9]+]]:vgpr(f32), [[UV12:%[0-9]+]]:vgpr(f32), [[UV13:%[0-9]+]]:vgpr(f32), [[UV14:%[0-9]+]]:vgpr(f32), [[UV15:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x f32>)
   ; GFX1250-NEXT:   $vgpr0 = COPY [[UV]](f32)
   ; GFX1250-NEXT:   $vgpr1 = COPY [[UV1]](f32)
   ; GFX1250-NEXT:   $vgpr2 = COPY [[UV2]](f32)
   ; GFX1250-NEXT:   $vgpr3 = COPY [[UV3]](f32)
   ; GFX1250-NEXT:   $vgpr4 = COPY [[UV4]](f32)
   ; GFX1250-NEXT:   $vgpr5 = COPY [[UV5]](f32)
   ; GFX1250-NEXT:   $vgpr6 = COPY [[UV6]](f32)
   ; GFX1250-NEXT:   $vgpr7 = COPY [[UV7]](f32)
   ; GFX1250-NEXT:   $vgpr8 = COPY [[UV8]](f32)
   ; GFX1250-NEXT:   $vgpr9 = COPY [[UV9]](f32)
   ; GFX1250-NEXT:   $vgpr10 = COPY [[UV10]](f32)
   ; GFX1250-NEXT:   $vgpr11 = COPY [[UV11]](f32)
   ; GFX1250-NEXT:   $vgpr12 = COPY [[UV12]](f32)
   ; GFX1250-NEXT:   $vgpr13 = COPY [[UV13]](f32)
   ; GFX1250-NEXT:   $vgpr14 = COPY [[UV14]](f32)
   ; GFX1250-NEXT:   $vgpr15 = COPY [[UV15]](f32)
   ; GFX1250-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15
   %soffset = add i32 %soffset.base, 4032
   %val = call <16 x float> @llvm.amdgcn.ptr.s.buffer.load.v16f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0
   ret <16 x float> %val
 }

 define amdgpu_ps <16 x float> @ptr_s_buffer_load_v16f32_vgpr_offset_add_4036(ptr addrspace(8) inreg %rsrc, i32 %soffset.base) {
   ; GFX7-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4036
   ; GFX7: bb.1 (%ir-block.0):
   ; GFX7-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
   ; GFX7-NEXT: {{  $}}
   ; GFX7-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX7-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX7-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX7-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX7-NEXT:   [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
   ; GFX7-NEXT:   [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4036
   ; GFX7-NEXT:   [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32)
   ; GFX7-NEXT:   [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]]
   ; GFX7-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX7-NEXT:   [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0
   ; GFX7-NEXT:   [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
   ; GFX7-NEXT:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[COPY4]], [[C1]], 4036, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8)
   ; GFX7-NEXT:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[COPY4]], [[C1]], 4052, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8)
   ; GFX7-NEXT:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[COPY4]], [[C1]], 4068, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8)
   ; GFX7-NEXT:   [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[COPY4]], [[C1]], 4084, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8)
   ; GFX7-NEXT:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x f32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x f32>), [[AMDGPU_BUFFER_LOAD1]](<4 x f32>), [[AMDGPU_BUFFER_LOAD2]](<4 x f32>), [[AMDGPU_BUFFER_LOAD3]](<4 x f32>)
   ; GFX7-NEXT:   [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32), [[UV4:%[0-9]+]]:vgpr(f32), [[UV5:%[0-9]+]]:vgpr(f32), [[UV6:%[0-9]+]]:vgpr(f32), [[UV7:%[0-9]+]]:vgpr(f32), [[UV8:%[0-9]+]]:vgpr(f32), [[UV9:%[0-9]+]]:vgpr(f32), [[UV10:%[0-9]+]]:vgpr(f32), [[UV11:%[0-9]+]]:vgpr(f32), [[UV12:%[0-9]+]]:vgpr(f32), [[UV13:%[0-9]+]]:vgpr(f32), [[UV14:%[0-9]+]]:vgpr(f32), [[UV15:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x f32>)
   ; GFX7-NEXT:   $vgpr0 = COPY [[UV]](f32)
   ; GFX7-NEXT:   $vgpr1 = COPY [[UV1]](f32)
   ; GFX7-NEXT:   $vgpr2 = COPY [[UV2]](f32)
   ; GFX7-NEXT:   $vgpr3 = COPY [[UV3]](f32)
   ; GFX7-NEXT:   $vgpr4 = COPY [[UV4]](f32)
   ; GFX7-NEXT:   $vgpr5 = COPY [[UV5]](f32)
   ; GFX7-NEXT:   $vgpr6 = COPY [[UV6]](f32)
   ; GFX7-NEXT:   $vgpr7 = COPY [[UV7]](f32)
   ; GFX7-NEXT:   $vgpr8 = COPY [[UV8]](f32)
   ; GFX7-NEXT:   $vgpr9 = COPY [[UV9]](f32)
   ; GFX7-NEXT:   $vgpr10 = COPY [[UV10]](f32)
   ; GFX7-NEXT:   $vgpr11 = COPY [[UV11]](f32)
   ; GFX7-NEXT:   $vgpr12 = COPY [[UV12]](f32)
   ; GFX7-NEXT:   $vgpr13 = COPY [[UV13]](f32)
   ; GFX7-NEXT:   $vgpr14 = COPY [[UV14]](f32)
   ; GFX7-NEXT:   $vgpr15 = COPY [[UV15]](f32)
   ; GFX7-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15
   ;
   ; GFX1200-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4036
   ; GFX1200: bb.1 (%ir-block.0):
   ; GFX1200-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
   ; GFX1200-NEXT: {{  $}}
   ; GFX1200-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX1200-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX1200-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX1200-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX1200-NEXT:   [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
   ; GFX1200-NEXT:   [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4036
   ; GFX1200-NEXT:   [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32)
   ; GFX1200-NEXT:   [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]]
   ; GFX1200-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX1200-NEXT:   [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0
   ; GFX1200-NEXT:   [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
   ; GFX1200-NEXT:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[COPY4]], [[C1]], 4036, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8)
   ; GFX1200-NEXT:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[COPY4]], [[C1]], 4052, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8)
   ; GFX1200-NEXT:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[COPY4]], [[C1]], 4068, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8)
   ; GFX1200-NEXT:   [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[COPY4]], [[C1]], 4084, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8)
   ; GFX1200-NEXT:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x f32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x f32>), [[AMDGPU_BUFFER_LOAD1]](<4 x f32>), [[AMDGPU_BUFFER_LOAD2]](<4 x f32>), [[AMDGPU_BUFFER_LOAD3]](<4 x f32>)
   ; GFX1200-NEXT:   [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32), [[UV4:%[0-9]+]]:vgpr(f32), [[UV5:%[0-9]+]]:vgpr(f32), [[UV6:%[0-9]+]]:vgpr(f32), [[UV7:%[0-9]+]]:vgpr(f32), [[UV8:%[0-9]+]]:vgpr(f32), [[UV9:%[0-9]+]]:vgpr(f32), [[UV10:%[0-9]+]]:vgpr(f32), [[UV11:%[0-9]+]]:vgpr(f32), [[UV12:%[0-9]+]]:vgpr(f32), [[UV13:%[0-9]+]]:vgpr(f32), [[UV14:%[0-9]+]]:vgpr(f32), [[UV15:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x f32>)
   ; GFX1200-NEXT:   $vgpr0 = COPY [[UV]](f32)
   ; GFX1200-NEXT:   $vgpr1 = COPY [[UV1]](f32)
   ; GFX1200-NEXT:   $vgpr2 = COPY [[UV2]](f32)
   ; GFX1200-NEXT:   $vgpr3 = COPY [[UV3]](f32)
   ; GFX1200-NEXT:   $vgpr4 = COPY [[UV4]](f32)
   ; GFX1200-NEXT:   $vgpr5 = COPY [[UV5]](f32)
   ; GFX1200-NEXT:   $vgpr6 = COPY [[UV6]](f32)
   ; GFX1200-NEXT:   $vgpr7 = COPY [[UV7]](f32)
   ; GFX1200-NEXT:   $vgpr8 = COPY [[UV8]](f32)
   ; GFX1200-NEXT:   $vgpr9 = COPY [[UV9]](f32)
   ; GFX1200-NEXT:   $vgpr10 = COPY [[UV10]](f32)
   ; GFX1200-NEXT:   $vgpr11 = COPY [[UV11]](f32)
   ; GFX1200-NEXT:   $vgpr12 = COPY [[UV12]](f32)
   ; GFX1200-NEXT:   $vgpr13 = COPY [[UV13]](f32)
   ; GFX1200-NEXT:   $vgpr14 = COPY [[UV14]](f32)
   ; GFX1200-NEXT:   $vgpr15 = COPY [[UV15]](f32)
   ; GFX1200-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15
   ;
   ; GFX1250-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4036
   ; GFX1250: bb.1 (%ir-block.0):
   ; GFX1250-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
   ; GFX1250-NEXT: {{  $}}
   ; GFX1250-NEXT:   [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2
   ; GFX1250-NEXT:   [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3
   ; GFX1250-NEXT:   [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4
   ; GFX1250-NEXT:   [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5
   ; GFX1250-NEXT:   [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0
   ; GFX1250-NEXT:   [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4036
   ; GFX1250-NEXT:   [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32)
   ; GFX1250-NEXT:   [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY5]]
   ; GFX1250-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32)
   ; GFX1250-NEXT:   [[C1:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0
   ; GFX1250-NEXT:   [[C2:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
   ; GFX1250-NEXT:   [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[ADD]], [[C1]], 0, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8)
   ; GFX1250-NEXT:   [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[ADD]], [[C1]], 16, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8)
   ; GFX1250-NEXT:   [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[ADD]], [[C1]], 32, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8)
   ; GFX1250-NEXT:   [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<4 x f32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[C2]](i32), [[ADD]], [[C1]], 48, 0, 0 :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8)
   ; GFX1250-NEXT:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x f32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x f32>), [[AMDGPU_BUFFER_LOAD1]](<4 x f32>), [[AMDGPU_BUFFER_LOAD2]](<4 x f32>), [[AMDGPU_BUFFER_LOAD3]](<4 x f32>)
   ; GFX1250-NEXT:   [[UV:%[0-9]+]]:vgpr(f32), [[UV1:%[0-9]+]]:vgpr(f32), [[UV2:%[0-9]+]]:vgpr(f32), [[UV3:%[0-9]+]]:vgpr(f32), [[UV4:%[0-9]+]]:vgpr(f32), [[UV5:%[0-9]+]]:vgpr(f32), [[UV6:%[0-9]+]]:vgpr(f32), [[UV7:%[0-9]+]]:vgpr(f32), [[UV8:%[0-9]+]]:vgpr(f32), [[UV9:%[0-9]+]]:vgpr(f32), [[UV10:%[0-9]+]]:vgpr(f32), [[UV11:%[0-9]+]]:vgpr(f32), [[UV12:%[0-9]+]]:vgpr(f32), [[UV13:%[0-9]+]]:vgpr(f32), [[UV14:%[0-9]+]]:vgpr(f32), [[UV15:%[0-9]+]]:vgpr(f32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x f32>)
   ; GFX1250-NEXT:   $vgpr0 = COPY [[UV]](f32)
   ; GFX1250-NEXT:   $vgpr1 = COPY [[UV1]](f32)
   ; GFX1250-NEXT:   $vgpr2 = COPY [[UV2]](f32)
   ; GFX1250-NEXT:   $vgpr3 = COPY [[UV3]](f32)
   ; GFX1250-NEXT:   $vgpr4 = COPY [[UV4]](f32)
   ; GFX1250-NEXT:   $vgpr5 = COPY [[UV5]](f32)
   ; GFX1250-NEXT:   $vgpr6 = COPY [[UV6]](f32)
   ; GFX1250-NEXT:   $vgpr7 = COPY [[UV7]](f32)
   ; GFX1250-NEXT:   $vgpr8 = COPY [[UV8]](f32)
   ; GFX1250-NEXT:   $vgpr9 = COPY [[UV9]](f32)
   ; GFX1250-NEXT:   $vgpr10 = COPY [[UV10]](f32)
   ; GFX1250-NEXT:   $vgpr11 = COPY [[UV11]](f32)
   ; GFX1250-NEXT:   $vgpr12 = COPY [[UV12]](f32)
   ; GFX1250-NEXT:   $vgpr13 = COPY [[UV13]](f32)
   ; GFX1250-NEXT:   $vgpr14 = COPY [[UV14]](f32)
   ; GFX1250-NEXT:   $vgpr15 = COPY [[UV15]](f32)
   ; GFX1250-NEXT:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15
   %soffset = add i32 %soffset.base, 4036
   %val = call <16 x float> @llvm.amdgcn.ptr.s.buffer.load.v16f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0
   ret <16 x float> %val
 }

 ; Waterfall loop due to resource being VGPR

 declare i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8), i32, i32 immarg)
 declare <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8), i32, i32 immarg)
 declare <3 x i32> @llvm.amdgcn.ptr.s.buffer.load.v3i32(ptr addrspace(8), i32, i32 immarg)
 declare <4 x i32> @llvm.amdgcn.ptr.s.buffer.load.v4i32(ptr addrspace(8), i32, i32 immarg)
 declare <8 x i32> @llvm.amdgcn.ptr.s.buffer.load.v8i32(ptr addrspace(8), i32, i32 immarg)
 declare <16 x i32> @llvm.amdgcn.ptr.s.buffer.load.v16i32(ptr addrspace(8), i32, i32 immarg)

 declare float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8), i32, i32      immarg)
 declare <2 x float> @llvm.amdgcn.ptr.s.buffer.load.v2f32(ptr addrspace(8), i32, i32 immarg)
 declare <3 x float> @llvm.amdgcn.ptr.s.buffer.load.v3f32(ptr addrspace(8), i32, i32 immarg)
 declare <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8), i32, i32 immarg)
 declare <8 x float> @llvm.amdgcn.ptr.s.buffer.load.v8f32(ptr addrspace(8), i32, i32 immarg)
 declare <16 x float> @llvm.amdgcn.ptr.s.buffer.load.v16f32(ptr addrspace(8), i32, i32 immarg)


 !0 = !{}