| ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| ; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX6 %s |
| ; RUN: llc -global-isel -mtriple=amdgpu7.00-mesa-mesa3d -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX7 %s |
| ; RUN: llc -global-isel -mtriple=amdgpu8.03-mesa-mesa3d -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX8 %s |
| ; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=GFX1200_1250,GFX1200 %s |
| ; RUN: llc -global-isel -mtriple=amdgpu12.50-mesa-mesa3d -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=GFX1200_1250,GFX1250 %s |
| |
| ; FIXME: Merge with regbankselect, which mostly overlaps when all types supported. |
| |
| ; Natural mapping |
| define amdgpu_ps i32 @ptr_s_buffer_load_i32(ptr addrspace(8) inreg %rsrc, i32 inreg %soffset) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_i32 |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec |
| ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_i32 |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec |
| ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_i32 |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec |
| ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32 |
| ; GFX1200_1250: bb.1 (%ir-block.0): |
| ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 |
| ; GFX1200_1250-NEXT: {{ $}} |
| ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR_IMM]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| %val = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 |
| ret i32 %val |
| } |
| |
| define amdgpu_ps i32 @ptr_s_buffer_load_i32_glc(ptr addrspace(8) inreg %rsrc, i32 inreg %soffset) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_i32_glc |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[COPY4]], 1 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec |
| ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_i32_glc |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[COPY4]], 1 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec |
| ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_i32_glc |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[COPY4]], 1 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec |
| ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_glc |
| ; GFX1200_1250: bb.1 (%ir-block.0): |
| ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 |
| ; GFX1200_1250-NEXT: {{ $}} |
| ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[COPY4]], 0, 1 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR_IMM]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| %val = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %rsrc, i32 %soffset, i32 1), !invariant.load !0 |
| ret i32 %val |
| } |
| |
| define amdgpu_ps <2 x i32> @ptr_s_buffer_load_v2i32(ptr addrspace(8) inreg %rsrc, i32 inreg %soffset) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_v2i32 |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORDX2_SGPR:%[0-9]+]]:sreg_64_xexec = S_BUFFER_LOAD_DWORDX2_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (<2 x i32>) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub0 |
| ; GFX6-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub1 |
| ; GFX6-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec |
| ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX6-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec |
| ; GFX6-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_v2i32 |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORDX2_SGPR:%[0-9]+]]:sreg_64_xexec = S_BUFFER_LOAD_DWORDX2_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (<2 x i32>) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub0 |
| ; GFX7-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub1 |
| ; GFX7-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec |
| ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX7-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec |
| ; GFX7-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_v2i32 |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORDX2_SGPR:%[0-9]+]]:sreg_64_xexec = S_BUFFER_LOAD_DWORDX2_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (<2 x i32>) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub0 |
| ; GFX8-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub1 |
| ; GFX8-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec |
| ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX8-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec |
| ; GFX8-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1 |
| ; |
| ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v2i32 |
| ; GFX1200_1250: bb.1 (%ir-block.0): |
| ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 |
| ; GFX1200_1250-NEXT: {{ $}} |
| ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORDX2_SGPR_IMM:%[0-9]+]]:sreg_64_xexec = S_BUFFER_LOAD_DWORDX2_SGPR_IMM [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load (<2 x i32>) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR_IMM]].sub0 |
| ; GFX1200_1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR_IMM]].sub1 |
| ; GFX1200_1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX1200_1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] |
| ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1 |
| %val = call <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 |
| ret <2 x i32> %val |
| } |
| |
| define amdgpu_ps <3 x i32> @ptr_s_buffer_load_v3i32(ptr addrspace(8) inreg %rsrc, i32 inreg %soffset) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_v3i32 |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORDX4_SGPR:%[0-9]+]]:sgpr_128 = S_BUFFER_LOAD_DWORDX4_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (<3 x i32>) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub0 |
| ; GFX6-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub1 |
| ; GFX6-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub2 |
| ; GFX6-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub3 |
| ; GFX6-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec |
| ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX6-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec |
| ; GFX6-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] |
| ; GFX6-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY7]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec |
| ; GFX6-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_v3i32 |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORDX4_SGPR:%[0-9]+]]:sgpr_128 = S_BUFFER_LOAD_DWORDX4_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (<3 x i32>) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub0 |
| ; GFX7-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub1 |
| ; GFX7-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub2 |
| ; GFX7-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub3 |
| ; GFX7-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec |
| ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX7-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec |
| ; GFX7-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] |
| ; GFX7-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY7]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec |
| ; GFX7-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_v3i32 |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORDX4_SGPR:%[0-9]+]]:sgpr_128 = S_BUFFER_LOAD_DWORDX4_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (<3 x i32>) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub0 |
| ; GFX8-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub1 |
| ; GFX8-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub2 |
| ; GFX8-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub3 |
| ; GFX8-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec |
| ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX8-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec |
| ; GFX8-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] |
| ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY7]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec |
| ; GFX8-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2 |
| ; |
| ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v3i32 |
| ; GFX1200_1250: bb.1 (%ir-block.0): |
| ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 |
| ; GFX1200_1250-NEXT: {{ $}} |
| ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORDX3_SGPR_IMM:%[0-9]+]]:sgpr_96 = S_BUFFER_LOAD_DWORDX3_SGPR_IMM [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load (<3 x i32>) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX3_SGPR_IMM]].sub0 |
| ; GFX1200_1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX3_SGPR_IMM]].sub1 |
| ; GFX1200_1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX3_SGPR_IMM]].sub2 |
| ; GFX1200_1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX1200_1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] |
| ; GFX1200_1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY7]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] |
| ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2 |
| %val = call <3 x i32> @llvm.amdgcn.ptr.s.buffer.load.v3i32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 |
| ret <3 x i32> %val |
| } |
| |
| define amdgpu_ps <8 x i32> @ptr_s_buffer_load_v8i32(ptr addrspace(8) inreg %rsrc, i32 inreg %soffset) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_v8i32 |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORDX8_SGPR:%[0-9]+]]:sgpr_256 = S_BUFFER_LOAD_DWORDX8_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (<8 x i32>) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub0 |
| ; GFX6-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub1 |
| ; GFX6-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub2 |
| ; GFX6-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub3 |
| ; GFX6-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub4 |
| ; GFX6-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub5 |
| ; GFX6-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub6 |
| ; GFX6-NEXT: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub7 |
| ; GFX6-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec |
| ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX6-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY14]], implicit $exec |
| ; GFX6-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] |
| ; GFX6-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[COPY7]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY15]], implicit $exec |
| ; GFX6-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] |
| ; GFX6-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[COPY8]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY16]], implicit $exec |
| ; GFX6-NEXT: $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]] |
| ; GFX6-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[COPY9]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY17]], implicit $exec |
| ; GFX6-NEXT: $sgpr4 = COPY [[V_READFIRSTLANE_B32_4]] |
| ; GFX6-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[COPY10]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY18]], implicit $exec |
| ; GFX6-NEXT: $sgpr5 = COPY [[V_READFIRSTLANE_B32_5]] |
| ; GFX6-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[COPY11]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY19]], implicit $exec |
| ; GFX6-NEXT: $sgpr6 = COPY [[V_READFIRSTLANE_B32_6]] |
| ; GFX6-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[COPY12]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY20]], implicit $exec |
| ; GFX6-NEXT: $sgpr7 = COPY [[V_READFIRSTLANE_B32_7]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_v8i32 |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORDX8_SGPR:%[0-9]+]]:sgpr_256 = S_BUFFER_LOAD_DWORDX8_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (<8 x i32>) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub0 |
| ; GFX7-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub1 |
| ; GFX7-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub2 |
| ; GFX7-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub3 |
| ; GFX7-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub4 |
| ; GFX7-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub5 |
| ; GFX7-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub6 |
| ; GFX7-NEXT: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub7 |
| ; GFX7-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec |
| ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX7-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY14]], implicit $exec |
| ; GFX7-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] |
| ; GFX7-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[COPY7]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY15]], implicit $exec |
| ; GFX7-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] |
| ; GFX7-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[COPY8]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY16]], implicit $exec |
| ; GFX7-NEXT: $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]] |
| ; GFX7-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[COPY9]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY17]], implicit $exec |
| ; GFX7-NEXT: $sgpr4 = COPY [[V_READFIRSTLANE_B32_4]] |
| ; GFX7-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[COPY10]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY18]], implicit $exec |
| ; GFX7-NEXT: $sgpr5 = COPY [[V_READFIRSTLANE_B32_5]] |
| ; GFX7-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[COPY11]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY19]], implicit $exec |
| ; GFX7-NEXT: $sgpr6 = COPY [[V_READFIRSTLANE_B32_6]] |
| ; GFX7-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[COPY12]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY20]], implicit $exec |
| ; GFX7-NEXT: $sgpr7 = COPY [[V_READFIRSTLANE_B32_7]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_v8i32 |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORDX8_SGPR:%[0-9]+]]:sgpr_256 = S_BUFFER_LOAD_DWORDX8_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (<8 x i32>) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub0 |
| ; GFX8-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub1 |
| ; GFX8-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub2 |
| ; GFX8-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub3 |
| ; GFX8-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub4 |
| ; GFX8-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub5 |
| ; GFX8-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub6 |
| ; GFX8-NEXT: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub7 |
| ; GFX8-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec |
| ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX8-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY14]], implicit $exec |
| ; GFX8-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] |
| ; GFX8-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[COPY7]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY15]], implicit $exec |
| ; GFX8-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] |
| ; GFX8-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[COPY8]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY16]], implicit $exec |
| ; GFX8-NEXT: $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]] |
| ; GFX8-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[COPY9]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY17]], implicit $exec |
| ; GFX8-NEXT: $sgpr4 = COPY [[V_READFIRSTLANE_B32_4]] |
| ; GFX8-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[COPY10]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY18]], implicit $exec |
| ; GFX8-NEXT: $sgpr5 = COPY [[V_READFIRSTLANE_B32_5]] |
| ; GFX8-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[COPY11]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY19]], implicit $exec |
| ; GFX8-NEXT: $sgpr6 = COPY [[V_READFIRSTLANE_B32_6]] |
| ; GFX8-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[COPY12]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY20]], implicit $exec |
| ; GFX8-NEXT: $sgpr7 = COPY [[V_READFIRSTLANE_B32_7]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7 |
| ; |
| ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v8i32 |
| ; GFX1200_1250: bb.1 (%ir-block.0): |
| ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 |
| ; GFX1200_1250-NEXT: {{ $}} |
| ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM:%[0-9]+]]:sgpr_256 = S_BUFFER_LOAD_DWORDX8_SGPR_IMM [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load (<8 x i32>) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub0 |
| ; GFX1200_1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub1 |
| ; GFX1200_1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub2 |
| ; GFX1200_1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub3 |
| ; GFX1200_1250-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub4 |
| ; GFX1200_1250-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub5 |
| ; GFX1200_1250-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub6 |
| ; GFX1200_1250-NEXT: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub7 |
| ; GFX1200_1250-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX1200_1250-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY14]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] |
| ; GFX1200_1250-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[COPY7]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY15]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] |
| ; GFX1200_1250-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[COPY8]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY16]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]] |
| ; GFX1200_1250-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[COPY9]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY17]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr4 = COPY [[V_READFIRSTLANE_B32_4]] |
| ; GFX1200_1250-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[COPY10]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY18]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr5 = COPY [[V_READFIRSTLANE_B32_5]] |
| ; GFX1200_1250-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[COPY11]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY19]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr6 = COPY [[V_READFIRSTLANE_B32_6]] |
| ; GFX1200_1250-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[COPY12]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY20]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr7 = COPY [[V_READFIRSTLANE_B32_7]] |
| ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7 |
| %val = call <8 x i32> @llvm.amdgcn.ptr.s.buffer.load.v8i32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 |
| ret <8 x i32> %val |
| } |
| |
| define amdgpu_ps <16 x i32> @ptr_s_buffer_load_v16i32(ptr addrspace(8) inreg %rsrc, i32 inreg %soffset) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_v16i32 |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORDX16_SGPR:%[0-9]+]]:sgpr_512 = S_BUFFER_LOAD_DWORDX16_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (<16 x i32>) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub0 |
| ; GFX6-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub1 |
| ; GFX6-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub2 |
| ; GFX6-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub3 |
| ; GFX6-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub4 |
| ; GFX6-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub5 |
| ; GFX6-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub6 |
| ; GFX6-NEXT: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub7 |
| ; GFX6-NEXT: [[COPY13:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub8 |
| ; GFX6-NEXT: [[COPY14:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub9 |
| ; GFX6-NEXT: [[COPY15:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub10 |
| ; GFX6-NEXT: [[COPY16:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub11 |
| ; GFX6-NEXT: [[COPY17:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub12 |
| ; GFX6-NEXT: [[COPY18:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub13 |
| ; GFX6-NEXT: [[COPY19:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub14 |
| ; GFX6-NEXT: [[COPY20:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub15 |
| ; GFX6-NEXT: [[COPY21:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY21]], implicit $exec |
| ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX6-NEXT: [[COPY22:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY22]], implicit $exec |
| ; GFX6-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] |
| ; GFX6-NEXT: [[COPY23:%[0-9]+]]:vgpr_32 = COPY [[COPY7]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY23]], implicit $exec |
| ; GFX6-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] |
| ; GFX6-NEXT: [[COPY24:%[0-9]+]]:vgpr_32 = COPY [[COPY8]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY24]], implicit $exec |
| ; GFX6-NEXT: $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]] |
| ; GFX6-NEXT: [[COPY25:%[0-9]+]]:vgpr_32 = COPY [[COPY9]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY25]], implicit $exec |
| ; GFX6-NEXT: $sgpr4 = COPY [[V_READFIRSTLANE_B32_4]] |
| ; GFX6-NEXT: [[COPY26:%[0-9]+]]:vgpr_32 = COPY [[COPY10]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY26]], implicit $exec |
| ; GFX6-NEXT: $sgpr5 = COPY [[V_READFIRSTLANE_B32_5]] |
| ; GFX6-NEXT: [[COPY27:%[0-9]+]]:vgpr_32 = COPY [[COPY11]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY27]], implicit $exec |
| ; GFX6-NEXT: $sgpr6 = COPY [[V_READFIRSTLANE_B32_6]] |
| ; GFX6-NEXT: [[COPY28:%[0-9]+]]:vgpr_32 = COPY [[COPY12]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY28]], implicit $exec |
| ; GFX6-NEXT: $sgpr7 = COPY [[V_READFIRSTLANE_B32_7]] |
| ; GFX6-NEXT: [[COPY29:%[0-9]+]]:vgpr_32 = COPY [[COPY13]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_8:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY29]], implicit $exec |
| ; GFX6-NEXT: $sgpr8 = COPY [[V_READFIRSTLANE_B32_8]] |
| ; GFX6-NEXT: [[COPY30:%[0-9]+]]:vgpr_32 = COPY [[COPY14]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_9:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY30]], implicit $exec |
| ; GFX6-NEXT: $sgpr9 = COPY [[V_READFIRSTLANE_B32_9]] |
| ; GFX6-NEXT: [[COPY31:%[0-9]+]]:vgpr_32 = COPY [[COPY15]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_10:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY31]], implicit $exec |
| ; GFX6-NEXT: $sgpr10 = COPY [[V_READFIRSTLANE_B32_10]] |
| ; GFX6-NEXT: [[COPY32:%[0-9]+]]:vgpr_32 = COPY [[COPY16]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_11:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY32]], implicit $exec |
| ; GFX6-NEXT: $sgpr11 = COPY [[V_READFIRSTLANE_B32_11]] |
| ; GFX6-NEXT: [[COPY33:%[0-9]+]]:vgpr_32 = COPY [[COPY17]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_12:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY33]], implicit $exec |
| ; GFX6-NEXT: $sgpr12 = COPY [[V_READFIRSTLANE_B32_12]] |
| ; GFX6-NEXT: [[COPY34:%[0-9]+]]:vgpr_32 = COPY [[COPY18]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_13:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY34]], implicit $exec |
| ; GFX6-NEXT: $sgpr13 = COPY [[V_READFIRSTLANE_B32_13]] |
| ; GFX6-NEXT: [[COPY35:%[0-9]+]]:vgpr_32 = COPY [[COPY19]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_14:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY35]], implicit $exec |
| ; GFX6-NEXT: $sgpr14 = COPY [[V_READFIRSTLANE_B32_14]] |
| ; GFX6-NEXT: [[COPY36:%[0-9]+]]:vgpr_32 = COPY [[COPY20]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_15:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY36]], implicit $exec |
| ; GFX6-NEXT: $sgpr15 = COPY [[V_READFIRSTLANE_B32_15]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_v16i32 |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORDX16_SGPR:%[0-9]+]]:sgpr_512 = S_BUFFER_LOAD_DWORDX16_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (<16 x i32>) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub0 |
| ; GFX7-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub1 |
| ; GFX7-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub2 |
| ; GFX7-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub3 |
| ; GFX7-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub4 |
| ; GFX7-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub5 |
| ; GFX7-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub6 |
| ; GFX7-NEXT: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub7 |
| ; GFX7-NEXT: [[COPY13:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub8 |
| ; GFX7-NEXT: [[COPY14:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub9 |
| ; GFX7-NEXT: [[COPY15:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub10 |
| ; GFX7-NEXT: [[COPY16:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub11 |
| ; GFX7-NEXT: [[COPY17:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub12 |
| ; GFX7-NEXT: [[COPY18:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub13 |
| ; GFX7-NEXT: [[COPY19:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub14 |
| ; GFX7-NEXT: [[COPY20:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub15 |
| ; GFX7-NEXT: [[COPY21:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY21]], implicit $exec |
| ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX7-NEXT: [[COPY22:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY22]], implicit $exec |
| ; GFX7-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] |
| ; GFX7-NEXT: [[COPY23:%[0-9]+]]:vgpr_32 = COPY [[COPY7]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY23]], implicit $exec |
| ; GFX7-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] |
| ; GFX7-NEXT: [[COPY24:%[0-9]+]]:vgpr_32 = COPY [[COPY8]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY24]], implicit $exec |
| ; GFX7-NEXT: $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]] |
| ; GFX7-NEXT: [[COPY25:%[0-9]+]]:vgpr_32 = COPY [[COPY9]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY25]], implicit $exec |
| ; GFX7-NEXT: $sgpr4 = COPY [[V_READFIRSTLANE_B32_4]] |
| ; GFX7-NEXT: [[COPY26:%[0-9]+]]:vgpr_32 = COPY [[COPY10]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY26]], implicit $exec |
| ; GFX7-NEXT: $sgpr5 = COPY [[V_READFIRSTLANE_B32_5]] |
| ; GFX7-NEXT: [[COPY27:%[0-9]+]]:vgpr_32 = COPY [[COPY11]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY27]], implicit $exec |
| ; GFX7-NEXT: $sgpr6 = COPY [[V_READFIRSTLANE_B32_6]] |
| ; GFX7-NEXT: [[COPY28:%[0-9]+]]:vgpr_32 = COPY [[COPY12]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY28]], implicit $exec |
| ; GFX7-NEXT: $sgpr7 = COPY [[V_READFIRSTLANE_B32_7]] |
| ; GFX7-NEXT: [[COPY29:%[0-9]+]]:vgpr_32 = COPY [[COPY13]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_8:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY29]], implicit $exec |
| ; GFX7-NEXT: $sgpr8 = COPY [[V_READFIRSTLANE_B32_8]] |
| ; GFX7-NEXT: [[COPY30:%[0-9]+]]:vgpr_32 = COPY [[COPY14]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_9:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY30]], implicit $exec |
| ; GFX7-NEXT: $sgpr9 = COPY [[V_READFIRSTLANE_B32_9]] |
| ; GFX7-NEXT: [[COPY31:%[0-9]+]]:vgpr_32 = COPY [[COPY15]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_10:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY31]], implicit $exec |
| ; GFX7-NEXT: $sgpr10 = COPY [[V_READFIRSTLANE_B32_10]] |
| ; GFX7-NEXT: [[COPY32:%[0-9]+]]:vgpr_32 = COPY [[COPY16]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_11:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY32]], implicit $exec |
| ; GFX7-NEXT: $sgpr11 = COPY [[V_READFIRSTLANE_B32_11]] |
| ; GFX7-NEXT: [[COPY33:%[0-9]+]]:vgpr_32 = COPY [[COPY17]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_12:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY33]], implicit $exec |
| ; GFX7-NEXT: $sgpr12 = COPY [[V_READFIRSTLANE_B32_12]] |
| ; GFX7-NEXT: [[COPY34:%[0-9]+]]:vgpr_32 = COPY [[COPY18]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_13:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY34]], implicit $exec |
| ; GFX7-NEXT: $sgpr13 = COPY [[V_READFIRSTLANE_B32_13]] |
| ; GFX7-NEXT: [[COPY35:%[0-9]+]]:vgpr_32 = COPY [[COPY19]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_14:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY35]], implicit $exec |
| ; GFX7-NEXT: $sgpr14 = COPY [[V_READFIRSTLANE_B32_14]] |
| ; GFX7-NEXT: [[COPY36:%[0-9]+]]:vgpr_32 = COPY [[COPY20]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_15:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY36]], implicit $exec |
| ; GFX7-NEXT: $sgpr15 = COPY [[V_READFIRSTLANE_B32_15]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_v16i32 |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORDX16_SGPR:%[0-9]+]]:sgpr_512 = S_BUFFER_LOAD_DWORDX16_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (<16 x i32>) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub0 |
| ; GFX8-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub1 |
| ; GFX8-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub2 |
| ; GFX8-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub3 |
| ; GFX8-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub4 |
| ; GFX8-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub5 |
| ; GFX8-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub6 |
| ; GFX8-NEXT: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub7 |
| ; GFX8-NEXT: [[COPY13:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub8 |
| ; GFX8-NEXT: [[COPY14:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub9 |
| ; GFX8-NEXT: [[COPY15:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub10 |
| ; GFX8-NEXT: [[COPY16:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub11 |
| ; GFX8-NEXT: [[COPY17:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub12 |
| ; GFX8-NEXT: [[COPY18:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub13 |
| ; GFX8-NEXT: [[COPY19:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub14 |
| ; GFX8-NEXT: [[COPY20:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub15 |
| ; GFX8-NEXT: [[COPY21:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY21]], implicit $exec |
| ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX8-NEXT: [[COPY22:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY22]], implicit $exec |
| ; GFX8-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] |
| ; GFX8-NEXT: [[COPY23:%[0-9]+]]:vgpr_32 = COPY [[COPY7]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY23]], implicit $exec |
| ; GFX8-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] |
| ; GFX8-NEXT: [[COPY24:%[0-9]+]]:vgpr_32 = COPY [[COPY8]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY24]], implicit $exec |
| ; GFX8-NEXT: $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]] |
| ; GFX8-NEXT: [[COPY25:%[0-9]+]]:vgpr_32 = COPY [[COPY9]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY25]], implicit $exec |
| ; GFX8-NEXT: $sgpr4 = COPY [[V_READFIRSTLANE_B32_4]] |
| ; GFX8-NEXT: [[COPY26:%[0-9]+]]:vgpr_32 = COPY [[COPY10]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY26]], implicit $exec |
| ; GFX8-NEXT: $sgpr5 = COPY [[V_READFIRSTLANE_B32_5]] |
| ; GFX8-NEXT: [[COPY27:%[0-9]+]]:vgpr_32 = COPY [[COPY11]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY27]], implicit $exec |
| ; GFX8-NEXT: $sgpr6 = COPY [[V_READFIRSTLANE_B32_6]] |
| ; GFX8-NEXT: [[COPY28:%[0-9]+]]:vgpr_32 = COPY [[COPY12]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY28]], implicit $exec |
| ; GFX8-NEXT: $sgpr7 = COPY [[V_READFIRSTLANE_B32_7]] |
| ; GFX8-NEXT: [[COPY29:%[0-9]+]]:vgpr_32 = COPY [[COPY13]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_8:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY29]], implicit $exec |
| ; GFX8-NEXT: $sgpr8 = COPY [[V_READFIRSTLANE_B32_8]] |
| ; GFX8-NEXT: [[COPY30:%[0-9]+]]:vgpr_32 = COPY [[COPY14]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_9:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY30]], implicit $exec |
| ; GFX8-NEXT: $sgpr9 = COPY [[V_READFIRSTLANE_B32_9]] |
| ; GFX8-NEXT: [[COPY31:%[0-9]+]]:vgpr_32 = COPY [[COPY15]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_10:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY31]], implicit $exec |
| ; GFX8-NEXT: $sgpr10 = COPY [[V_READFIRSTLANE_B32_10]] |
| ; GFX8-NEXT: [[COPY32:%[0-9]+]]:vgpr_32 = COPY [[COPY16]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_11:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY32]], implicit $exec |
| ; GFX8-NEXT: $sgpr11 = COPY [[V_READFIRSTLANE_B32_11]] |
| ; GFX8-NEXT: [[COPY33:%[0-9]+]]:vgpr_32 = COPY [[COPY17]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_12:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY33]], implicit $exec |
| ; GFX8-NEXT: $sgpr12 = COPY [[V_READFIRSTLANE_B32_12]] |
| ; GFX8-NEXT: [[COPY34:%[0-9]+]]:vgpr_32 = COPY [[COPY18]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_13:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY34]], implicit $exec |
| ; GFX8-NEXT: $sgpr13 = COPY [[V_READFIRSTLANE_B32_13]] |
| ; GFX8-NEXT: [[COPY35:%[0-9]+]]:vgpr_32 = COPY [[COPY19]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_14:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY35]], implicit $exec |
| ; GFX8-NEXT: $sgpr14 = COPY [[V_READFIRSTLANE_B32_14]] |
| ; GFX8-NEXT: [[COPY36:%[0-9]+]]:vgpr_32 = COPY [[COPY20]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_15:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY36]], implicit $exec |
| ; GFX8-NEXT: $sgpr15 = COPY [[V_READFIRSTLANE_B32_15]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15 |
| ; |
| ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v16i32 |
| ; GFX1200_1250: bb.1 (%ir-block.0): |
| ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 |
| ; GFX1200_1250-NEXT: {{ $}} |
| ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM:%[0-9]+]]:sgpr_512 = S_BUFFER_LOAD_DWORDX16_SGPR_IMM [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load (<16 x i32>) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub0 |
| ; GFX1200_1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub1 |
| ; GFX1200_1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub2 |
| ; GFX1200_1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub3 |
| ; GFX1200_1250-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub4 |
| ; GFX1200_1250-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub5 |
| ; GFX1200_1250-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub6 |
| ; GFX1200_1250-NEXT: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub7 |
| ; GFX1200_1250-NEXT: [[COPY13:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub8 |
| ; GFX1200_1250-NEXT: [[COPY14:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub9 |
| ; GFX1200_1250-NEXT: [[COPY15:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub10 |
| ; GFX1200_1250-NEXT: [[COPY16:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub11 |
| ; GFX1200_1250-NEXT: [[COPY17:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub12 |
| ; GFX1200_1250-NEXT: [[COPY18:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub13 |
| ; GFX1200_1250-NEXT: [[COPY19:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub14 |
| ; GFX1200_1250-NEXT: [[COPY20:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub15 |
| ; GFX1200_1250-NEXT: [[COPY21:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY21]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX1200_1250-NEXT: [[COPY22:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY22]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] |
| ; GFX1200_1250-NEXT: [[COPY23:%[0-9]+]]:vgpr_32 = COPY [[COPY7]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY23]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] |
| ; GFX1200_1250-NEXT: [[COPY24:%[0-9]+]]:vgpr_32 = COPY [[COPY8]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY24]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]] |
| ; GFX1200_1250-NEXT: [[COPY25:%[0-9]+]]:vgpr_32 = COPY [[COPY9]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY25]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr4 = COPY [[V_READFIRSTLANE_B32_4]] |
| ; GFX1200_1250-NEXT: [[COPY26:%[0-9]+]]:vgpr_32 = COPY [[COPY10]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY26]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr5 = COPY [[V_READFIRSTLANE_B32_5]] |
| ; GFX1200_1250-NEXT: [[COPY27:%[0-9]+]]:vgpr_32 = COPY [[COPY11]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY27]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr6 = COPY [[V_READFIRSTLANE_B32_6]] |
| ; GFX1200_1250-NEXT: [[COPY28:%[0-9]+]]:vgpr_32 = COPY [[COPY12]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY28]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr7 = COPY [[V_READFIRSTLANE_B32_7]] |
| ; GFX1200_1250-NEXT: [[COPY29:%[0-9]+]]:vgpr_32 = COPY [[COPY13]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_8:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY29]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr8 = COPY [[V_READFIRSTLANE_B32_8]] |
| ; GFX1200_1250-NEXT: [[COPY30:%[0-9]+]]:vgpr_32 = COPY [[COPY14]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_9:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY30]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr9 = COPY [[V_READFIRSTLANE_B32_9]] |
| ; GFX1200_1250-NEXT: [[COPY31:%[0-9]+]]:vgpr_32 = COPY [[COPY15]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_10:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY31]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr10 = COPY [[V_READFIRSTLANE_B32_10]] |
| ; GFX1200_1250-NEXT: [[COPY32:%[0-9]+]]:vgpr_32 = COPY [[COPY16]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_11:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY32]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr11 = COPY [[V_READFIRSTLANE_B32_11]] |
| ; GFX1200_1250-NEXT: [[COPY33:%[0-9]+]]:vgpr_32 = COPY [[COPY17]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_12:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY33]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr12 = COPY [[V_READFIRSTLANE_B32_12]] |
| ; GFX1200_1250-NEXT: [[COPY34:%[0-9]+]]:vgpr_32 = COPY [[COPY18]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_13:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY34]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr13 = COPY [[V_READFIRSTLANE_B32_13]] |
| ; GFX1200_1250-NEXT: [[COPY35:%[0-9]+]]:vgpr_32 = COPY [[COPY19]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_14:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY35]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr14 = COPY [[V_READFIRSTLANE_B32_14]] |
| ; GFX1200_1250-NEXT: [[COPY36:%[0-9]+]]:vgpr_32 = COPY [[COPY20]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_15:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY36]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr15 = COPY [[V_READFIRSTLANE_B32_15]] |
| ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15 |
| %val = call <16 x i32> @llvm.amdgcn.ptr.s.buffer.load.v16i32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 |
| ret <16 x i32> %val |
| } |
| |
| define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_1(ptr addrspace(8) inreg %rsrc) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_1 |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_1 |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_1 |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_1 |
| ; GFX1200_1250: bb.1 (%ir-block.0): |
| ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX1200_1250-NEXT: {{ $}} |
| ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| %val = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %rsrc, i32 1, i32 0), !invariant.load !0 |
| ret i32 %val |
| } |
| |
| define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_glc_4(ptr addrspace(8) inreg %rsrc) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_glc_4 |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1, 1 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_glc_4 |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1, 1 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_glc_4 |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 4, 1 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_glc_4 |
| ; GFX1200_1250: bb.1 (%ir-block.0): |
| ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX1200_1250-NEXT: {{ $}} |
| ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 4, 1 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| %val = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %rsrc, i32 4, i32 1), !invariant.load !0 |
| ret i32 %val |
| } |
| |
| define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_255(ptr addrspace(8) inreg %rsrc) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_255 |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 255 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_255 |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 255 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_255 |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 255, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_255 |
| ; GFX1200_1250: bb.1 (%ir-block.0): |
| ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX1200_1250-NEXT: {{ $}} |
| ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 255, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| %val = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %rsrc, i32 255, i32 0), !invariant.load !0 |
| ret i32 %val |
| } |
| |
| define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_256(ptr addrspace(8) inreg %rsrc) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_256 |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 64, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_256 |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 64, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_256 |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 256, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_256 |
| ; GFX1200_1250: bb.1 (%ir-block.0): |
| ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX1200_1250-NEXT: {{ $}} |
| ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 256, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| %val = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %rsrc, i32 256, i32 0), !invariant.load !0 |
| ret i32 %val |
| } |
| |
| define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_1020(ptr addrspace(8) inreg %rsrc) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_1020 |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 255, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_1020 |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 255, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_1020 |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1020, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_1020 |
| ; GFX1200_1250: bb.1 (%ir-block.0): |
| ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX1200_1250-NEXT: {{ $}} |
| ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1020, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| %val = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %rsrc, i32 1020, i32 0), !invariant.load !0 |
| ret i32 %val |
| } |
| |
| define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_1023(ptr addrspace(8) inreg %rsrc) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_1023 |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1023 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_1023 |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1023 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_1023 |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1023, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_1023 |
| ; GFX1200_1250: bb.1 (%ir-block.0): |
| ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX1200_1250-NEXT: {{ $}} |
| ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1023, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| %val = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %rsrc, i32 1023, i32 0), !invariant.load !0 |
| ret i32 %val |
| } |
| |
| define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_1024(ptr addrspace(8) inreg %rsrc) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_1024 |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1024 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_1024 |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM_ci [[REG_SEQUENCE]], 256, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM_ci]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_1024 |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1024, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_1024 |
| ; GFX1200_1250: bb.1 (%ir-block.0): |
| ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX1200_1250-NEXT: {{ $}} |
| ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1024, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| %val = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %rsrc, i32 1024, i32 0), !invariant.load !0 |
| ret i32 %val |
| } |
| |
| define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_1025(ptr addrspace(8) inreg %rsrc) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_1025 |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1025 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_1025 |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1025 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_1025 |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1025, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_1025 |
| ; GFX1200_1250: bb.1 (%ir-block.0): |
| ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX1200_1250-NEXT: {{ $}} |
| ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1025, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| %val = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %rsrc, i32 1025, i32 0), !invariant.load !0 |
| ret i32 %val |
| } |
| |
| define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_neg1(ptr addrspace(8) inreg %desc) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_neg1 |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_neg1 |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_neg1 |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_neg1 |
| ; GFX1200_1250: bb.1 (%ir-block.0): |
| ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX1200_1250-NEXT: {{ $}} |
| ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200_1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1 |
| ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR_IMM]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| %load = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %desc, i32 -1, i32 0), !invariant.load !0 |
| ret i32 %load |
| } |
| |
| define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_neg4(ptr addrspace(8) inreg %desc) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_neg4 |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -4 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_neg4 |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM_ci [[REG_SEQUENCE]], 1073741823, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM_ci]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_neg4 |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -4 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_neg4 |
| ; GFX1200_1250: bb.1 (%ir-block.0): |
| ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX1200_1250-NEXT: {{ $}} |
| ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200_1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -4 |
| ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR_IMM]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| %load = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %desc, i32 -4, i32 0), !invariant.load !0 |
| ret i32 %load |
| } |
| |
| define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_neg8(ptr addrspace(8) inreg %desc) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_neg8 |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -8 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_neg8 |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM_ci [[REG_SEQUENCE]], 1073741822, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM_ci]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_neg8 |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -8 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_neg8 |
| ; GFX1200_1250: bb.1 (%ir-block.0): |
| ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX1200_1250-NEXT: {{ $}} |
| ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200_1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -8 |
| ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR_IMM]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| %load = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %desc, i32 -8, i32 0), !invariant.load !0 |
| ret i32 %load |
| } |
| |
| define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_bit31(ptr addrspace(8) inreg %desc) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_bit31 |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -2147483648 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_bit31 |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM_ci [[REG_SEQUENCE]], 536870912, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM_ci]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_bit31 |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -2147483648 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_bit31 |
| ; GFX1200_1250: bb.1 (%ir-block.0): |
| ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX1200_1250-NEXT: {{ $}} |
| ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200_1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -2147483648 |
| ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR_IMM]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| %load = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %desc, i32 -2147483648, i32 0), !invariant.load !0 |
| ret i32 %load |
| } |
| |
| define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_glc_bit30(ptr addrspace(8) inreg %desc) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_glc_bit30 |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1073741824 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 1 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_glc_bit30 |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM_ci [[REG_SEQUENCE]], 268435456, 1 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM_ci]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_glc_bit30 |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1073741824 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 1 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_glc_bit30 |
| ; GFX1200_1250: bb.1 (%ir-block.0): |
| ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX1200_1250-NEXT: {{ $}} |
| ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200_1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1073741824 |
| ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 1 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR_IMM]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| %load = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %desc, i32 1073741824, i32 1), !invariant.load !0 |
| ret i32 %load |
| } |
| |
| define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_bit29(ptr addrspace(8) inreg %desc) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_bit29 |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 536870912 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_bit29 |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM_ci [[REG_SEQUENCE]], 134217728, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM_ci]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_bit29 |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 536870912 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_bit29 |
| ; GFX1200_1250: bb.1 (%ir-block.0): |
| ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX1200_1250-NEXT: {{ $}} |
| ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200_1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 536870912 |
| ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR_IMM]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| %load = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %desc, i32 536870912, i32 0), !invariant.load !0 |
| ret i32 %load |
| } |
| |
| define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_bit21(ptr addrspace(8) inreg %desc) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_bit21 |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2097152 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_bit21 |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM_ci [[REG_SEQUENCE]], 524288, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM_ci]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_bit21 |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2097152 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_bit21 |
| ; GFX1200_1250: bb.1 (%ir-block.0): |
| ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX1200_1250-NEXT: {{ $}} |
| ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 2097152, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| %load = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %desc, i32 2097152, i32 0), !invariant.load !0 |
| ret i32 %load |
| } |
| |
| define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_bit20(ptr addrspace(8) inreg %desc) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_bit20 |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1048576 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_bit20 |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM_ci [[REG_SEQUENCE]], 262144, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM_ci]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_bit20 |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1048576 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_bit20 |
| ; GFX1200_1250: bb.1 (%ir-block.0): |
| ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX1200_1250-NEXT: {{ $}} |
| ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1048576, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| %load = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %desc, i32 1048576, i32 0), !invariant.load !0 |
| ret i32 %load |
| } |
| |
| define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_neg_bit20(ptr addrspace(8) inreg %desc) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_neg_bit20 |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1048576 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_neg_bit20 |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM_ci [[REG_SEQUENCE]], 1073479680, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM_ci]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_neg_bit20 |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1048576 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_neg_bit20 |
| ; GFX1200_1250: bb.1 (%ir-block.0): |
| ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX1200_1250-NEXT: {{ $}} |
| ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200_1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1048576 |
| ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR_IMM]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| %load = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %desc, i32 -1048576, i32 0), !invariant.load !0 |
| ret i32 %load |
| } |
| |
| define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_bit19(ptr addrspace(8) inreg %desc) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_bit19 |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 524288 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_bit19 |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM_ci [[REG_SEQUENCE]], 131072, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM_ci]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_bit19 |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 524288, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_bit19 |
| ; GFX1200_1250: bb.1 (%ir-block.0): |
| ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX1200_1250-NEXT: {{ $}} |
| ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 524288, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| %load = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %desc, i32 524288, i32 0), !invariant.load !0 |
| ret i32 %load |
| } |
| |
| define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_neg_bit19(ptr addrspace(8) inreg %desc) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_i32_offset_neg_bit19 |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -524288 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_i32_offset_neg_bit19 |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_BUFFER_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM_ci [[REG_SEQUENCE]], 1073610752, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM_ci]] |
| ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_i32_offset_neg_bit19 |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -524288 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]] |
| ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ; |
| ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_neg_bit19 |
| ; GFX1200_1250: bb.1 (%ir-block.0): |
| ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 |
| ; GFX1200_1250-NEXT: {{ $}} |
| ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200_1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -524288 |
| ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) |
| ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR_IMM]] |
| ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec |
| ; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] |
| ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| %load = call i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8) %desc, i32 -524288, i32 0), !invariant.load !0 |
| ret i32 %load |
| } |
| |
| ; Check cases that need to be converted to MUBUF due to the offset being a VGPR. |
| define amdgpu_ps float @ptr_s_buffer_load_f32_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %soffset) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX6-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX7-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX7-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX8-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX8-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 |
| ; |
| ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset |
| ; GFX1200_1250: bb.1 (%ir-block.0): |
| ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX1200_1250-NEXT: {{ $}} |
| ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200_1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1200_1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] |
| ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 |
| %val = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 |
| ret float %val |
| } |
| |
| define amdgpu_ps <2 x float> @ptr_s_buffer_load_v2f32_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %soffset) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_v2f32_vgpr_offset |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX2_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s64) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub0 |
| ; GFX6-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub1 |
| ; GFX6-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX6-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_v2f32_vgpr_offset |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX2_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s64) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub0 |
| ; GFX7-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub1 |
| ; GFX7-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX7-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_v2f32_vgpr_offset |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX2_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s64) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub0 |
| ; GFX8-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub1 |
| ; GFX8-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX8-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 |
| ; |
| ; GFX1200-LABEL: name: ptr_s_buffer_load_v2f32_vgpr_offset |
| ; GFX1200: bb.1 (%ir-block.0): |
| ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX1200-NEXT: {{ $}} |
| ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s64) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN]].sub0 |
| ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN]].sub1 |
| ; GFX1200-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX1200-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 |
| ; |
| ; GFX1250-LABEL: name: ptr_s_buffer_load_v2f32_vgpr_offset |
| ; GFX1250: bb.1 (%ir-block.0): |
| ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX1250-NEXT: {{ $}} |
| ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN:%[0-9]+]]:vreg_64_align2 = BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s64) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN]].sub0 |
| ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN]].sub1 |
| ; GFX1250-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX1250-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 |
| %val = call <2 x float> @llvm.amdgcn.ptr.s.buffer.load.v2f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 |
| ret <2 x float> %val |
| } |
| |
| define amdgpu_ps <3 x float> @ptr_s_buffer_load_v3f32_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %soffset) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_v3f32_vgpr_offset |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s96) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub0 |
| ; GFX6-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub1 |
| ; GFX6-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub2 |
| ; GFX6-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub3 |
| ; GFX6-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX6-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX6-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_v3f32_vgpr_offset |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s96) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub0 |
| ; GFX7-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub1 |
| ; GFX7-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub2 |
| ; GFX7-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub3 |
| ; GFX7-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX7-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX7-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_v3f32_vgpr_offset |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s96) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub0 |
| ; GFX8-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub1 |
| ; GFX8-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub2 |
| ; GFX8-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub3 |
| ; GFX8-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX8-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX8-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 |
| ; |
| ; GFX1200-LABEL: name: ptr_s_buffer_load_v3f32_vgpr_offset |
| ; GFX1200: bb.1 (%ir-block.0): |
| ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX1200-NEXT: {{ $}} |
| ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN:%[0-9]+]]:vreg_96 = BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s96) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN]].sub0 |
| ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN]].sub1 |
| ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN]].sub2 |
| ; GFX1200-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX1200-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX1200-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 |
| ; |
| ; GFX1250-LABEL: name: ptr_s_buffer_load_v3f32_vgpr_offset |
| ; GFX1250: bb.1 (%ir-block.0): |
| ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX1250-NEXT: {{ $}} |
| ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN:%[0-9]+]]:vreg_96_align2 = BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s96) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN]].sub0 |
| ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN]].sub1 |
| ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN]].sub2 |
| ; GFX1250-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX1250-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX1250-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 |
| %val = call <3 x float> @llvm.amdgcn.ptr.s.buffer.load.v3f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 |
| ret <3 x float> %val |
| } |
| |
| define amdgpu_ps <4 x float> @ptr_s_buffer_load_v4f32_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %soffset) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_v4f32_vgpr_offset |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub0 |
| ; GFX6-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub1 |
| ; GFX6-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub2 |
| ; GFX6-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub3 |
| ; GFX6-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX6-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX6-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX6-NEXT: $vgpr3 = COPY [[COPY8]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_v4f32_vgpr_offset |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub0 |
| ; GFX7-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub1 |
| ; GFX7-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub2 |
| ; GFX7-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub3 |
| ; GFX7-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX7-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX7-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX7-NEXT: $vgpr3 = COPY [[COPY8]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_v4f32_vgpr_offset |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub0 |
| ; GFX8-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub1 |
| ; GFX8-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub2 |
| ; GFX8-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub3 |
| ; GFX8-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX8-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX8-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX8-NEXT: $vgpr3 = COPY [[COPY8]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 |
| ; |
| ; GFX1200-LABEL: name: ptr_s_buffer_load_v4f32_vgpr_offset |
| ; GFX1200: bb.1 (%ir-block.0): |
| ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX1200-NEXT: {{ $}} |
| ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]].sub0 |
| ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]].sub1 |
| ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]].sub2 |
| ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]].sub3 |
| ; GFX1200-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX1200-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX1200-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX1200-NEXT: $vgpr3 = COPY [[COPY8]] |
| ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 |
| ; |
| ; GFX1250-LABEL: name: ptr_s_buffer_load_v4f32_vgpr_offset |
| ; GFX1250: bb.1 (%ir-block.0): |
| ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX1250-NEXT: {{ $}} |
| ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]].sub0 |
| ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]].sub1 |
| ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]].sub2 |
| ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]].sub3 |
| ; GFX1250-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX1250-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX1250-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX1250-NEXT: $vgpr3 = COPY [[COPY8]] |
| ; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 |
| %val = call <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 |
| ret <4 x float> %val |
| } |
| |
| define amdgpu_ps <8 x float> @ptr_s_buffer_load_v8f32_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %soffset) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) |
| ; GFX6-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7 |
| ; GFX6-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 |
| ; GFX6-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 |
| ; GFX6-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 |
| ; GFX6-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 |
| ; GFX6-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 |
| ; GFX6-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 |
| ; GFX6-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 |
| ; GFX6-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 |
| ; GFX6-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX6-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX6-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX6-NEXT: $vgpr3 = COPY [[COPY8]] |
| ; GFX6-NEXT: $vgpr4 = COPY [[COPY9]] |
| ; GFX6-NEXT: $vgpr5 = COPY [[COPY10]] |
| ; GFX6-NEXT: $vgpr6 = COPY [[COPY11]] |
| ; GFX6-NEXT: $vgpr7 = COPY [[COPY12]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) |
| ; GFX7-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7 |
| ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 |
| ; GFX7-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 |
| ; GFX7-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 |
| ; GFX7-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 |
| ; GFX7-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 |
| ; GFX7-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 |
| ; GFX7-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 |
| ; GFX7-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 |
| ; GFX7-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX7-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX7-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX7-NEXT: $vgpr3 = COPY [[COPY8]] |
| ; GFX7-NEXT: $vgpr4 = COPY [[COPY9]] |
| ; GFX7-NEXT: $vgpr5 = COPY [[COPY10]] |
| ; GFX7-NEXT: $vgpr6 = COPY [[COPY11]] |
| ; GFX7-NEXT: $vgpr7 = COPY [[COPY12]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) |
| ; GFX8-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7 |
| ; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 |
| ; GFX8-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 |
| ; GFX8-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 |
| ; GFX8-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 |
| ; GFX8-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 |
| ; GFX8-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 |
| ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 |
| ; GFX8-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 |
| ; GFX8-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX8-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX8-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX8-NEXT: $vgpr3 = COPY [[COPY8]] |
| ; GFX8-NEXT: $vgpr4 = COPY [[COPY9]] |
| ; GFX8-NEXT: $vgpr5 = COPY [[COPY10]] |
| ; GFX8-NEXT: $vgpr6 = COPY [[COPY11]] |
| ; GFX8-NEXT: $vgpr7 = COPY [[COPY12]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 |
| ; |
| ; GFX1200-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset |
| ; GFX1200: bb.1 (%ir-block.0): |
| ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX1200-NEXT: {{ $}} |
| ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 16, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) |
| ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1]], %subreg.sub4_sub5_sub6_sub7 |
| ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 |
| ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 |
| ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 |
| ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 |
| ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 |
| ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 |
| ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 |
| ; GFX1200-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 |
| ; GFX1200-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX1200-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX1200-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX1200-NEXT: $vgpr3 = COPY [[COPY8]] |
| ; GFX1200-NEXT: $vgpr4 = COPY [[COPY9]] |
| ; GFX1200-NEXT: $vgpr5 = COPY [[COPY10]] |
| ; GFX1200-NEXT: $vgpr6 = COPY [[COPY11]] |
| ; GFX1200-NEXT: $vgpr7 = COPY [[COPY12]] |
| ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 |
| ; |
| ; GFX1250-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset |
| ; GFX1250: bb.1 (%ir-block.0): |
| ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX1250-NEXT: {{ $}} |
| ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 16, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) |
| ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_256_align2 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1]], %subreg.sub4_sub5_sub6_sub7 |
| ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 |
| ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 |
| ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 |
| ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 |
| ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 |
| ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 |
| ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 |
| ; GFX1250-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 |
| ; GFX1250-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX1250-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX1250-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX1250-NEXT: $vgpr3 = COPY [[COPY8]] |
| ; GFX1250-NEXT: $vgpr4 = COPY [[COPY9]] |
| ; GFX1250-NEXT: $vgpr5 = COPY [[COPY10]] |
| ; GFX1250-NEXT: $vgpr6 = COPY [[COPY11]] |
| ; GFX1250-NEXT: $vgpr7 = COPY [[COPY12]] |
| ; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 |
| %val = call <8 x float> @llvm.amdgcn.ptr.s.buffer.load.v8f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 |
| ret <8 x float> %val |
| } |
| |
| define amdgpu_ps <16 x float> @ptr_s_buffer_load_v16f32_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %soffset) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) |
| ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 32, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) |
| ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 48, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) |
| ; GFX6-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15 |
| ; GFX6-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 |
| ; GFX6-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 |
| ; GFX6-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 |
| ; GFX6-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 |
| ; GFX6-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 |
| ; GFX6-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 |
| ; GFX6-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 |
| ; GFX6-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 |
| ; GFX6-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8 |
| ; GFX6-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9 |
| ; GFX6-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10 |
| ; GFX6-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11 |
| ; GFX6-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12 |
| ; GFX6-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13 |
| ; GFX6-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14 |
| ; GFX6-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15 |
| ; GFX6-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX6-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX6-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX6-NEXT: $vgpr3 = COPY [[COPY8]] |
| ; GFX6-NEXT: $vgpr4 = COPY [[COPY9]] |
| ; GFX6-NEXT: $vgpr5 = COPY [[COPY10]] |
| ; GFX6-NEXT: $vgpr6 = COPY [[COPY11]] |
| ; GFX6-NEXT: $vgpr7 = COPY [[COPY12]] |
| ; GFX6-NEXT: $vgpr8 = COPY [[COPY13]] |
| ; GFX6-NEXT: $vgpr9 = COPY [[COPY14]] |
| ; GFX6-NEXT: $vgpr10 = COPY [[COPY15]] |
| ; GFX6-NEXT: $vgpr11 = COPY [[COPY16]] |
| ; GFX6-NEXT: $vgpr12 = COPY [[COPY17]] |
| ; GFX6-NEXT: $vgpr13 = COPY [[COPY18]] |
| ; GFX6-NEXT: $vgpr14 = COPY [[COPY19]] |
| ; GFX6-NEXT: $vgpr15 = COPY [[COPY20]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) |
| ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 32, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) |
| ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 48, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) |
| ; GFX7-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15 |
| ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 |
| ; GFX7-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 |
| ; GFX7-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 |
| ; GFX7-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 |
| ; GFX7-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 |
| ; GFX7-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 |
| ; GFX7-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 |
| ; GFX7-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 |
| ; GFX7-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8 |
| ; GFX7-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9 |
| ; GFX7-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10 |
| ; GFX7-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11 |
| ; GFX7-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12 |
| ; GFX7-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13 |
| ; GFX7-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14 |
| ; GFX7-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15 |
| ; GFX7-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX7-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX7-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX7-NEXT: $vgpr3 = COPY [[COPY8]] |
| ; GFX7-NEXT: $vgpr4 = COPY [[COPY9]] |
| ; GFX7-NEXT: $vgpr5 = COPY [[COPY10]] |
| ; GFX7-NEXT: $vgpr6 = COPY [[COPY11]] |
| ; GFX7-NEXT: $vgpr7 = COPY [[COPY12]] |
| ; GFX7-NEXT: $vgpr8 = COPY [[COPY13]] |
| ; GFX7-NEXT: $vgpr9 = COPY [[COPY14]] |
| ; GFX7-NEXT: $vgpr10 = COPY [[COPY15]] |
| ; GFX7-NEXT: $vgpr11 = COPY [[COPY16]] |
| ; GFX7-NEXT: $vgpr12 = COPY [[COPY17]] |
| ; GFX7-NEXT: $vgpr13 = COPY [[COPY18]] |
| ; GFX7-NEXT: $vgpr14 = COPY [[COPY19]] |
| ; GFX7-NEXT: $vgpr15 = COPY [[COPY20]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) |
| ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 32, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) |
| ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 48, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) |
| ; GFX8-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15 |
| ; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 |
| ; GFX8-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 |
| ; GFX8-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 |
| ; GFX8-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 |
| ; GFX8-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 |
| ; GFX8-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 |
| ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 |
| ; GFX8-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 |
| ; GFX8-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8 |
| ; GFX8-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9 |
| ; GFX8-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10 |
| ; GFX8-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11 |
| ; GFX8-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12 |
| ; GFX8-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13 |
| ; GFX8-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14 |
| ; GFX8-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15 |
| ; GFX8-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX8-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX8-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX8-NEXT: $vgpr3 = COPY [[COPY8]] |
| ; GFX8-NEXT: $vgpr4 = COPY [[COPY9]] |
| ; GFX8-NEXT: $vgpr5 = COPY [[COPY10]] |
| ; GFX8-NEXT: $vgpr6 = COPY [[COPY11]] |
| ; GFX8-NEXT: $vgpr7 = COPY [[COPY12]] |
| ; GFX8-NEXT: $vgpr8 = COPY [[COPY13]] |
| ; GFX8-NEXT: $vgpr9 = COPY [[COPY14]] |
| ; GFX8-NEXT: $vgpr10 = COPY [[COPY15]] |
| ; GFX8-NEXT: $vgpr11 = COPY [[COPY16]] |
| ; GFX8-NEXT: $vgpr12 = COPY [[COPY17]] |
| ; GFX8-NEXT: $vgpr13 = COPY [[COPY18]] |
| ; GFX8-NEXT: $vgpr14 = COPY [[COPY19]] |
| ; GFX8-NEXT: $vgpr15 = COPY [[COPY20]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 |
| ; |
| ; GFX1200-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset |
| ; GFX1200: bb.1 (%ir-block.0): |
| ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX1200-NEXT: {{ $}} |
| ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 16, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) |
| ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 32, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) |
| ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 48, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) |
| ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN3]], %subreg.sub12_sub13_sub14_sub15 |
| ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 |
| ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 |
| ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 |
| ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 |
| ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 |
| ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 |
| ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 |
| ; GFX1200-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 |
| ; GFX1200-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8 |
| ; GFX1200-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9 |
| ; GFX1200-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10 |
| ; GFX1200-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11 |
| ; GFX1200-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12 |
| ; GFX1200-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13 |
| ; GFX1200-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14 |
| ; GFX1200-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15 |
| ; GFX1200-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX1200-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX1200-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX1200-NEXT: $vgpr3 = COPY [[COPY8]] |
| ; GFX1200-NEXT: $vgpr4 = COPY [[COPY9]] |
| ; GFX1200-NEXT: $vgpr5 = COPY [[COPY10]] |
| ; GFX1200-NEXT: $vgpr6 = COPY [[COPY11]] |
| ; GFX1200-NEXT: $vgpr7 = COPY [[COPY12]] |
| ; GFX1200-NEXT: $vgpr8 = COPY [[COPY13]] |
| ; GFX1200-NEXT: $vgpr9 = COPY [[COPY14]] |
| ; GFX1200-NEXT: $vgpr10 = COPY [[COPY15]] |
| ; GFX1200-NEXT: $vgpr11 = COPY [[COPY16]] |
| ; GFX1200-NEXT: $vgpr12 = COPY [[COPY17]] |
| ; GFX1200-NEXT: $vgpr13 = COPY [[COPY18]] |
| ; GFX1200-NEXT: $vgpr14 = COPY [[COPY19]] |
| ; GFX1200-NEXT: $vgpr15 = COPY [[COPY20]] |
| ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 |
| ; |
| ; GFX1250-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset |
| ; GFX1250: bb.1 (%ir-block.0): |
| ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX1250-NEXT: {{ $}} |
| ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 16, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) |
| ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN2:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 32, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) |
| ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN3:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 48, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) |
| ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_512_align2 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN3]], %subreg.sub12_sub13_sub14_sub15 |
| ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 |
| ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 |
| ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 |
| ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 |
| ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 |
| ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 |
| ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 |
| ; GFX1250-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 |
| ; GFX1250-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8 |
| ; GFX1250-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9 |
| ; GFX1250-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10 |
| ; GFX1250-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11 |
| ; GFX1250-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12 |
| ; GFX1250-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13 |
| ; GFX1250-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14 |
| ; GFX1250-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15 |
| ; GFX1250-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX1250-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX1250-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX1250-NEXT: $vgpr3 = COPY [[COPY8]] |
| ; GFX1250-NEXT: $vgpr4 = COPY [[COPY9]] |
| ; GFX1250-NEXT: $vgpr5 = COPY [[COPY10]] |
| ; GFX1250-NEXT: $vgpr6 = COPY [[COPY11]] |
| ; GFX1250-NEXT: $vgpr7 = COPY [[COPY12]] |
| ; GFX1250-NEXT: $vgpr8 = COPY [[COPY13]] |
| ; GFX1250-NEXT: $vgpr9 = COPY [[COPY14]] |
| ; GFX1250-NEXT: $vgpr10 = COPY [[COPY15]] |
| ; GFX1250-NEXT: $vgpr11 = COPY [[COPY16]] |
| ; GFX1250-NEXT: $vgpr12 = COPY [[COPY17]] |
| ; GFX1250-NEXT: $vgpr13 = COPY [[COPY18]] |
| ; GFX1250-NEXT: $vgpr14 = COPY [[COPY19]] |
| ; GFX1250-NEXT: $vgpr15 = COPY [[COPY20]] |
| ; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 |
| %val = call <16 x float> @llvm.amdgcn.ptr.s.buffer.load.v16f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 |
| ret <16 x float> %val |
| } |
| |
| define amdgpu_ps float @ptr_s_buffer_load_f32_vgpr_offset_add_4092(ptr addrspace(8) inreg %rsrc, i32 %soffset.base) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4092 |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX6-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4092, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4092 |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX7-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4092, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX7-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4092 |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX8-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4092, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX8-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 |
| ; |
| ; GFX1200-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4092 |
| ; GFX1200: bb.1 (%ir-block.0): |
| ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX1200-NEXT: {{ $}} |
| ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4092, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1200-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] |
| ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 |
| ; |
| ; GFX1250-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4092 |
| ; GFX1250: bb.1 (%ir-block.0): |
| ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX1250-NEXT: {{ $}} |
| ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4092 |
| ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] |
| ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY4]], [[COPY5]], 0, implicit $exec |
| ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] |
| ; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 |
| %soffset = add i32 %soffset.base, 4092 |
| %val = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 |
| ret float %val |
| } |
| |
| define amdgpu_ps float @ptr_s_buffer_load_f32_vgpr_offset_add_4095(ptr addrspace(8) inreg %rsrc, i32 %soffset.base) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4095 |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX6-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4095, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4095 |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX7-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4095, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX7-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4095 |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX8-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4095, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX8-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 |
| ; |
| ; GFX1200-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4095 |
| ; GFX1200: bb.1 (%ir-block.0): |
| ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX1200-NEXT: {{ $}} |
| ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4095, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1200-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] |
| ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 |
| ; |
| ; GFX1250-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4095 |
| ; GFX1250: bb.1 (%ir-block.0): |
| ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX1250-NEXT: {{ $}} |
| ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095 |
| ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] |
| ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY4]], [[COPY5]], 0, implicit $exec |
| ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] |
| ; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 |
| %soffset = add i32 %soffset.base, 4095 |
| %val = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 |
| ret float %val |
| } |
| |
| define amdgpu_ps float @ptr_s_buffer_load_f32_vgpr_offset_add_4092_nuw(ptr addrspace(8) inreg %rsrc, i32 %soffset.base) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4092_nuw |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX6-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4092, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4092_nuw |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX7-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4092, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX7-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4092_nuw |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX8-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4092, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX8-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 |
| ; |
| ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4092_nuw |
| ; GFX1200_1250: bb.1 (%ir-block.0): |
| ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX1200_1250-NEXT: {{ $}} |
| ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200_1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4092, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1200_1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] |
| ; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 |
| %soffset = add nuw i32 %soffset.base, 4092 |
| %val = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 |
| ret float %val |
| } |
| |
| define amdgpu_ps float @ptr_s_buffer_load_f32_vgpr_offset_add_4096(ptr addrspace(8) inreg %rsrc, i32 %soffset.base) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4096 |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4096 |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX7-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4096 |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1 |
| ; GFX8-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4095, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX8-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 |
| ; |
| ; GFX1200-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4096 |
| ; GFX1200: bb.1 (%ir-block.0): |
| ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX1200-NEXT: {{ $}} |
| ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4096, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1200-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] |
| ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 |
| ; |
| ; GFX1250-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4096 |
| ; GFX1250: bb.1 (%ir-block.0): |
| ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX1250-NEXT: {{ $}} |
| ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096 |
| ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] |
| ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY4]], [[COPY5]], 0, implicit $exec |
| ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] |
| ; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 |
| %soffset = add i32 %soffset.base, 4096 |
| %val = call float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 |
| ret float %val |
| } |
| |
| ; Make sure the base offset is added to each split load. |
| define amdgpu_ps <8 x float> @ptr_s_buffer_load_v8f32_vgpr_offset_add_4064(ptr addrspace(8) inreg %rsrc, i32 %soffset.base) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4064 |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) |
| ; GFX6-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7 |
| ; GFX6-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 |
| ; GFX6-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 |
| ; GFX6-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 |
| ; GFX6-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 |
| ; GFX6-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 |
| ; GFX6-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 |
| ; GFX6-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 |
| ; GFX6-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 |
| ; GFX6-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX6-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX6-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX6-NEXT: $vgpr3 = COPY [[COPY8]] |
| ; GFX6-NEXT: $vgpr4 = COPY [[COPY9]] |
| ; GFX6-NEXT: $vgpr5 = COPY [[COPY10]] |
| ; GFX6-NEXT: $vgpr6 = COPY [[COPY11]] |
| ; GFX6-NEXT: $vgpr7 = COPY [[COPY12]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4064 |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) |
| ; GFX7-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7 |
| ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 |
| ; GFX7-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 |
| ; GFX7-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 |
| ; GFX7-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 |
| ; GFX7-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 |
| ; GFX7-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 |
| ; GFX7-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 |
| ; GFX7-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 |
| ; GFX7-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX7-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX7-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX7-NEXT: $vgpr3 = COPY [[COPY8]] |
| ; GFX7-NEXT: $vgpr4 = COPY [[COPY9]] |
| ; GFX7-NEXT: $vgpr5 = COPY [[COPY10]] |
| ; GFX7-NEXT: $vgpr6 = COPY [[COPY11]] |
| ; GFX7-NEXT: $vgpr7 = COPY [[COPY12]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4064 |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) |
| ; GFX8-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7 |
| ; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 |
| ; GFX8-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 |
| ; GFX8-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 |
| ; GFX8-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 |
| ; GFX8-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 |
| ; GFX8-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 |
| ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 |
| ; GFX8-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 |
| ; GFX8-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX8-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX8-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX8-NEXT: $vgpr3 = COPY [[COPY8]] |
| ; GFX8-NEXT: $vgpr4 = COPY [[COPY9]] |
| ; GFX8-NEXT: $vgpr5 = COPY [[COPY10]] |
| ; GFX8-NEXT: $vgpr6 = COPY [[COPY11]] |
| ; GFX8-NEXT: $vgpr7 = COPY [[COPY12]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 |
| ; |
| ; GFX1200-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4064 |
| ; GFX1200: bb.1 (%ir-block.0): |
| ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX1200-NEXT: {{ $}} |
| ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4064, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4080, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) |
| ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1]], %subreg.sub4_sub5_sub6_sub7 |
| ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 |
| ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 |
| ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 |
| ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 |
| ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 |
| ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 |
| ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 |
| ; GFX1200-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 |
| ; GFX1200-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX1200-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX1200-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX1200-NEXT: $vgpr3 = COPY [[COPY8]] |
| ; GFX1200-NEXT: $vgpr4 = COPY [[COPY9]] |
| ; GFX1200-NEXT: $vgpr5 = COPY [[COPY10]] |
| ; GFX1200-NEXT: $vgpr6 = COPY [[COPY11]] |
| ; GFX1200-NEXT: $vgpr7 = COPY [[COPY12]] |
| ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 |
| ; |
| ; GFX1250-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4064 |
| ; GFX1250: bb.1 (%ir-block.0): |
| ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX1250-NEXT: {{ $}} |
| ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4064 |
| ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] |
| ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY4]], [[COPY5]], 0, implicit $exec |
| ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 16, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) |
| ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_256_align2 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1]], %subreg.sub4_sub5_sub6_sub7 |
| ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 |
| ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 |
| ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 |
| ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 |
| ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 |
| ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 |
| ; GFX1250-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 |
| ; GFX1250-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 |
| ; GFX1250-NEXT: $vgpr0 = COPY [[COPY6]] |
| ; GFX1250-NEXT: $vgpr1 = COPY [[COPY7]] |
| ; GFX1250-NEXT: $vgpr2 = COPY [[COPY8]] |
| ; GFX1250-NEXT: $vgpr3 = COPY [[COPY9]] |
| ; GFX1250-NEXT: $vgpr4 = COPY [[COPY10]] |
| ; GFX1250-NEXT: $vgpr5 = COPY [[COPY11]] |
| ; GFX1250-NEXT: $vgpr6 = COPY [[COPY12]] |
| ; GFX1250-NEXT: $vgpr7 = COPY [[COPY13]] |
| ; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 |
| %soffset = add i32 %soffset.base, 4064 |
| %val = call <8 x float> @llvm.amdgcn.ptr.s.buffer.load.v8f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 |
| ret <8 x float> %val |
| } |
| |
| ; Make sure the maximum offset isn't exeeded when splitting this |
| define amdgpu_ps <8 x float> @ptr_s_buffer_load_v8f32_vgpr_offset_add_4068(ptr addrspace(8) inreg %rsrc, i32 %soffset.base) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4068 |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4068, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4084, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) |
| ; GFX6-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7 |
| ; GFX6-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 |
| ; GFX6-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 |
| ; GFX6-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 |
| ; GFX6-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 |
| ; GFX6-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 |
| ; GFX6-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 |
| ; GFX6-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 |
| ; GFX6-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 |
| ; GFX6-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX6-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX6-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX6-NEXT: $vgpr3 = COPY [[COPY8]] |
| ; GFX6-NEXT: $vgpr4 = COPY [[COPY9]] |
| ; GFX6-NEXT: $vgpr5 = COPY [[COPY10]] |
| ; GFX6-NEXT: $vgpr6 = COPY [[COPY11]] |
| ; GFX6-NEXT: $vgpr7 = COPY [[COPY12]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4068 |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4068, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4084, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) |
| ; GFX7-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7 |
| ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 |
| ; GFX7-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 |
| ; GFX7-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 |
| ; GFX7-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 |
| ; GFX7-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 |
| ; GFX7-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 |
| ; GFX7-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 |
| ; GFX7-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 |
| ; GFX7-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX7-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX7-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX7-NEXT: $vgpr3 = COPY [[COPY8]] |
| ; GFX7-NEXT: $vgpr4 = COPY [[COPY9]] |
| ; GFX7-NEXT: $vgpr5 = COPY [[COPY10]] |
| ; GFX7-NEXT: $vgpr6 = COPY [[COPY11]] |
| ; GFX7-NEXT: $vgpr7 = COPY [[COPY12]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4068 |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4068, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4084, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) |
| ; GFX8-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7 |
| ; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 |
| ; GFX8-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 |
| ; GFX8-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 |
| ; GFX8-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 |
| ; GFX8-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 |
| ; GFX8-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 |
| ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 |
| ; GFX8-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 |
| ; GFX8-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX8-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX8-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX8-NEXT: $vgpr3 = COPY [[COPY8]] |
| ; GFX8-NEXT: $vgpr4 = COPY [[COPY9]] |
| ; GFX8-NEXT: $vgpr5 = COPY [[COPY10]] |
| ; GFX8-NEXT: $vgpr6 = COPY [[COPY11]] |
| ; GFX8-NEXT: $vgpr7 = COPY [[COPY12]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 |
| ; |
| ; GFX1200-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4068 |
| ; GFX1200: bb.1 (%ir-block.0): |
| ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX1200-NEXT: {{ $}} |
| ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4068, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4084, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) |
| ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1]], %subreg.sub4_sub5_sub6_sub7 |
| ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 |
| ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 |
| ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 |
| ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 |
| ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 |
| ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 |
| ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 |
| ; GFX1200-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 |
| ; GFX1200-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX1200-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX1200-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX1200-NEXT: $vgpr3 = COPY [[COPY8]] |
| ; GFX1200-NEXT: $vgpr4 = COPY [[COPY9]] |
| ; GFX1200-NEXT: $vgpr5 = COPY [[COPY10]] |
| ; GFX1200-NEXT: $vgpr6 = COPY [[COPY11]] |
| ; GFX1200-NEXT: $vgpr7 = COPY [[COPY12]] |
| ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 |
| ; |
| ; GFX1250-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4068 |
| ; GFX1250: bb.1 (%ir-block.0): |
| ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX1250-NEXT: {{ $}} |
| ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4068 |
| ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] |
| ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY4]], [[COPY5]], 0, implicit $exec |
| ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 16, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) |
| ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_256_align2 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1]], %subreg.sub4_sub5_sub6_sub7 |
| ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 |
| ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 |
| ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 |
| ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 |
| ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 |
| ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 |
| ; GFX1250-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 |
| ; GFX1250-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 |
| ; GFX1250-NEXT: $vgpr0 = COPY [[COPY6]] |
| ; GFX1250-NEXT: $vgpr1 = COPY [[COPY7]] |
| ; GFX1250-NEXT: $vgpr2 = COPY [[COPY8]] |
| ; GFX1250-NEXT: $vgpr3 = COPY [[COPY9]] |
| ; GFX1250-NEXT: $vgpr4 = COPY [[COPY10]] |
| ; GFX1250-NEXT: $vgpr5 = COPY [[COPY11]] |
| ; GFX1250-NEXT: $vgpr6 = COPY [[COPY12]] |
| ; GFX1250-NEXT: $vgpr7 = COPY [[COPY13]] |
| ; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 |
| %soffset = add i32 %soffset.base, 4068 |
| %val = call <8 x float> @llvm.amdgcn.ptr.s.buffer.load.v8f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 |
| ret <8 x float> %val |
| } |
| |
| define amdgpu_ps <16 x float> @ptr_s_buffer_load_v16f32_vgpr_offset_add_4032(ptr addrspace(8) inreg %rsrc, i32 %soffset.base) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4032 |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4032, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4048, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) |
| ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) |
| ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) |
| ; GFX6-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15 |
| ; GFX6-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 |
| ; GFX6-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 |
| ; GFX6-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 |
| ; GFX6-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 |
| ; GFX6-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 |
| ; GFX6-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 |
| ; GFX6-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 |
| ; GFX6-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 |
| ; GFX6-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8 |
| ; GFX6-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9 |
| ; GFX6-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10 |
| ; GFX6-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11 |
| ; GFX6-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12 |
| ; GFX6-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13 |
| ; GFX6-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14 |
| ; GFX6-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15 |
| ; GFX6-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX6-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX6-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX6-NEXT: $vgpr3 = COPY [[COPY8]] |
| ; GFX6-NEXT: $vgpr4 = COPY [[COPY9]] |
| ; GFX6-NEXT: $vgpr5 = COPY [[COPY10]] |
| ; GFX6-NEXT: $vgpr6 = COPY [[COPY11]] |
| ; GFX6-NEXT: $vgpr7 = COPY [[COPY12]] |
| ; GFX6-NEXT: $vgpr8 = COPY [[COPY13]] |
| ; GFX6-NEXT: $vgpr9 = COPY [[COPY14]] |
| ; GFX6-NEXT: $vgpr10 = COPY [[COPY15]] |
| ; GFX6-NEXT: $vgpr11 = COPY [[COPY16]] |
| ; GFX6-NEXT: $vgpr12 = COPY [[COPY17]] |
| ; GFX6-NEXT: $vgpr13 = COPY [[COPY18]] |
| ; GFX6-NEXT: $vgpr14 = COPY [[COPY19]] |
| ; GFX6-NEXT: $vgpr15 = COPY [[COPY20]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4032 |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4032, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4048, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) |
| ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) |
| ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) |
| ; GFX7-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15 |
| ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 |
| ; GFX7-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 |
| ; GFX7-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 |
| ; GFX7-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 |
| ; GFX7-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 |
| ; GFX7-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 |
| ; GFX7-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 |
| ; GFX7-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 |
| ; GFX7-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8 |
| ; GFX7-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9 |
| ; GFX7-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10 |
| ; GFX7-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11 |
| ; GFX7-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12 |
| ; GFX7-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13 |
| ; GFX7-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14 |
| ; GFX7-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15 |
| ; GFX7-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX7-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX7-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX7-NEXT: $vgpr3 = COPY [[COPY8]] |
| ; GFX7-NEXT: $vgpr4 = COPY [[COPY9]] |
| ; GFX7-NEXT: $vgpr5 = COPY [[COPY10]] |
| ; GFX7-NEXT: $vgpr6 = COPY [[COPY11]] |
| ; GFX7-NEXT: $vgpr7 = COPY [[COPY12]] |
| ; GFX7-NEXT: $vgpr8 = COPY [[COPY13]] |
| ; GFX7-NEXT: $vgpr9 = COPY [[COPY14]] |
| ; GFX7-NEXT: $vgpr10 = COPY [[COPY15]] |
| ; GFX7-NEXT: $vgpr11 = COPY [[COPY16]] |
| ; GFX7-NEXT: $vgpr12 = COPY [[COPY17]] |
| ; GFX7-NEXT: $vgpr13 = COPY [[COPY18]] |
| ; GFX7-NEXT: $vgpr14 = COPY [[COPY19]] |
| ; GFX7-NEXT: $vgpr15 = COPY [[COPY20]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4032 |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4032, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4048, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) |
| ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) |
| ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) |
| ; GFX8-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15 |
| ; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 |
| ; GFX8-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 |
| ; GFX8-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 |
| ; GFX8-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 |
| ; GFX8-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 |
| ; GFX8-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 |
| ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 |
| ; GFX8-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 |
| ; GFX8-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8 |
| ; GFX8-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9 |
| ; GFX8-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10 |
| ; GFX8-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11 |
| ; GFX8-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12 |
| ; GFX8-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13 |
| ; GFX8-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14 |
| ; GFX8-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15 |
| ; GFX8-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX8-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX8-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX8-NEXT: $vgpr3 = COPY [[COPY8]] |
| ; GFX8-NEXT: $vgpr4 = COPY [[COPY9]] |
| ; GFX8-NEXT: $vgpr5 = COPY [[COPY10]] |
| ; GFX8-NEXT: $vgpr6 = COPY [[COPY11]] |
| ; GFX8-NEXT: $vgpr7 = COPY [[COPY12]] |
| ; GFX8-NEXT: $vgpr8 = COPY [[COPY13]] |
| ; GFX8-NEXT: $vgpr9 = COPY [[COPY14]] |
| ; GFX8-NEXT: $vgpr10 = COPY [[COPY15]] |
| ; GFX8-NEXT: $vgpr11 = COPY [[COPY16]] |
| ; GFX8-NEXT: $vgpr12 = COPY [[COPY17]] |
| ; GFX8-NEXT: $vgpr13 = COPY [[COPY18]] |
| ; GFX8-NEXT: $vgpr14 = COPY [[COPY19]] |
| ; GFX8-NEXT: $vgpr15 = COPY [[COPY20]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 |
| ; |
| ; GFX1200-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4032 |
| ; GFX1200: bb.1 (%ir-block.0): |
| ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX1200-NEXT: {{ $}} |
| ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4032, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4048, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) |
| ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4064, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) |
| ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4080, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) |
| ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN3]], %subreg.sub12_sub13_sub14_sub15 |
| ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 |
| ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 |
| ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 |
| ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 |
| ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 |
| ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 |
| ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 |
| ; GFX1200-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 |
| ; GFX1200-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8 |
| ; GFX1200-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9 |
| ; GFX1200-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10 |
| ; GFX1200-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11 |
| ; GFX1200-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12 |
| ; GFX1200-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13 |
| ; GFX1200-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14 |
| ; GFX1200-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15 |
| ; GFX1200-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX1200-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX1200-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX1200-NEXT: $vgpr3 = COPY [[COPY8]] |
| ; GFX1200-NEXT: $vgpr4 = COPY [[COPY9]] |
| ; GFX1200-NEXT: $vgpr5 = COPY [[COPY10]] |
| ; GFX1200-NEXT: $vgpr6 = COPY [[COPY11]] |
| ; GFX1200-NEXT: $vgpr7 = COPY [[COPY12]] |
| ; GFX1200-NEXT: $vgpr8 = COPY [[COPY13]] |
| ; GFX1200-NEXT: $vgpr9 = COPY [[COPY14]] |
| ; GFX1200-NEXT: $vgpr10 = COPY [[COPY15]] |
| ; GFX1200-NEXT: $vgpr11 = COPY [[COPY16]] |
| ; GFX1200-NEXT: $vgpr12 = COPY [[COPY17]] |
| ; GFX1200-NEXT: $vgpr13 = COPY [[COPY18]] |
| ; GFX1200-NEXT: $vgpr14 = COPY [[COPY19]] |
| ; GFX1200-NEXT: $vgpr15 = COPY [[COPY20]] |
| ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 |
| ; |
| ; GFX1250-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4032 |
| ; GFX1250: bb.1 (%ir-block.0): |
| ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX1250-NEXT: {{ $}} |
| ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4032 |
| ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] |
| ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY4]], [[COPY5]], 0, implicit $exec |
| ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 16, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) |
| ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN2:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 32, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) |
| ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN3:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 48, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) |
| ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_512_align2 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN3]], %subreg.sub12_sub13_sub14_sub15 |
| ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 |
| ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 |
| ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 |
| ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 |
| ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 |
| ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 |
| ; GFX1250-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 |
| ; GFX1250-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 |
| ; GFX1250-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8 |
| ; GFX1250-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9 |
| ; GFX1250-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10 |
| ; GFX1250-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11 |
| ; GFX1250-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12 |
| ; GFX1250-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13 |
| ; GFX1250-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14 |
| ; GFX1250-NEXT: [[COPY21:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15 |
| ; GFX1250-NEXT: $vgpr0 = COPY [[COPY6]] |
| ; GFX1250-NEXT: $vgpr1 = COPY [[COPY7]] |
| ; GFX1250-NEXT: $vgpr2 = COPY [[COPY8]] |
| ; GFX1250-NEXT: $vgpr3 = COPY [[COPY9]] |
| ; GFX1250-NEXT: $vgpr4 = COPY [[COPY10]] |
| ; GFX1250-NEXT: $vgpr5 = COPY [[COPY11]] |
| ; GFX1250-NEXT: $vgpr6 = COPY [[COPY12]] |
| ; GFX1250-NEXT: $vgpr7 = COPY [[COPY13]] |
| ; GFX1250-NEXT: $vgpr8 = COPY [[COPY14]] |
| ; GFX1250-NEXT: $vgpr9 = COPY [[COPY15]] |
| ; GFX1250-NEXT: $vgpr10 = COPY [[COPY16]] |
| ; GFX1250-NEXT: $vgpr11 = COPY [[COPY17]] |
| ; GFX1250-NEXT: $vgpr12 = COPY [[COPY18]] |
| ; GFX1250-NEXT: $vgpr13 = COPY [[COPY19]] |
| ; GFX1250-NEXT: $vgpr14 = COPY [[COPY20]] |
| ; GFX1250-NEXT: $vgpr15 = COPY [[COPY21]] |
| ; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 |
| %soffset = add i32 %soffset.base, 4032 |
| %val = call <16 x float> @llvm.amdgcn.ptr.s.buffer.load.v16f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 |
| ret <16 x float> %val |
| } |
| |
| define amdgpu_ps <16 x float> @ptr_s_buffer_load_v16f32_vgpr_offset_add_4036(ptr addrspace(8) inreg %rsrc, i32 %soffset.base) { |
| ; GFX6-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4036 |
| ; GFX6: bb.1 (%ir-block.0): |
| ; GFX6-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX6-NEXT: {{ $}} |
| ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX6-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX6-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4036, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4052, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) |
| ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4068, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) |
| ; GFX6-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4084, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) |
| ; GFX6-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15 |
| ; GFX6-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 |
| ; GFX6-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 |
| ; GFX6-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 |
| ; GFX6-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 |
| ; GFX6-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 |
| ; GFX6-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 |
| ; GFX6-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 |
| ; GFX6-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 |
| ; GFX6-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8 |
| ; GFX6-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9 |
| ; GFX6-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10 |
| ; GFX6-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11 |
| ; GFX6-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12 |
| ; GFX6-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13 |
| ; GFX6-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14 |
| ; GFX6-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15 |
| ; GFX6-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX6-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX6-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX6-NEXT: $vgpr3 = COPY [[COPY8]] |
| ; GFX6-NEXT: $vgpr4 = COPY [[COPY9]] |
| ; GFX6-NEXT: $vgpr5 = COPY [[COPY10]] |
| ; GFX6-NEXT: $vgpr6 = COPY [[COPY11]] |
| ; GFX6-NEXT: $vgpr7 = COPY [[COPY12]] |
| ; GFX6-NEXT: $vgpr8 = COPY [[COPY13]] |
| ; GFX6-NEXT: $vgpr9 = COPY [[COPY14]] |
| ; GFX6-NEXT: $vgpr10 = COPY [[COPY15]] |
| ; GFX6-NEXT: $vgpr11 = COPY [[COPY16]] |
| ; GFX6-NEXT: $vgpr12 = COPY [[COPY17]] |
| ; GFX6-NEXT: $vgpr13 = COPY [[COPY18]] |
| ; GFX6-NEXT: $vgpr14 = COPY [[COPY19]] |
| ; GFX6-NEXT: $vgpr15 = COPY [[COPY20]] |
| ; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 |
| ; |
| ; GFX7-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4036 |
| ; GFX7: bb.1 (%ir-block.0): |
| ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX7-NEXT: {{ $}} |
| ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX7-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX7-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX7-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4036, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4052, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) |
| ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4068, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) |
| ; GFX7-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4084, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) |
| ; GFX7-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15 |
| ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 |
| ; GFX7-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 |
| ; GFX7-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 |
| ; GFX7-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 |
| ; GFX7-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 |
| ; GFX7-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 |
| ; GFX7-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 |
| ; GFX7-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 |
| ; GFX7-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8 |
| ; GFX7-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9 |
| ; GFX7-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10 |
| ; GFX7-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11 |
| ; GFX7-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12 |
| ; GFX7-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13 |
| ; GFX7-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14 |
| ; GFX7-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15 |
| ; GFX7-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX7-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX7-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX7-NEXT: $vgpr3 = COPY [[COPY8]] |
| ; GFX7-NEXT: $vgpr4 = COPY [[COPY9]] |
| ; GFX7-NEXT: $vgpr5 = COPY [[COPY10]] |
| ; GFX7-NEXT: $vgpr6 = COPY [[COPY11]] |
| ; GFX7-NEXT: $vgpr7 = COPY [[COPY12]] |
| ; GFX7-NEXT: $vgpr8 = COPY [[COPY13]] |
| ; GFX7-NEXT: $vgpr9 = COPY [[COPY14]] |
| ; GFX7-NEXT: $vgpr10 = COPY [[COPY15]] |
| ; GFX7-NEXT: $vgpr11 = COPY [[COPY16]] |
| ; GFX7-NEXT: $vgpr12 = COPY [[COPY17]] |
| ; GFX7-NEXT: $vgpr13 = COPY [[COPY18]] |
| ; GFX7-NEXT: $vgpr14 = COPY [[COPY19]] |
| ; GFX7-NEXT: $vgpr15 = COPY [[COPY20]] |
| ; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 |
| ; |
| ; GFX8-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4036 |
| ; GFX8: bb.1 (%ir-block.0): |
| ; GFX8-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX8-NEXT: {{ $}} |
| ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX8-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX8-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4036, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4052, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) |
| ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4068, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) |
| ; GFX8-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4084, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) |
| ; GFX8-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15 |
| ; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 |
| ; GFX8-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 |
| ; GFX8-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 |
| ; GFX8-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 |
| ; GFX8-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 |
| ; GFX8-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 |
| ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 |
| ; GFX8-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 |
| ; GFX8-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8 |
| ; GFX8-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9 |
| ; GFX8-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10 |
| ; GFX8-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11 |
| ; GFX8-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12 |
| ; GFX8-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13 |
| ; GFX8-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14 |
| ; GFX8-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15 |
| ; GFX8-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX8-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX8-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX8-NEXT: $vgpr3 = COPY [[COPY8]] |
| ; GFX8-NEXT: $vgpr4 = COPY [[COPY9]] |
| ; GFX8-NEXT: $vgpr5 = COPY [[COPY10]] |
| ; GFX8-NEXT: $vgpr6 = COPY [[COPY11]] |
| ; GFX8-NEXT: $vgpr7 = COPY [[COPY12]] |
| ; GFX8-NEXT: $vgpr8 = COPY [[COPY13]] |
| ; GFX8-NEXT: $vgpr9 = COPY [[COPY14]] |
| ; GFX8-NEXT: $vgpr10 = COPY [[COPY15]] |
| ; GFX8-NEXT: $vgpr11 = COPY [[COPY16]] |
| ; GFX8-NEXT: $vgpr12 = COPY [[COPY17]] |
| ; GFX8-NEXT: $vgpr13 = COPY [[COPY18]] |
| ; GFX8-NEXT: $vgpr14 = COPY [[COPY19]] |
| ; GFX8-NEXT: $vgpr15 = COPY [[COPY20]] |
| ; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 |
| ; |
| ; GFX1200-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4036 |
| ; GFX1200: bb.1 (%ir-block.0): |
| ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX1200-NEXT: {{ $}} |
| ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4036, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4052, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) |
| ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4068, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) |
| ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4084, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) |
| ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN3]], %subreg.sub12_sub13_sub14_sub15 |
| ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 |
| ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 |
| ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 |
| ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 |
| ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 |
| ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 |
| ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 |
| ; GFX1200-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 |
| ; GFX1200-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8 |
| ; GFX1200-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9 |
| ; GFX1200-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10 |
| ; GFX1200-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11 |
| ; GFX1200-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12 |
| ; GFX1200-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13 |
| ; GFX1200-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14 |
| ; GFX1200-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15 |
| ; GFX1200-NEXT: $vgpr0 = COPY [[COPY5]] |
| ; GFX1200-NEXT: $vgpr1 = COPY [[COPY6]] |
| ; GFX1200-NEXT: $vgpr2 = COPY [[COPY7]] |
| ; GFX1200-NEXT: $vgpr3 = COPY [[COPY8]] |
| ; GFX1200-NEXT: $vgpr4 = COPY [[COPY9]] |
| ; GFX1200-NEXT: $vgpr5 = COPY [[COPY10]] |
| ; GFX1200-NEXT: $vgpr6 = COPY [[COPY11]] |
| ; GFX1200-NEXT: $vgpr7 = COPY [[COPY12]] |
| ; GFX1200-NEXT: $vgpr8 = COPY [[COPY13]] |
| ; GFX1200-NEXT: $vgpr9 = COPY [[COPY14]] |
| ; GFX1200-NEXT: $vgpr10 = COPY [[COPY15]] |
| ; GFX1200-NEXT: $vgpr11 = COPY [[COPY16]] |
| ; GFX1200-NEXT: $vgpr12 = COPY [[COPY17]] |
| ; GFX1200-NEXT: $vgpr13 = COPY [[COPY18]] |
| ; GFX1200-NEXT: $vgpr14 = COPY [[COPY19]] |
| ; GFX1200-NEXT: $vgpr15 = COPY [[COPY20]] |
| ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 |
| ; |
| ; GFX1250-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4036 |
| ; GFX1250: bb.1 (%ir-block.0): |
| ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 |
| ; GFX1250-NEXT: {{ $}} |
| ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4036 |
| ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] |
| ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY4]], [[COPY5]], 0, implicit $exec |
| ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) |
| ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 16, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 16, align 1, addrspace 8) |
| ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN2:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 32, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 32, align 1, addrspace 8) |
| ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN3:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 48, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc + 48, align 1, addrspace 8) |
| ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_512_align2 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN3]], %subreg.sub12_sub13_sub14_sub15 |
| ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0 |
| ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 |
| ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2 |
| ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3 |
| ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4 |
| ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5 |
| ; GFX1250-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6 |
| ; GFX1250-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7 |
| ; GFX1250-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8 |
| ; GFX1250-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9 |
| ; GFX1250-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10 |
| ; GFX1250-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11 |
| ; GFX1250-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12 |
| ; GFX1250-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13 |
| ; GFX1250-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14 |
| ; GFX1250-NEXT: [[COPY21:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15 |
| ; GFX1250-NEXT: $vgpr0 = COPY [[COPY6]] |
| ; GFX1250-NEXT: $vgpr1 = COPY [[COPY7]] |
| ; GFX1250-NEXT: $vgpr2 = COPY [[COPY8]] |
| ; GFX1250-NEXT: $vgpr3 = COPY [[COPY9]] |
| ; GFX1250-NEXT: $vgpr4 = COPY [[COPY10]] |
| ; GFX1250-NEXT: $vgpr5 = COPY [[COPY11]] |
| ; GFX1250-NEXT: $vgpr6 = COPY [[COPY12]] |
| ; GFX1250-NEXT: $vgpr7 = COPY [[COPY13]] |
| ; GFX1250-NEXT: $vgpr8 = COPY [[COPY14]] |
| ; GFX1250-NEXT: $vgpr9 = COPY [[COPY15]] |
| ; GFX1250-NEXT: $vgpr10 = COPY [[COPY16]] |
| ; GFX1250-NEXT: $vgpr11 = COPY [[COPY17]] |
| ; GFX1250-NEXT: $vgpr12 = COPY [[COPY18]] |
| ; GFX1250-NEXT: $vgpr13 = COPY [[COPY19]] |
| ; GFX1250-NEXT: $vgpr14 = COPY [[COPY20]] |
| ; GFX1250-NEXT: $vgpr15 = COPY [[COPY21]] |
| ; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 |
| %soffset = add i32 %soffset.base, 4036 |
| %val = call <16 x float> @llvm.amdgcn.ptr.s.buffer.load.v16f32(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0 |
| ret <16 x float> %val |
| } |
| |
| ; Waterfall loop due to resource being VGPR |
| |
| declare i32 @llvm.amdgcn.ptr.s.buffer.load.i32(ptr addrspace(8), i32, i32 immarg) |
| declare <2 x i32> @llvm.amdgcn.ptr.s.buffer.load.v2i32(ptr addrspace(8), i32, i32 immarg) |
| declare <3 x i32> @llvm.amdgcn.ptr.s.buffer.load.v3i32(ptr addrspace(8), i32, i32 immarg) |
| declare <4 x i32> @llvm.amdgcn.ptr.s.buffer.load.v4i32(ptr addrspace(8), i32, i32 immarg) |
| declare <8 x i32> @llvm.amdgcn.ptr.s.buffer.load.v8i32(ptr addrspace(8), i32, i32 immarg) |
| declare <16 x i32> @llvm.amdgcn.ptr.s.buffer.load.v16i32(ptr addrspace(8), i32, i32 immarg) |
| |
| declare float @llvm.amdgcn.ptr.s.buffer.load.f32(ptr addrspace(8), i32, i32 immarg) |
| declare <2 x float> @llvm.amdgcn.ptr.s.buffer.load.v2f32(ptr addrspace(8), i32, i32 immarg) |
| declare <3 x float> @llvm.amdgcn.ptr.s.buffer.load.v3f32(ptr addrspace(8), i32, i32 immarg) |
| declare <4 x float> @llvm.amdgcn.ptr.s.buffer.load.v4f32(ptr addrspace(8), i32, i32 immarg) |
| declare <8 x float> @llvm.amdgcn.ptr.s.buffer.load.v8f32(ptr addrspace(8), i32, i32 immarg) |
| declare <16 x float> @llvm.amdgcn.ptr.s.buffer.load.v16f32(ptr addrspace(8), i32, i32 immarg) |
| |
| declare i256 @llvm.amdgcn.ptr.s.buffer.load.i256(ptr addrspace(8), i32, i32 immarg) |
| declare i512 @llvm.amdgcn.ptr.s.buffer.load.i512(ptr addrspace(8), i32, i32 immarg) |
| |
| declare <16 x i16> @llvm.amdgcn.ptr.s.buffer.load.v16i16(ptr addrspace(8), i32, i32 immarg) |
| declare <32 x i16> @llvm.amdgcn.ptr.s.buffer.load.v32i16(ptr addrspace(8), i32, i32 immarg) |
| |
| declare <4 x i64> @llvm.amdgcn.ptr.s.buffer.load.v4i64(ptr addrspace(8), i32, i32 immarg) |
| declare <8 x i64> @llvm.amdgcn.ptr.s.buffer.load.v8i64(ptr addrspace(8), i32, i32 immarg) |
| |
| !0 = !{} |
