| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc -global-isel -amdgpu-scalarize-global-loads=false -enable-misched=0 -mtriple=amdgpu7.04 < %s | FileCheck --check-prefix=CI %s |
| ; RUN: llc -global-isel -amdgpu-scalarize-global-loads=false -enable-misched=0 -mtriple=amdgpu8.02 < %s | FileCheck --check-prefix=VI %s |
| |
| define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 { |
| ; CI-LABEL: frem_f16: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 |
| ; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_load_dword s2, s[2:3], 0x0 |
| ; CI-NEXT: s_load_dword s3, s[4:5], 0x2 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_cvt_f32_f16_e64 v1, |s2| |
| ; CI-NEXT: v_cvt_f32_f16_e64 v0, |s3| |
| ; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v1, v0 |
| ; CI-NEXT: s_or_b64 s[4:5], vcc, vcc |
| ; CI-NEXT: s_mov_b32 s5, 1 |
| ; CI-NEXT: ; implicit-def: $sgpr4 |
| ; CI-NEXT: s_cbranch_scc0 .LBB0_2 |
| ; CI-NEXT: ; %bb.1: ; %frem.else |
| ; CI-NEXT: s_and_b32 s4, s2, 0xffff8000 |
| ; CI-NEXT: v_cmp_eq_f32_e32 vcc, v1, v0 |
| ; CI-NEXT: s_or_b64 s[6:7], vcc, vcc |
| ; CI-NEXT: s_mov_b32 s5, 0 |
| ; CI-NEXT: s_cselect_b32 s4, s4, s2 |
| ; CI-NEXT: .LBB0_2: ; %Flow18 |
| ; CI-NEXT: s_xor_b32 s5, s5, 1 |
| ; CI-NEXT: s_cmp_lg_u32 s5, 0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB0_8 |
| ; CI-NEXT: ; %bb.3: ; %frem.compute |
| ; CI-NEXT: v_frexp_mant_f32_e32 v2, v1 |
| ; CI-NEXT: v_frexp_exp_i32_f32_e32 v1, v1 |
| ; CI-NEXT: v_readfirstlane_b32 s7, v1 |
| ; CI-NEXT: v_ldexp_f32_e64 v1, v2, 11 |
| ; CI-NEXT: v_readfirstlane_b32 s6, v1 |
| ; CI-NEXT: v_frexp_mant_f32_e32 v1, v0 |
| ; CI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s8, v0 |
| ; CI-NEXT: v_ldexp_f32_e64 v0, v1, 1 |
| ; CI-NEXT: v_div_scale_f32 v1, s[10:11], v0, v0, 1.0 |
| ; CI-NEXT: s_add_i32 s5, s7, -1 |
| ; CI-NEXT: s_add_i32 s4, s8, -1 |
| ; CI-NEXT: s_sub_i32 s5, s5, s4 |
| ; CI-NEXT: v_div_scale_f32 v2, s[10:11], 1.0, v0, 1.0 |
| ; CI-NEXT: s_or_b64 s[10:11], s[10:11], s[10:11] |
| ; CI-NEXT: v_rcp_f32_e32 v3, v1 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 |
| ; CI-NEXT: v_fma_f32 v3, v4, v3, v3 |
| ; CI-NEXT: v_mul_f32_e32 v4, v2, v3 |
| ; CI-NEXT: v_fma_f32 v5, -v1, v4, v2 |
| ; CI-NEXT: v_fma_f32 v4, v5, v3, v4 |
| ; CI-NEXT: v_fma_f32 v1, -v1, v4, v2 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; CI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 |
| ; CI-NEXT: s_cmp_le_i32 s5, 11 |
| ; CI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB0_6 |
| ; CI-NEXT: ; %bb.4: ; %frem.loop_body.preheader |
| ; CI-NEXT: s_add_i32 s7, s7, 11 |
| ; CI-NEXT: s_sub_i32 s5, s7, s8 |
| ; CI-NEXT: .LBB0_5: ; %frem.loop_body |
| ; CI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; CI-NEXT: v_mul_f32_e32 v2, s6, v1 |
| ; CI-NEXT: v_rndne_f32_e32 v2, v2 |
| ; CI-NEXT: v_fma_f32 v2, -v2, v0, s6 |
| ; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 |
| ; CI-NEXT: v_readfirstlane_b32 s7, v2 |
| ; CI-NEXT: s_or_b64 s[8:9], vcc, vcc |
| ; CI-NEXT: v_add_f32_e32 v2, v2, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s8, v2 |
| ; CI-NEXT: s_cselect_b32 s7, s8, s7 |
| ; CI-NEXT: v_ldexp_f32_e64 v2, s7, 11 |
| ; CI-NEXT: v_readfirstlane_b32 s8, v2 |
| ; CI-NEXT: s_add_i32 s5, s5, -11 |
| ; CI-NEXT: s_cmp_gt_i32 s5, 11 |
| ; CI-NEXT: s_mov_b32 s7, s6 |
| ; CI-NEXT: s_mov_b32 s6, s8 |
| ; CI-NEXT: s_cbranch_scc1 .LBB0_5 |
| ; CI-NEXT: s_branch .LBB0_7 |
| ; CI-NEXT: .LBB0_6: |
| ; CI-NEXT: s_mov_b32 s7, s6 |
| ; CI-NEXT: .LBB0_7: ; %frem.loop_exit |
| ; CI-NEXT: s_add_i32 s5, s5, -10 |
| ; CI-NEXT: v_mov_b32_e32 v2, s5 |
| ; CI-NEXT: v_ldexp_f32_e32 v2, s7, v2 |
| ; CI-NEXT: v_mul_f32_e32 v1, v2, v1 |
| ; CI-NEXT: v_rndne_f32_e32 v1, v1 |
| ; CI-NEXT: v_fma_f32 v1, -v1, v0, v2 |
| ; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1 |
| ; CI-NEXT: s_or_b64 s[6:7], vcc, vcc |
| ; CI-NEXT: v_add_f32_e32 v0, v1, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s5, v1 |
| ; CI-NEXT: v_readfirstlane_b32 s6, v0 |
| ; CI-NEXT: s_cselect_b32 s5, s6, s5 |
| ; CI-NEXT: v_mov_b32_e32 v0, s4 |
| ; CI-NEXT: v_ldexp_f32_e32 v0, s5, v0 |
| ; CI-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; CI-NEXT: s_and_b32 s5, s2, 0xffff8000 |
| ; CI-NEXT: v_readfirstlane_b32 s4, v0 |
| ; CI-NEXT: s_and_b32 s4, s4, 0x7fff |
| ; CI-NEXT: s_or_b32 s4, s4, s5 |
| ; CI-NEXT: .LBB0_8: ; %Flow19 |
| ; CI-NEXT: v_cvt_f32_f16_e32 v0, s3 |
| ; CI-NEXT: v_mov_b32_e32 v1, 0x7f800000 |
| ; CI-NEXT: v_cmp_nlg_f32_e32 vcc, 0, v0 |
| ; CI-NEXT: v_cvt_f32_f16_e64 v0, |s2| |
| ; CI-NEXT: s_or_b64 s[6:7], vcc, vcc |
| ; CI-NEXT: s_cselect_b32 s5, 1, 0 |
| ; CI-NEXT: v_cmp_nge_f32_e32 vcc, v0, v1 |
| ; CI-NEXT: s_or_b64 s[2:3], vcc, vcc |
| ; CI-NEXT: s_cselect_b32 s2, 1, 0 |
| ; CI-NEXT: s_cmp_lg_u32 s5, 0 |
| ; CI-NEXT: s_cselect_b32 s3, 0x7e00, s4 |
| ; CI-NEXT: s_cmp_lg_u32 s2, 0 |
| ; CI-NEXT: s_cselect_b32 s2, s3, 0x7e00 |
| ; CI-NEXT: v_mov_b32_e32 v0, s2 |
| ; CI-NEXT: s_mov_b32 s2, -1 |
| ; CI-NEXT: s_mov_b32 s3, 0xf000 |
| ; CI-NEXT: buffer_store_short v0, off, s[0:3], 0 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: frem_f16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_load_dword s2, s[2:3], 0x0 |
| ; VI-NEXT: s_load_dword s3, s[4:5], 0x8 |
| ; VI-NEXT: s_mov_b32 s5, 1 |
| ; VI-NEXT: ; implicit-def: $sgpr4 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_cvt_f32_f16_e64 v1, |s2| |
| ; VI-NEXT: v_cvt_f32_f16_e64 v0, |s3| |
| ; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v1, v0 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: s_cbranch_scc0 .LBB0_2 |
| ; VI-NEXT: ; %bb.1: ; %frem.else |
| ; VI-NEXT: s_and_b32 s4, s2, 0xffff8000 |
| ; VI-NEXT: v_cmp_eq_f32_e32 vcc, v1, v0 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: s_mov_b32 s5, 0 |
| ; VI-NEXT: s_cselect_b32 s4, s4, s2 |
| ; VI-NEXT: .LBB0_2: ; %Flow18 |
| ; VI-NEXT: s_xor_b32 s5, s5, 1 |
| ; VI-NEXT: s_cmp_lg_u32 s5, 0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB0_8 |
| ; VI-NEXT: ; %bb.3: ; %frem.compute |
| ; VI-NEXT: v_frexp_mant_f32_e32 v2, v1 |
| ; VI-NEXT: v_frexp_exp_i32_f32_e32 v1, v1 |
| ; VI-NEXT: v_readfirstlane_b32 s7, v1 |
| ; VI-NEXT: v_ldexp_f32 v1, v2, 11 |
| ; VI-NEXT: v_readfirstlane_b32 s6, v1 |
| ; VI-NEXT: v_frexp_mant_f32_e32 v1, v0 |
| ; VI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s8, v0 |
| ; VI-NEXT: v_ldexp_f32 v0, v1, 1 |
| ; VI-NEXT: v_div_scale_f32 v1, s[10:11], v0, v0, 1.0 |
| ; VI-NEXT: s_add_i32 s5, s7, -1 |
| ; VI-NEXT: s_add_i32 s4, s8, -1 |
| ; VI-NEXT: s_sub_i32 s5, s5, s4 |
| ; VI-NEXT: v_div_scale_f32 v2, s[10:11], 1.0, v0, 1.0 |
| ; VI-NEXT: s_cmp_lg_u64 s[10:11], 0 |
| ; VI-NEXT: v_rcp_f32_e32 v3, v1 |
| ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 |
| ; VI-NEXT: v_fma_f32 v3, v4, v3, v3 |
| ; VI-NEXT: v_mul_f32_e32 v4, v2, v3 |
| ; VI-NEXT: v_fma_f32 v5, -v1, v4, v2 |
| ; VI-NEXT: v_fma_f32 v4, v5, v3, v4 |
| ; VI-NEXT: v_fma_f32 v1, -v1, v4, v2 |
| ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; VI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 |
| ; VI-NEXT: s_cmp_le_i32 s5, 11 |
| ; VI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB0_6 |
| ; VI-NEXT: ; %bb.4: ; %frem.loop_body.preheader |
| ; VI-NEXT: s_add_i32 s7, s7, 11 |
| ; VI-NEXT: s_sub_i32 s5, s7, s8 |
| ; VI-NEXT: .LBB0_5: ; %frem.loop_body |
| ; VI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; VI-NEXT: v_mul_f32_e32 v2, s6, v1 |
| ; VI-NEXT: v_rndne_f32_e32 v2, v2 |
| ; VI-NEXT: v_fma_f32 v2, -v2, v0, s6 |
| ; VI-NEXT: v_readfirstlane_b32 s7, v2 |
| ; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 |
| ; VI-NEXT: v_add_f32_e32 v2, v2, v0 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s8, v2 |
| ; VI-NEXT: s_cselect_b32 s7, s8, s7 |
| ; VI-NEXT: v_ldexp_f32 v2, s7, 11 |
| ; VI-NEXT: v_readfirstlane_b32 s8, v2 |
| ; VI-NEXT: s_add_i32 s5, s5, -11 |
| ; VI-NEXT: s_cmp_gt_i32 s5, 11 |
| ; VI-NEXT: s_mov_b32 s7, s6 |
| ; VI-NEXT: s_mov_b32 s6, s8 |
| ; VI-NEXT: s_cbranch_scc1 .LBB0_5 |
| ; VI-NEXT: s_branch .LBB0_7 |
| ; VI-NEXT: .LBB0_6: |
| ; VI-NEXT: s_mov_b32 s7, s6 |
| ; VI-NEXT: .LBB0_7: ; %frem.loop_exit |
| ; VI-NEXT: s_add_i32 s5, s5, -10 |
| ; VI-NEXT: v_mov_b32_e32 v2, s5 |
| ; VI-NEXT: v_ldexp_f32 v2, s7, v2 |
| ; VI-NEXT: v_mul_f32_e32 v1, v2, v1 |
| ; VI-NEXT: v_rndne_f32_e32 v1, v1 |
| ; VI-NEXT: v_fma_f32 v1, -v1, v0, v2 |
| ; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1 |
| ; VI-NEXT: v_add_f32_e32 v0, v1, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s5, v1 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s6, v0 |
| ; VI-NEXT: s_cselect_b32 s5, s6, s5 |
| ; VI-NEXT: v_mov_b32_e32 v0, s4 |
| ; VI-NEXT: v_ldexp_f32 v0, s5, v0 |
| ; VI-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; VI-NEXT: s_and_b32 s5, s2, 0xffff8000 |
| ; VI-NEXT: v_readfirstlane_b32 s4, v0 |
| ; VI-NEXT: s_and_b32 s4, s4, 0x7fff |
| ; VI-NEXT: s_or_b32 s4, s4, s5 |
| ; VI-NEXT: .LBB0_8: ; %Flow19 |
| ; VI-NEXT: v_cmp_nlg_f16_e64 s[6:7], s3, 0 |
| ; VI-NEXT: v_mov_b32_e32 v0, 0x7c00 |
| ; VI-NEXT: s_cmp_lg_u64 s[6:7], 0 |
| ; VI-NEXT: v_cmp_nge_f16_e64 s[2:3], |s2|, v0 |
| ; VI-NEXT: s_cselect_b32 s5, 1, 0 |
| ; VI-NEXT: s_cmp_lg_u64 s[2:3], 0 |
| ; VI-NEXT: s_cselect_b32 s2, 1, 0 |
| ; VI-NEXT: s_cmp_lg_u32 s5, 0 |
| ; VI-NEXT: s_cselect_b32 s3, 0x7e00, s4 |
| ; VI-NEXT: s_cmp_lg_u32 s2, 0 |
| ; VI-NEXT: s_cselect_b32 s2, s3, 0x7e00 |
| ; VI-NEXT: v_mov_b32_e32 v2, s2 |
| ; VI-NEXT: v_mov_b32_e32 v0, s0 |
| ; VI-NEXT: v_mov_b32_e32 v1, s1 |
| ; VI-NEXT: flat_store_short v[0:1], v2 |
| ; VI-NEXT: s_endpgm |
| %gep2 = getelementptr half, ptr addrspace(1) %in2, i32 4 |
| %r0 = load half, ptr addrspace(1) %in1, align 4 |
| %r1 = load half, ptr addrspace(1) %gep2, align 4 |
| %r2 = frem half %r0, %r1 |
| store half %r2, ptr addrspace(1) %out, align 4 |
| ret void |
| } |
| |
| define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 { |
| ; CI-LABEL: fast_frem_f16: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 |
| ; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_load_dword s6, s[2:3], 0x0 |
| ; CI-NEXT: s_load_dword s4, s[4:5], 0x2 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_cvt_f32_f16_e32 v0, s6 |
| ; CI-NEXT: v_cvt_f32_f16_e32 v1, s4 |
| ; CI-NEXT: v_div_scale_f32 v2, s[2:3], v1, v1, v0 |
| ; CI-NEXT: v_div_scale_f32 v3, s[2:3], v0, v1, v0 |
| ; CI-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3] |
| ; CI-NEXT: v_rcp_f32_e32 v4, v2 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; CI-NEXT: v_fma_f32 v5, -v2, v4, 1.0 |
| ; CI-NEXT: v_fma_f32 v4, v5, v4, v4 |
| ; CI-NEXT: v_mul_f32_e32 v5, v3, v4 |
| ; CI-NEXT: v_fma_f32 v6, -v2, v5, v3 |
| ; CI-NEXT: v_fma_f32 v5, v6, v4, v5 |
| ; CI-NEXT: v_fma_f32 v2, -v2, v5, v3 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; CI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; CI-NEXT: v_div_fmas_f32 v2, v2, v4, v5 |
| ; CI-NEXT: s_mov_b32 s2, -1 |
| ; CI-NEXT: s_mov_b32 s3, 0xf000 |
| ; CI-NEXT: v_div_fixup_f32 v0, v2, v1, v0 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 |
| ; CI-NEXT: v_cvt_f16_f32_e64 v0, -v0 |
| ; CI-NEXT: v_cvt_f32_f16_e32 v1, s4 |
| ; CI-NEXT: v_cvt_f32_f16_e32 v2, s6 |
| ; CI-NEXT: v_cvt_f32_f16_e32 v0, v0 |
| ; CI-NEXT: v_trunc_f32_e32 v0, v0 |
| ; CI-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; CI-NEXT: v_cvt_f32_f16_e32 v0, v0 |
| ; CI-NEXT: v_fma_f32 v0, v0, v1, v2 |
| ; CI-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; CI-NEXT: buffer_store_short v0, off, s[0:3], 0 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: fast_frem_f16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_load_dword s2, s[2:3], 0x0 |
| ; VI-NEXT: s_load_dword s3, s[4:5], 0x8 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_cvt_f32_f16_e32 v0, s2 |
| ; VI-NEXT: v_cvt_f32_f16_e32 v2, s3 |
| ; VI-NEXT: v_mov_b32_e32 v1, s3 |
| ; VI-NEXT: v_rcp_f32_e32 v3, v2 |
| ; VI-NEXT: v_mul_f32_e32 v4, v0, v3 |
| ; VI-NEXT: v_mad_f32 v5, -v2, v4, v0 |
| ; VI-NEXT: v_mac_f32_e32 v4, v5, v3 |
| ; VI-NEXT: v_mad_f32 v0, -v2, v4, v0 |
| ; VI-NEXT: v_mul_f32_e32 v0, v0, v3 |
| ; VI-NEXT: v_readfirstlane_b32 s3, v0 |
| ; VI-NEXT: s_and_b32 s3, s3, 0xff800000 |
| ; VI-NEXT: v_add_f32_e32 v0, s3, v4 |
| ; VI-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; VI-NEXT: v_div_fixup_f16 v0, v0, v1, s2 |
| ; VI-NEXT: v_trunc_f16_e32 v0, v0 |
| ; VI-NEXT: v_fma_f16 v2, -v0, v1, s2 |
| ; VI-NEXT: v_mov_b32_e32 v0, s0 |
| ; VI-NEXT: v_mov_b32_e32 v1, s1 |
| ; VI-NEXT: flat_store_short v[0:1], v2 |
| ; VI-NEXT: s_endpgm |
| %gep2 = getelementptr half, ptr addrspace(1) %in2, i32 4 |
| %r0 = load half, ptr addrspace(1) %in1, align 4 |
| %r1 = load half, ptr addrspace(1) %gep2, align 4 |
| %r2 = frem fast half %r0, %r1 |
| store half %r2, ptr addrspace(1) %out, align 4 |
| ret void |
| } |
| |
| define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #1 { |
| ; CI-LABEL: unsafe_frem_f16: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 |
| ; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_load_dword s6, s[2:3], 0x0 |
| ; CI-NEXT: s_load_dword s4, s[4:5], 0x2 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_cvt_f32_f16_e32 v0, s6 |
| ; CI-NEXT: v_cvt_f32_f16_e32 v1, s4 |
| ; CI-NEXT: v_div_scale_f32 v2, s[2:3], v1, v1, v0 |
| ; CI-NEXT: v_div_scale_f32 v3, s[2:3], v0, v1, v0 |
| ; CI-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3] |
| ; CI-NEXT: v_rcp_f32_e32 v4, v2 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; CI-NEXT: v_fma_f32 v5, -v2, v4, 1.0 |
| ; CI-NEXT: v_fma_f32 v4, v5, v4, v4 |
| ; CI-NEXT: v_mul_f32_e32 v5, v3, v4 |
| ; CI-NEXT: v_fma_f32 v6, -v2, v5, v3 |
| ; CI-NEXT: v_fma_f32 v5, v6, v4, v5 |
| ; CI-NEXT: v_fma_f32 v2, -v2, v5, v3 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; CI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; CI-NEXT: v_div_fmas_f32 v2, v2, v4, v5 |
| ; CI-NEXT: s_mov_b32 s2, -1 |
| ; CI-NEXT: s_mov_b32 s3, 0xf000 |
| ; CI-NEXT: v_div_fixup_f32 v0, v2, v1, v0 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 |
| ; CI-NEXT: v_cvt_f16_f32_e64 v0, -v0 |
| ; CI-NEXT: v_cvt_f32_f16_e32 v1, s4 |
| ; CI-NEXT: v_cvt_f32_f16_e32 v2, s6 |
| ; CI-NEXT: v_cvt_f32_f16_e32 v0, v0 |
| ; CI-NEXT: v_trunc_f32_e32 v0, v0 |
| ; CI-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; CI-NEXT: v_cvt_f32_f16_e32 v0, v0 |
| ; CI-NEXT: v_fma_f32 v0, v0, v1, v2 |
| ; CI-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; CI-NEXT: buffer_store_short v0, off, s[0:3], 0 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: unsafe_frem_f16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_load_dword s2, s[2:3], 0x0 |
| ; VI-NEXT: s_load_dword s3, s[4:5], 0x8 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_cvt_f32_f16_e32 v0, s2 |
| ; VI-NEXT: v_cvt_f32_f16_e32 v2, s3 |
| ; VI-NEXT: v_mov_b32_e32 v1, s3 |
| ; VI-NEXT: v_rcp_f32_e32 v3, v2 |
| ; VI-NEXT: v_mul_f32_e32 v4, v0, v3 |
| ; VI-NEXT: v_mad_f32 v5, -v2, v4, v0 |
| ; VI-NEXT: v_mac_f32_e32 v4, v5, v3 |
| ; VI-NEXT: v_mad_f32 v0, -v2, v4, v0 |
| ; VI-NEXT: v_mul_f32_e32 v0, v0, v3 |
| ; VI-NEXT: v_readfirstlane_b32 s3, v0 |
| ; VI-NEXT: s_and_b32 s3, s3, 0xff800000 |
| ; VI-NEXT: v_add_f32_e32 v0, s3, v4 |
| ; VI-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; VI-NEXT: v_div_fixup_f16 v0, v0, v1, s2 |
| ; VI-NEXT: v_trunc_f16_e32 v0, v0 |
| ; VI-NEXT: v_fma_f16 v2, -v0, v1, s2 |
| ; VI-NEXT: v_mov_b32_e32 v0, s0 |
| ; VI-NEXT: v_mov_b32_e32 v1, s1 |
| ; VI-NEXT: flat_store_short v[0:1], v2 |
| ; VI-NEXT: s_endpgm |
| %gep2 = getelementptr half, ptr addrspace(1) %in2, i32 4 |
| %r0 = load half, ptr addrspace(1) %in1, align 4 |
| %r1 = load half, ptr addrspace(1) %gep2, align 4 |
| %r2 = frem afn half %r0, %r1 |
| store half %r2, ptr addrspace(1) %out, align 4 |
| ret void |
| } |
| |
| define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 { |
| ; CI-LABEL: frem_f32: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 |
| ; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_load_dword s2, s[2:3], 0x0 |
| ; CI-NEXT: s_load_dword s3, s[4:5], 0x4 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_mov_b32_e32 v0, s3 |
| ; CI-NEXT: v_cmp_ngt_f32_e64 s[4:5], |s2|, |v0| |
| ; CI-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5] |
| ; CI-NEXT: s_mov_b32 s5, 1 |
| ; CI-NEXT: ; implicit-def: $sgpr4 |
| ; CI-NEXT: s_cbranch_scc0 .LBB3_2 |
| ; CI-NEXT: ; %bb.1: ; %frem.else |
| ; CI-NEXT: v_mov_b32_e32 v0, s3 |
| ; CI-NEXT: s_and_b32 s4, s2, 0x80000000 |
| ; CI-NEXT: v_cmp_eq_f32_e64 s[6:7], |s2|, |v0| |
| ; CI-NEXT: s_or_b64 s[6:7], s[6:7], s[6:7] |
| ; CI-NEXT: s_mov_b32 s5, 0 |
| ; CI-NEXT: s_cselect_b32 s4, s4, s2 |
| ; CI-NEXT: .LBB3_2: ; %Flow16 |
| ; CI-NEXT: s_xor_b32 s5, s5, 1 |
| ; CI-NEXT: s_cmp_lg_u32 s5, 0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB3_8 |
| ; CI-NEXT: ; %bb.3: ; %frem.compute |
| ; CI-NEXT: v_frexp_mant_f32_e64 v0, |s2| |
| ; CI-NEXT: v_ldexp_f32_e64 v0, v0, 12 |
| ; CI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s2| |
| ; CI-NEXT: v_readfirstlane_b32 s6, v0 |
| ; CI-NEXT: v_frexp_mant_f32_e64 v0, |s3| |
| ; CI-NEXT: v_readfirstlane_b32 s7, v1 |
| ; CI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s3| |
| ; CI-NEXT: v_ldexp_f32_e64 v0, v0, 1 |
| ; CI-NEXT: v_readfirstlane_b32 s8, v1 |
| ; CI-NEXT: v_div_scale_f32 v1, s[10:11], v0, v0, 1.0 |
| ; CI-NEXT: s_add_i32 s5, s7, -1 |
| ; CI-NEXT: s_add_i32 s4, s8, -1 |
| ; CI-NEXT: s_sub_i32 s5, s5, s4 |
| ; CI-NEXT: v_div_scale_f32 v2, s[10:11], 1.0, v0, 1.0 |
| ; CI-NEXT: s_or_b64 s[10:11], s[10:11], s[10:11] |
| ; CI-NEXT: v_rcp_f32_e32 v3, v1 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 |
| ; CI-NEXT: v_fma_f32 v3, v4, v3, v3 |
| ; CI-NEXT: v_mul_f32_e32 v4, v2, v3 |
| ; CI-NEXT: v_fma_f32 v5, -v1, v4, v2 |
| ; CI-NEXT: v_fma_f32 v4, v5, v3, v4 |
| ; CI-NEXT: v_fma_f32 v1, -v1, v4, v2 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; CI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 |
| ; CI-NEXT: s_cmp_le_i32 s5, 12 |
| ; CI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB3_6 |
| ; CI-NEXT: ; %bb.4: ; %frem.loop_body.preheader |
| ; CI-NEXT: s_add_i32 s7, s7, 12 |
| ; CI-NEXT: s_sub_i32 s5, s7, s8 |
| ; CI-NEXT: .LBB3_5: ; %frem.loop_body |
| ; CI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; CI-NEXT: v_mul_f32_e32 v2, s6, v1 |
| ; CI-NEXT: v_rndne_f32_e32 v2, v2 |
| ; CI-NEXT: v_fma_f32 v2, -v2, v0, s6 |
| ; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 |
| ; CI-NEXT: v_readfirstlane_b32 s7, v2 |
| ; CI-NEXT: s_or_b64 s[8:9], vcc, vcc |
| ; CI-NEXT: v_add_f32_e32 v2, v2, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s8, v2 |
| ; CI-NEXT: s_cselect_b32 s7, s8, s7 |
| ; CI-NEXT: v_ldexp_f32_e64 v2, s7, 12 |
| ; CI-NEXT: v_readfirstlane_b32 s8, v2 |
| ; CI-NEXT: s_add_i32 s5, s5, -12 |
| ; CI-NEXT: s_cmp_gt_i32 s5, 12 |
| ; CI-NEXT: s_mov_b32 s7, s6 |
| ; CI-NEXT: s_mov_b32 s6, s8 |
| ; CI-NEXT: s_cbranch_scc1 .LBB3_5 |
| ; CI-NEXT: s_branch .LBB3_7 |
| ; CI-NEXT: .LBB3_6: |
| ; CI-NEXT: s_mov_b32 s7, s6 |
| ; CI-NEXT: .LBB3_7: ; %frem.loop_exit |
| ; CI-NEXT: s_add_i32 s5, s5, -11 |
| ; CI-NEXT: v_mov_b32_e32 v2, s5 |
| ; CI-NEXT: v_ldexp_f32_e32 v2, s7, v2 |
| ; CI-NEXT: v_mul_f32_e32 v1, v2, v1 |
| ; CI-NEXT: v_rndne_f32_e32 v1, v1 |
| ; CI-NEXT: v_fma_f32 v1, -v1, v0, v2 |
| ; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1 |
| ; CI-NEXT: s_or_b64 s[6:7], vcc, vcc |
| ; CI-NEXT: v_add_f32_e32 v0, v1, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s5, v1 |
| ; CI-NEXT: v_readfirstlane_b32 s6, v0 |
| ; CI-NEXT: s_cselect_b32 s5, s6, s5 |
| ; CI-NEXT: v_mov_b32_e32 v0, s4 |
| ; CI-NEXT: v_ldexp_f32_e32 v0, s5, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s4, v0 |
| ; CI-NEXT: s_bitset0_b32 s4, 31 |
| ; CI-NEXT: s_and_b32 s5, s2, 0x80000000 |
| ; CI-NEXT: s_or_b32 s4, s4, s5 |
| ; CI-NEXT: .LBB3_8: ; %Flow17 |
| ; CI-NEXT: v_cmp_nlg_f32_e64 s[6:7], s3, 0 |
| ; CI-NEXT: v_mov_b32_e32 v0, 0x7f800000 |
| ; CI-NEXT: s_or_b64 s[6:7], s[6:7], s[6:7] |
| ; CI-NEXT: v_cmp_nge_f32_e64 s[2:3], |s2|, v0 |
| ; CI-NEXT: s_cselect_b32 s4, 0x7fc00000, s4 |
| ; CI-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3] |
| ; CI-NEXT: s_cselect_b32 s2, s4, 0x7fc00000 |
| ; CI-NEXT: v_mov_b32_e32 v0, s2 |
| ; CI-NEXT: s_mov_b32 s2, -1 |
| ; CI-NEXT: s_mov_b32 s3, 0xf000 |
| ; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: frem_f32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_load_dword s2, s[2:3], 0x0 |
| ; VI-NEXT: s_load_dword s3, s[4:5], 0x10 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v0, s3 |
| ; VI-NEXT: v_cmp_ngt_f32_e64 s[4:5], |s2|, |v0| |
| ; VI-NEXT: s_cmp_lg_u64 s[4:5], 0 |
| ; VI-NEXT: s_mov_b32 s5, 1 |
| ; VI-NEXT: ; implicit-def: $sgpr4 |
| ; VI-NEXT: s_cbranch_scc0 .LBB3_2 |
| ; VI-NEXT: ; %bb.1: ; %frem.else |
| ; VI-NEXT: v_mov_b32_e32 v0, s3 |
| ; VI-NEXT: s_and_b32 s4, s2, 0x80000000 |
| ; VI-NEXT: v_cmp_eq_f32_e64 s[6:7], |s2|, |v0| |
| ; VI-NEXT: s_cmp_lg_u64 s[6:7], 0 |
| ; VI-NEXT: s_mov_b32 s5, 0 |
| ; VI-NEXT: s_cselect_b32 s4, s4, s2 |
| ; VI-NEXT: .LBB3_2: ; %Flow16 |
| ; VI-NEXT: s_xor_b32 s5, s5, 1 |
| ; VI-NEXT: s_cmp_lg_u32 s5, 0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB3_8 |
| ; VI-NEXT: ; %bb.3: ; %frem.compute |
| ; VI-NEXT: v_frexp_mant_f32_e64 v0, |s2| |
| ; VI-NEXT: v_ldexp_f32 v0, v0, 12 |
| ; VI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s2| |
| ; VI-NEXT: v_readfirstlane_b32 s6, v0 |
| ; VI-NEXT: v_frexp_mant_f32_e64 v0, |s3| |
| ; VI-NEXT: v_readfirstlane_b32 s7, v1 |
| ; VI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s3| |
| ; VI-NEXT: v_ldexp_f32 v0, v0, 1 |
| ; VI-NEXT: v_readfirstlane_b32 s8, v1 |
| ; VI-NEXT: v_div_scale_f32 v1, s[10:11], v0, v0, 1.0 |
| ; VI-NEXT: s_add_i32 s5, s7, -1 |
| ; VI-NEXT: s_add_i32 s4, s8, -1 |
| ; VI-NEXT: s_sub_i32 s5, s5, s4 |
| ; VI-NEXT: v_div_scale_f32 v2, s[10:11], 1.0, v0, 1.0 |
| ; VI-NEXT: s_cmp_lg_u64 s[10:11], 0 |
| ; VI-NEXT: v_rcp_f32_e32 v3, v1 |
| ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 |
| ; VI-NEXT: v_fma_f32 v3, v4, v3, v3 |
| ; VI-NEXT: v_mul_f32_e32 v4, v2, v3 |
| ; VI-NEXT: v_fma_f32 v5, -v1, v4, v2 |
| ; VI-NEXT: v_fma_f32 v4, v5, v3, v4 |
| ; VI-NEXT: v_fma_f32 v1, -v1, v4, v2 |
| ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; VI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 |
| ; VI-NEXT: s_cmp_le_i32 s5, 12 |
| ; VI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB3_6 |
| ; VI-NEXT: ; %bb.4: ; %frem.loop_body.preheader |
| ; VI-NEXT: s_add_i32 s7, s7, 12 |
| ; VI-NEXT: s_sub_i32 s5, s7, s8 |
| ; VI-NEXT: .LBB3_5: ; %frem.loop_body |
| ; VI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; VI-NEXT: v_mul_f32_e32 v2, s6, v1 |
| ; VI-NEXT: v_rndne_f32_e32 v2, v2 |
| ; VI-NEXT: v_fma_f32 v2, -v2, v0, s6 |
| ; VI-NEXT: v_readfirstlane_b32 s7, v2 |
| ; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 |
| ; VI-NEXT: v_add_f32_e32 v2, v2, v0 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s8, v2 |
| ; VI-NEXT: s_cselect_b32 s7, s8, s7 |
| ; VI-NEXT: v_ldexp_f32 v2, s7, 12 |
| ; VI-NEXT: v_readfirstlane_b32 s8, v2 |
| ; VI-NEXT: s_add_i32 s5, s5, -12 |
| ; VI-NEXT: s_cmp_gt_i32 s5, 12 |
| ; VI-NEXT: s_mov_b32 s7, s6 |
| ; VI-NEXT: s_mov_b32 s6, s8 |
| ; VI-NEXT: s_cbranch_scc1 .LBB3_5 |
| ; VI-NEXT: s_branch .LBB3_7 |
| ; VI-NEXT: .LBB3_6: |
| ; VI-NEXT: s_mov_b32 s7, s6 |
| ; VI-NEXT: .LBB3_7: ; %frem.loop_exit |
| ; VI-NEXT: s_add_i32 s5, s5, -11 |
| ; VI-NEXT: v_mov_b32_e32 v2, s5 |
| ; VI-NEXT: v_ldexp_f32 v2, s7, v2 |
| ; VI-NEXT: v_mul_f32_e32 v1, v2, v1 |
| ; VI-NEXT: v_rndne_f32_e32 v1, v1 |
| ; VI-NEXT: v_fma_f32 v1, -v1, v0, v2 |
| ; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1 |
| ; VI-NEXT: v_add_f32_e32 v0, v1, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s5, v1 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s6, v0 |
| ; VI-NEXT: s_cselect_b32 s5, s6, s5 |
| ; VI-NEXT: v_mov_b32_e32 v0, s4 |
| ; VI-NEXT: v_ldexp_f32 v0, s5, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s4, v0 |
| ; VI-NEXT: s_bitset0_b32 s4, 31 |
| ; VI-NEXT: s_and_b32 s5, s2, 0x80000000 |
| ; VI-NEXT: s_or_b32 s4, s4, s5 |
| ; VI-NEXT: .LBB3_8: ; %Flow17 |
| ; VI-NEXT: v_cmp_nlg_f32_e64 s[6:7], s3, 0 |
| ; VI-NEXT: v_mov_b32_e32 v0, 0x7f800000 |
| ; VI-NEXT: s_cmp_lg_u64 s[6:7], 0 |
| ; VI-NEXT: v_cmp_nge_f32_e64 s[2:3], |s2|, v0 |
| ; VI-NEXT: s_cselect_b32 s4, 0x7fc00000, s4 |
| ; VI-NEXT: s_cmp_lg_u64 s[2:3], 0 |
| ; VI-NEXT: s_cselect_b32 s2, s4, 0x7fc00000 |
| ; VI-NEXT: v_mov_b32_e32 v2, s2 |
| ; VI-NEXT: v_mov_b32_e32 v0, s0 |
| ; VI-NEXT: v_mov_b32_e32 v1, s1 |
| ; VI-NEXT: flat_store_dword v[0:1], v2 |
| ; VI-NEXT: s_endpgm |
| %gep2 = getelementptr float, ptr addrspace(1) %in2, i32 4 |
| %r0 = load float, ptr addrspace(1) %in1, align 4 |
| %r1 = load float, ptr addrspace(1) %gep2, align 4 |
| %r2 = frem float %r0, %r1 |
| store float %r2, ptr addrspace(1) %out, align 4 |
| ret void |
| } |
| |
| define amdgpu_kernel void @fast_frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 { |
| ; CI-LABEL: fast_frem_f32: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 |
| ; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_load_dword s6, s[2:3], 0x0 |
| ; CI-NEXT: s_load_dword s2, s[4:5], 0x4 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_mov_b32_e32 v0, s2 |
| ; CI-NEXT: v_div_scale_f32 v1, s[2:3], v0, v0, s6 |
| ; CI-NEXT: v_div_scale_f32 v2, s[2:3], s6, v0, s6 |
| ; CI-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3] |
| ; CI-NEXT: v_rcp_f32_e32 v3, v1 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 |
| ; CI-NEXT: v_fma_f32 v3, v4, v3, v3 |
| ; CI-NEXT: v_mul_f32_e32 v4, v2, v3 |
| ; CI-NEXT: v_fma_f32 v5, -v1, v4, v2 |
| ; CI-NEXT: v_fma_f32 v4, v5, v3, v4 |
| ; CI-NEXT: v_fma_f32 v1, -v1, v4, v2 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; CI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 |
| ; CI-NEXT: s_mov_b32 s2, -1 |
| ; CI-NEXT: s_mov_b32 s3, 0xf000 |
| ; CI-NEXT: v_div_fixup_f32 v1, v1, v0, s6 |
| ; CI-NEXT: v_trunc_f32_e32 v1, v1 |
| ; CI-NEXT: v_fma_f32 v0, -v1, v0, s6 |
| ; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: fast_frem_f32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_load_dword s6, s[2:3], 0x0 |
| ; VI-NEXT: s_load_dword s2, s[4:5], 0x10 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v0, s2 |
| ; VI-NEXT: v_div_scale_f32 v1, s[2:3], v0, v0, s6 |
| ; VI-NEXT: v_div_scale_f32 v2, s[2:3], s6, v0, s6 |
| ; VI-NEXT: s_cmp_lg_u64 s[2:3], 0 |
| ; VI-NEXT: v_rcp_f32_e32 v3, v1 |
| ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 |
| ; VI-NEXT: v_fma_f32 v3, v4, v3, v3 |
| ; VI-NEXT: v_mul_f32_e32 v4, v2, v3 |
| ; VI-NEXT: v_fma_f32 v5, -v1, v4, v2 |
| ; VI-NEXT: v_fma_f32 v4, v5, v3, v4 |
| ; VI-NEXT: v_fma_f32 v1, -v1, v4, v2 |
| ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; VI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 |
| ; VI-NEXT: v_div_fixup_f32 v1, v1, v0, s6 |
| ; VI-NEXT: v_trunc_f32_e32 v1, v1 |
| ; VI-NEXT: v_fma_f32 v2, -v1, v0, s6 |
| ; VI-NEXT: v_mov_b32_e32 v0, s0 |
| ; VI-NEXT: v_mov_b32_e32 v1, s1 |
| ; VI-NEXT: flat_store_dword v[0:1], v2 |
| ; VI-NEXT: s_endpgm |
| %gep2 = getelementptr float, ptr addrspace(1) %in2, i32 4 |
| %r0 = load float, ptr addrspace(1) %in1, align 4 |
| %r1 = load float, ptr addrspace(1) %gep2, align 4 |
| %r2 = frem fast float %r0, %r1 |
| store float %r2, ptr addrspace(1) %out, align 4 |
| ret void |
| } |
| |
| define amdgpu_kernel void @unsafe_frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #1 { |
| ; CI-LABEL: unsafe_frem_f32: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 |
| ; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_load_dword s6, s[2:3], 0x0 |
| ; CI-NEXT: s_load_dword s2, s[4:5], 0x4 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_mov_b32_e32 v0, s2 |
| ; CI-NEXT: v_div_scale_f32 v1, s[2:3], v0, v0, s6 |
| ; CI-NEXT: v_div_scale_f32 v2, s[2:3], s6, v0, s6 |
| ; CI-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3] |
| ; CI-NEXT: v_rcp_f32_e32 v3, v1 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 |
| ; CI-NEXT: v_fma_f32 v3, v4, v3, v3 |
| ; CI-NEXT: v_mul_f32_e32 v4, v2, v3 |
| ; CI-NEXT: v_fma_f32 v5, -v1, v4, v2 |
| ; CI-NEXT: v_fma_f32 v4, v5, v3, v4 |
| ; CI-NEXT: v_fma_f32 v1, -v1, v4, v2 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; CI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 |
| ; CI-NEXT: s_mov_b32 s2, -1 |
| ; CI-NEXT: s_mov_b32 s3, 0xf000 |
| ; CI-NEXT: v_div_fixup_f32 v1, v1, v0, s6 |
| ; CI-NEXT: v_trunc_f32_e32 v1, v1 |
| ; CI-NEXT: v_fma_f32 v0, -v1, v0, s6 |
| ; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: unsafe_frem_f32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_load_dword s6, s[2:3], 0x0 |
| ; VI-NEXT: s_load_dword s2, s[4:5], 0x10 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v0, s2 |
| ; VI-NEXT: v_div_scale_f32 v1, s[2:3], v0, v0, s6 |
| ; VI-NEXT: v_div_scale_f32 v2, s[2:3], s6, v0, s6 |
| ; VI-NEXT: s_cmp_lg_u64 s[2:3], 0 |
| ; VI-NEXT: v_rcp_f32_e32 v3, v1 |
| ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 |
| ; VI-NEXT: v_fma_f32 v3, v4, v3, v3 |
| ; VI-NEXT: v_mul_f32_e32 v4, v2, v3 |
| ; VI-NEXT: v_fma_f32 v5, -v1, v4, v2 |
| ; VI-NEXT: v_fma_f32 v4, v5, v3, v4 |
| ; VI-NEXT: v_fma_f32 v1, -v1, v4, v2 |
| ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; VI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 |
| ; VI-NEXT: v_div_fixup_f32 v1, v1, v0, s6 |
| ; VI-NEXT: v_trunc_f32_e32 v1, v1 |
| ; VI-NEXT: v_fma_f32 v2, -v1, v0, s6 |
| ; VI-NEXT: v_mov_b32_e32 v0, s0 |
| ; VI-NEXT: v_mov_b32_e32 v1, s1 |
| ; VI-NEXT: flat_store_dword v[0:1], v2 |
| ; VI-NEXT: s_endpgm |
| %gep2 = getelementptr float, ptr addrspace(1) %in2, i32 4 |
| %r0 = load float, ptr addrspace(1) %in1, align 4 |
| %r1 = load float, ptr addrspace(1) %gep2, align 4 |
| %r2 = frem afn float %r0, %r1 |
| store float %r2, ptr addrspace(1) %out, align 4 |
| ret void |
| } |
| |
| define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 { |
| ; CI-LABEL: frem_f64: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 |
| ; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd |
| ; CI-NEXT: s_mov_b32 s9, 1 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 |
| ; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_mov_b32_e32 v0, s4 |
| ; CI-NEXT: v_mov_b32_e32 v1, s5 |
| ; CI-NEXT: v_cmp_ngt_f64_e64 s[6:7], |s[2:3]|, |v[0:1]| |
| ; CI-NEXT: s_or_b64 s[6:7], s[6:7], s[6:7] |
| ; CI-NEXT: ; implicit-def: $sgpr6_sgpr7 |
| ; CI-NEXT: s_cbranch_scc0 .LBB6_2 |
| ; CI-NEXT: ; %bb.1: ; %frem.else |
| ; CI-NEXT: v_mov_b32_e32 v0, s4 |
| ; CI-NEXT: v_mov_b32_e32 v1, s5 |
| ; CI-NEXT: v_cmp_eq_f64_e64 s[10:11], |s[2:3]|, |v[0:1]| |
| ; CI-NEXT: s_mov_b64 s[8:9], 0 |
| ; CI-NEXT: s_mov_b32 s6, 0 |
| ; CI-NEXT: s_brev_b32 s7, 1 |
| ; CI-NEXT: s_mov_b32 s9, 0 |
| ; CI-NEXT: s_and_b64 s[6:7], s[2:3], s[6:7] |
| ; CI-NEXT: s_or_b64 s[6:7], s[8:9], s[6:7] |
| ; CI-NEXT: s_or_b64 s[10:11], s[10:11], s[10:11] |
| ; CI-NEXT: s_cselect_b64 s[6:7], s[6:7], s[2:3] |
| ; CI-NEXT: .LBB6_2: ; %Flow16 |
| ; CI-NEXT: s_xor_b32 s8, s9, 1 |
| ; CI-NEXT: s_cmp_lg_u32 s8, 0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB6_8 |
| ; CI-NEXT: ; %bb.3: ; %frem.compute |
| ; CI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[2:3]| |
| ; CI-NEXT: v_frexp_exp_i32_f64_e64 v2, |s[2:3]| |
| ; CI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 26 |
| ; CI-NEXT: v_readfirstlane_b32 s8, v2 |
| ; CI-NEXT: v_frexp_exp_i32_f64_e64 v2, |s[4:5]| |
| ; CI-NEXT: s_add_i32 s11, s8, -1 |
| ; CI-NEXT: v_readfirstlane_b32 s6, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s7, v1 |
| ; CI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[4:5]| |
| ; CI-NEXT: v_readfirstlane_b32 s9, v2 |
| ; CI-NEXT: s_add_i32 s10, s9, -1 |
| ; CI-NEXT: s_sub_i32 s11, s11, s10 |
| ; CI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 1 |
| ; CI-NEXT: v_div_scale_f64 v[2:3], s[12:13], v[0:1], v[0:1], 1.0 |
| ; CI-NEXT: v_div_scale_f64 v[8:9], s[12:13], 1.0, v[0:1], 1.0 |
| ; CI-NEXT: s_or_b64 s[12:13], s[12:13], s[12:13] |
| ; CI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; CI-NEXT: s_cmp_le_i32 s11, 26 |
| ; CI-NEXT: v_rcp_f64_e32 v[4:5], v[2:3] |
| ; CI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 |
| ; CI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] |
| ; CI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 |
| ; CI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] |
| ; CI-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5] |
| ; CI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9] |
| ; CI-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7] |
| ; CI-NEXT: v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB6_6 |
| ; CI-NEXT: ; %bb.4: ; %frem.loop_body.preheader |
| ; CI-NEXT: s_add_i32 s8, s8, 26 |
| ; CI-NEXT: s_sub_i32 s11, s8, s9 |
| ; CI-NEXT: .LBB6_5: ; %frem.loop_body |
| ; CI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; CI-NEXT: v_mul_f64 v[4:5], s[6:7], v[2:3] |
| ; CI-NEXT: v_rndne_f64_e32 v[4:5], v[4:5] |
| ; CI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[0:1], s[6:7] |
| ; CI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5] |
| ; CI-NEXT: v_readfirstlane_b32 s8, v4 |
| ; CI-NEXT: v_readfirstlane_b32 s9, v5 |
| ; CI-NEXT: v_add_f64 v[4:5], v[4:5], v[0:1] |
| ; CI-NEXT: s_or_b64 s[12:13], vcc, vcc |
| ; CI-NEXT: v_readfirstlane_b32 s12, v4 |
| ; CI-NEXT: v_readfirstlane_b32 s13, v5 |
| ; CI-NEXT: s_cselect_b64 s[8:9], s[12:13], s[8:9] |
| ; CI-NEXT: v_ldexp_f64 v[4:5], s[8:9], 26 |
| ; CI-NEXT: s_sub_i32 s11, s11, 26 |
| ; CI-NEXT: s_cmp_gt_i32 s11, 26 |
| ; CI-NEXT: s_mov_b64 s[8:9], s[6:7] |
| ; CI-NEXT: v_readfirstlane_b32 s12, v4 |
| ; CI-NEXT: v_readfirstlane_b32 s13, v5 |
| ; CI-NEXT: s_mov_b64 s[6:7], s[12:13] |
| ; CI-NEXT: s_cbranch_scc1 .LBB6_5 |
| ; CI-NEXT: s_branch .LBB6_7 |
| ; CI-NEXT: .LBB6_6: |
| ; CI-NEXT: s_mov_b64 s[8:9], s[6:7] |
| ; CI-NEXT: .LBB6_7: ; %frem.loop_exit |
| ; CI-NEXT: s_sub_i32 s6, s11, 25 |
| ; CI-NEXT: v_mov_b32_e32 v4, s6 |
| ; CI-NEXT: v_ldexp_f64 v[4:5], s[8:9], v4 |
| ; CI-NEXT: v_mul_f64 v[2:3], v[4:5], v[2:3] |
| ; CI-NEXT: v_rndne_f64_e32 v[2:3], v[2:3] |
| ; CI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[0:1], v[4:5] |
| ; CI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[2:3] |
| ; CI-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1] |
| ; CI-NEXT: v_readfirstlane_b32 s6, v2 |
| ; CI-NEXT: v_readfirstlane_b32 s7, v3 |
| ; CI-NEXT: s_or_b64 s[8:9], vcc, vcc |
| ; CI-NEXT: v_readfirstlane_b32 s8, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s9, v1 |
| ; CI-NEXT: s_cselect_b64 s[6:7], s[8:9], s[6:7] |
| ; CI-NEXT: v_mov_b32_e32 v0, s10 |
| ; CI-NEXT: v_ldexp_f64 v[0:1], s[6:7], v0 |
| ; CI-NEXT: s_mov_b32 s8, 0 |
| ; CI-NEXT: s_brev_b32 s9, 1 |
| ; CI-NEXT: s_and_b64 s[8:9], s[2:3], s[8:9] |
| ; CI-NEXT: v_readfirstlane_b32 s7, v1 |
| ; CI-NEXT: v_readfirstlane_b32 s6, v0 |
| ; CI-NEXT: s_bitset0_b32 s7, 31 |
| ; CI-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9] |
| ; CI-NEXT: .LBB6_8: ; %Flow17 |
| ; CI-NEXT: v_cmp_nlg_f64_e64 s[4:5], s[4:5], 0 |
| ; CI-NEXT: v_mov_b32_e32 v0, 0 |
| ; CI-NEXT: v_mov_b32_e32 v1, 0x7ff00000 |
| ; CI-NEXT: v_cmp_nge_f64_e64 s[2:3], |s[2:3]|, v[0:1] |
| ; CI-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5] |
| ; CI-NEXT: s_mov_b32 s4, 0 |
| ; CI-NEXT: s_mov_b32 s5, 0x7ff80000 |
| ; CI-NEXT: s_cselect_b64 s[6:7], s[4:5], s[6:7] |
| ; CI-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3] |
| ; CI-NEXT: s_cselect_b64 s[2:3], s[6:7], s[4:5] |
| ; CI-NEXT: v_mov_b32_e32 v0, s2 |
| ; CI-NEXT: v_mov_b32_e32 v1, s3 |
| ; CI-NEXT: s_mov_b32 s2, -1 |
| ; CI-NEXT: s_mov_b32 s3, 0xf000 |
| ; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: frem_f64: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34 |
| ; VI-NEXT: s_mov_b32 s9, 1 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 |
| ; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v0, s4 |
| ; VI-NEXT: v_mov_b32_e32 v1, s5 |
| ; VI-NEXT: v_cmp_ngt_f64_e64 s[6:7], |s[2:3]|, |v[0:1]| |
| ; VI-NEXT: s_cmp_lg_u64 s[6:7], 0 |
| ; VI-NEXT: ; implicit-def: $sgpr6_sgpr7 |
| ; VI-NEXT: s_cbranch_scc0 .LBB6_2 |
| ; VI-NEXT: ; %bb.1: ; %frem.else |
| ; VI-NEXT: v_mov_b32_e32 v0, s4 |
| ; VI-NEXT: v_mov_b32_e32 v1, s5 |
| ; VI-NEXT: v_cmp_eq_f64_e64 s[10:11], |s[2:3]|, |v[0:1]| |
| ; VI-NEXT: s_mov_b64 s[8:9], 0 |
| ; VI-NEXT: s_mov_b32 s6, 0 |
| ; VI-NEXT: s_brev_b32 s7, 1 |
| ; VI-NEXT: s_mov_b32 s9, 0 |
| ; VI-NEXT: s_and_b64 s[6:7], s[2:3], s[6:7] |
| ; VI-NEXT: s_or_b64 s[6:7], s[8:9], s[6:7] |
| ; VI-NEXT: s_cmp_lg_u64 s[10:11], 0 |
| ; VI-NEXT: s_cselect_b64 s[6:7], s[6:7], s[2:3] |
| ; VI-NEXT: .LBB6_2: ; %Flow16 |
| ; VI-NEXT: s_xor_b32 s8, s9, 1 |
| ; VI-NEXT: s_cmp_lg_u32 s8, 0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB6_8 |
| ; VI-NEXT: ; %bb.3: ; %frem.compute |
| ; VI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[2:3]| |
| ; VI-NEXT: v_frexp_exp_i32_f64_e64 v2, |s[2:3]| |
| ; VI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 26 |
| ; VI-NEXT: v_readfirstlane_b32 s8, v2 |
| ; VI-NEXT: v_frexp_exp_i32_f64_e64 v2, |s[4:5]| |
| ; VI-NEXT: s_add_i32 s11, s8, -1 |
| ; VI-NEXT: v_readfirstlane_b32 s6, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s7, v1 |
| ; VI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[4:5]| |
| ; VI-NEXT: v_readfirstlane_b32 s9, v2 |
| ; VI-NEXT: s_add_i32 s10, s9, -1 |
| ; VI-NEXT: s_sub_i32 s11, s11, s10 |
| ; VI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 1 |
| ; VI-NEXT: v_div_scale_f64 v[2:3], s[12:13], v[0:1], v[0:1], 1.0 |
| ; VI-NEXT: v_div_scale_f64 v[8:9], s[12:13], 1.0, v[0:1], 1.0 |
| ; VI-NEXT: s_cmp_lg_u64 s[12:13], 0 |
| ; VI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; VI-NEXT: s_cmp_le_i32 s11, 26 |
| ; VI-NEXT: v_rcp_f64_e32 v[4:5], v[2:3] |
| ; VI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 |
| ; VI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] |
| ; VI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 |
| ; VI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] |
| ; VI-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5] |
| ; VI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9] |
| ; VI-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7] |
| ; VI-NEXT: v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB6_6 |
| ; VI-NEXT: ; %bb.4: ; %frem.loop_body.preheader |
| ; VI-NEXT: s_add_i32 s8, s8, 26 |
| ; VI-NEXT: s_sub_i32 s11, s8, s9 |
| ; VI-NEXT: .LBB6_5: ; %frem.loop_body |
| ; VI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; VI-NEXT: v_mul_f64 v[4:5], s[6:7], v[2:3] |
| ; VI-NEXT: v_rndne_f64_e32 v[4:5], v[4:5] |
| ; VI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[0:1], s[6:7] |
| ; VI-NEXT: v_readfirstlane_b32 s8, v4 |
| ; VI-NEXT: v_readfirstlane_b32 s9, v5 |
| ; VI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5] |
| ; VI-NEXT: v_add_f64 v[4:5], v[4:5], v[0:1] |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s12, v4 |
| ; VI-NEXT: v_readfirstlane_b32 s13, v5 |
| ; VI-NEXT: s_cselect_b64 s[8:9], s[12:13], s[8:9] |
| ; VI-NEXT: v_ldexp_f64 v[4:5], s[8:9], 26 |
| ; VI-NEXT: s_sub_i32 s11, s11, 26 |
| ; VI-NEXT: s_cmp_gt_i32 s11, 26 |
| ; VI-NEXT: s_mov_b64 s[8:9], s[6:7] |
| ; VI-NEXT: v_readfirstlane_b32 s12, v4 |
| ; VI-NEXT: v_readfirstlane_b32 s13, v5 |
| ; VI-NEXT: s_mov_b64 s[6:7], s[12:13] |
| ; VI-NEXT: s_cbranch_scc1 .LBB6_5 |
| ; VI-NEXT: s_branch .LBB6_7 |
| ; VI-NEXT: .LBB6_6: |
| ; VI-NEXT: s_mov_b64 s[8:9], s[6:7] |
| ; VI-NEXT: .LBB6_7: ; %frem.loop_exit |
| ; VI-NEXT: s_sub_i32 s6, s11, 25 |
| ; VI-NEXT: v_mov_b32_e32 v4, s6 |
| ; VI-NEXT: v_ldexp_f64 v[4:5], s[8:9], v4 |
| ; VI-NEXT: v_mul_f64 v[2:3], v[4:5], v[2:3] |
| ; VI-NEXT: v_rndne_f64_e32 v[2:3], v[2:3] |
| ; VI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[0:1], v[4:5] |
| ; VI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[2:3] |
| ; VI-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1] |
| ; VI-NEXT: v_readfirstlane_b32 s6, v2 |
| ; VI-NEXT: v_readfirstlane_b32 s7, v3 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s8, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s9, v1 |
| ; VI-NEXT: s_cselect_b64 s[6:7], s[8:9], s[6:7] |
| ; VI-NEXT: v_mov_b32_e32 v0, s10 |
| ; VI-NEXT: v_ldexp_f64 v[0:1], s[6:7], v0 |
| ; VI-NEXT: s_mov_b32 s8, 0 |
| ; VI-NEXT: s_brev_b32 s9, 1 |
| ; VI-NEXT: s_and_b64 s[8:9], s[2:3], s[8:9] |
| ; VI-NEXT: v_readfirstlane_b32 s7, v1 |
| ; VI-NEXT: v_readfirstlane_b32 s6, v0 |
| ; VI-NEXT: s_bitset0_b32 s7, 31 |
| ; VI-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9] |
| ; VI-NEXT: .LBB6_8: ; %Flow17 |
| ; VI-NEXT: v_cmp_nlg_f64_e64 s[4:5], s[4:5], 0 |
| ; VI-NEXT: v_mov_b32_e32 v0, 0 |
| ; VI-NEXT: v_mov_b32_e32 v1, 0x7ff00000 |
| ; VI-NEXT: v_cmp_nge_f64_e64 s[2:3], |s[2:3]|, v[0:1] |
| ; VI-NEXT: v_mov_b32_e32 v3, s1 |
| ; VI-NEXT: v_mov_b32_e32 v2, s0 |
| ; VI-NEXT: s_cmp_lg_u64 s[4:5], 0 |
| ; VI-NEXT: s_mov_b32 s4, 0 |
| ; VI-NEXT: s_mov_b32 s5, 0x7ff80000 |
| ; VI-NEXT: s_cselect_b64 s[6:7], s[4:5], s[6:7] |
| ; VI-NEXT: s_cmp_lg_u64 s[2:3], 0 |
| ; VI-NEXT: s_cselect_b64 s[2:3], s[6:7], s[4:5] |
| ; VI-NEXT: v_mov_b32_e32 v0, s2 |
| ; VI-NEXT: v_mov_b32_e32 v1, s3 |
| ; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] |
| ; VI-NEXT: s_endpgm |
| %r0 = load double, ptr addrspace(1) %in1, align 8 |
| %r1 = load double, ptr addrspace(1) %in2, align 8 |
| %r2 = frem double %r0, %r1 |
| store double %r2, ptr addrspace(1) %out, align 8 |
| ret void |
| } |
| |
| define amdgpu_kernel void @fast_frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 { |
| ; CI-LABEL: fast_frem_f64: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 |
| ; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 |
| ; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_mov_b32_e32 v0, s4 |
| ; CI-NEXT: v_mov_b32_e32 v1, s5 |
| ; CI-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], s[2:3] |
| ; CI-NEXT: v_div_scale_f64 v[8:9], s[4:5], s[2:3], v[0:1], s[2:3] |
| ; CI-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5] |
| ; CI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; CI-NEXT: v_rcp_f64_e32 v[4:5], v[2:3] |
| ; CI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 |
| ; CI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] |
| ; CI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 |
| ; CI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] |
| ; CI-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5] |
| ; CI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9] |
| ; CI-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7] |
| ; CI-NEXT: v_div_fixup_f64 v[2:3], v[2:3], v[0:1], s[2:3] |
| ; CI-NEXT: v_trunc_f64_e32 v[2:3], v[2:3] |
| ; CI-NEXT: v_fma_f64 v[0:1], -v[2:3], v[0:1], s[2:3] |
| ; CI-NEXT: s_mov_b32 s2, -1 |
| ; CI-NEXT: s_mov_b32 s3, 0xf000 |
| ; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: fast_frem_f64: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 |
| ; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v0, s4 |
| ; VI-NEXT: v_mov_b32_e32 v1, s5 |
| ; VI-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], s[2:3] |
| ; VI-NEXT: v_div_scale_f64 v[8:9], s[4:5], s[2:3], v[0:1], s[2:3] |
| ; VI-NEXT: s_cmp_lg_u64 s[4:5], 0 |
| ; VI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; VI-NEXT: v_rcp_f64_e32 v[4:5], v[2:3] |
| ; VI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 |
| ; VI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] |
| ; VI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 |
| ; VI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] |
| ; VI-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5] |
| ; VI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9] |
| ; VI-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7] |
| ; VI-NEXT: v_div_fixup_f64 v[2:3], v[2:3], v[0:1], s[2:3] |
| ; VI-NEXT: v_trunc_f64_e32 v[2:3], v[2:3] |
| ; VI-NEXT: v_fma_f64 v[0:1], -v[2:3], v[0:1], s[2:3] |
| ; VI-NEXT: v_mov_b32_e32 v3, s1 |
| ; VI-NEXT: v_mov_b32_e32 v2, s0 |
| ; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] |
| ; VI-NEXT: s_endpgm |
| %r0 = load double, ptr addrspace(1) %in1, align 8 |
| %r1 = load double, ptr addrspace(1) %in2, align 8 |
| %r2 = frem fast double %r0, %r1 |
| store double %r2, ptr addrspace(1) %out, align 8 |
| ret void |
| } |
| |
| define amdgpu_kernel void @unsafe_frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1, |
| ; CI-LABEL: unsafe_frem_f64: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 |
| ; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 |
| ; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_mov_b32_e32 v0, s4 |
| ; CI-NEXT: v_mov_b32_e32 v1, s5 |
| ; CI-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], s[2:3] |
| ; CI-NEXT: v_div_scale_f64 v[8:9], s[4:5], s[2:3], v[0:1], s[2:3] |
| ; CI-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5] |
| ; CI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; CI-NEXT: v_rcp_f64_e32 v[4:5], v[2:3] |
| ; CI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 |
| ; CI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] |
| ; CI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 |
| ; CI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] |
| ; CI-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5] |
| ; CI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9] |
| ; CI-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7] |
| ; CI-NEXT: v_div_fixup_f64 v[2:3], v[2:3], v[0:1], s[2:3] |
| ; CI-NEXT: v_trunc_f64_e32 v[2:3], v[2:3] |
| ; CI-NEXT: v_fma_f64 v[0:1], -v[2:3], v[0:1], s[2:3] |
| ; CI-NEXT: s_mov_b32 s2, -1 |
| ; CI-NEXT: s_mov_b32 s3, 0xf000 |
| ; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: unsafe_frem_f64: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 |
| ; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v0, s4 |
| ; VI-NEXT: v_mov_b32_e32 v1, s5 |
| ; VI-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], s[2:3] |
| ; VI-NEXT: v_div_scale_f64 v[8:9], s[4:5], s[2:3], v[0:1], s[2:3] |
| ; VI-NEXT: s_cmp_lg_u64 s[4:5], 0 |
| ; VI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; VI-NEXT: v_rcp_f64_e32 v[4:5], v[2:3] |
| ; VI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 |
| ; VI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] |
| ; VI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 |
| ; VI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] |
| ; VI-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5] |
| ; VI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9] |
| ; VI-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7] |
| ; VI-NEXT: v_div_fixup_f64 v[2:3], v[2:3], v[0:1], s[2:3] |
| ; VI-NEXT: v_trunc_f64_e32 v[2:3], v[2:3] |
| ; VI-NEXT: v_fma_f64 v[0:1], -v[2:3], v[0:1], s[2:3] |
| ; VI-NEXT: v_mov_b32_e32 v3, s1 |
| ; VI-NEXT: v_mov_b32_e32 v2, s0 |
| ; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] |
| ; VI-NEXT: s_endpgm |
| ptr addrspace(1) %in2) #1 { |
| %r0 = load double, ptr addrspace(1) %in1, align 8 |
| %r1 = load double, ptr addrspace(1) %in2, align 8 |
| %r2 = frem afn double %r0, %r1 |
| store double %r2, ptr addrspace(1) %out, align 8 |
| ret void |
| } |
| |
| define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 { |
| ; CI-LABEL: frem_v2f16: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 |
| ; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_load_dword s2, s[2:3], 0x0 |
| ; CI-NEXT: s_load_dword s3, s[4:5], 0x4 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_cvt_f32_f16_e64 v1, |s2| |
| ; CI-NEXT: v_cvt_f32_f16_e64 v0, |s3| |
| ; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v1, v0 |
| ; CI-NEXT: s_or_b64 s[4:5], vcc, vcc |
| ; CI-NEXT: s_mov_b32 s5, 1 |
| ; CI-NEXT: ; implicit-def: $sgpr4 |
| ; CI-NEXT: s_cbranch_scc0 .LBB9_2 |
| ; CI-NEXT: ; %bb.1: ; %frem.else20 |
| ; CI-NEXT: s_and_b32 s4, s2, 0xffff8000 |
| ; CI-NEXT: v_cmp_eq_f32_e32 vcc, v1, v0 |
| ; CI-NEXT: s_or_b64 s[6:7], vcc, vcc |
| ; CI-NEXT: s_mov_b32 s5, 0 |
| ; CI-NEXT: s_cselect_b32 s4, s4, s2 |
| ; CI-NEXT: .LBB9_2: ; %Flow57 |
| ; CI-NEXT: s_xor_b32 s5, s5, 1 |
| ; CI-NEXT: s_cmp_lg_u32 s5, 0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB9_8 |
| ; CI-NEXT: ; %bb.3: ; %frem.compute19 |
| ; CI-NEXT: v_frexp_mant_f32_e32 v2, v1 |
| ; CI-NEXT: v_frexp_exp_i32_f32_e32 v1, v1 |
| ; CI-NEXT: v_readfirstlane_b32 s7, v1 |
| ; CI-NEXT: v_ldexp_f32_e64 v1, v2, 11 |
| ; CI-NEXT: v_readfirstlane_b32 s6, v1 |
| ; CI-NEXT: v_frexp_mant_f32_e32 v1, v0 |
| ; CI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s8, v0 |
| ; CI-NEXT: v_ldexp_f32_e64 v0, v1, 1 |
| ; CI-NEXT: v_div_scale_f32 v1, s[10:11], v0, v0, 1.0 |
| ; CI-NEXT: s_add_i32 s5, s7, -1 |
| ; CI-NEXT: s_add_i32 s4, s8, -1 |
| ; CI-NEXT: s_sub_i32 s5, s5, s4 |
| ; CI-NEXT: v_div_scale_f32 v2, s[10:11], 1.0, v0, 1.0 |
| ; CI-NEXT: s_or_b64 s[10:11], s[10:11], s[10:11] |
| ; CI-NEXT: v_rcp_f32_e32 v3, v1 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 |
| ; CI-NEXT: v_fma_f32 v3, v4, v3, v3 |
| ; CI-NEXT: v_mul_f32_e32 v4, v2, v3 |
| ; CI-NEXT: v_fma_f32 v5, -v1, v4, v2 |
| ; CI-NEXT: v_fma_f32 v4, v5, v3, v4 |
| ; CI-NEXT: v_fma_f32 v1, -v1, v4, v2 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; CI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 |
| ; CI-NEXT: s_cmp_le_i32 s5, 11 |
| ; CI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB9_6 |
| ; CI-NEXT: ; %bb.4: ; %frem.loop_body27.preheader |
| ; CI-NEXT: s_add_i32 s7, s7, 11 |
| ; CI-NEXT: s_sub_i32 s5, s7, s8 |
| ; CI-NEXT: .LBB9_5: ; %frem.loop_body27 |
| ; CI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; CI-NEXT: v_mul_f32_e32 v2, s6, v1 |
| ; CI-NEXT: v_rndne_f32_e32 v2, v2 |
| ; CI-NEXT: v_fma_f32 v2, -v2, v0, s6 |
| ; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 |
| ; CI-NEXT: v_readfirstlane_b32 s7, v2 |
| ; CI-NEXT: s_or_b64 s[8:9], vcc, vcc |
| ; CI-NEXT: v_add_f32_e32 v2, v2, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s8, v2 |
| ; CI-NEXT: s_cselect_b32 s7, s8, s7 |
| ; CI-NEXT: v_ldexp_f32_e64 v2, s7, 11 |
| ; CI-NEXT: v_readfirstlane_b32 s8, v2 |
| ; CI-NEXT: s_add_i32 s5, s5, -11 |
| ; CI-NEXT: s_cmp_gt_i32 s5, 11 |
| ; CI-NEXT: s_mov_b32 s7, s6 |
| ; CI-NEXT: s_mov_b32 s6, s8 |
| ; CI-NEXT: s_cbranch_scc1 .LBB9_5 |
| ; CI-NEXT: s_branch .LBB9_7 |
| ; CI-NEXT: .LBB9_6: |
| ; CI-NEXT: s_mov_b32 s7, s6 |
| ; CI-NEXT: .LBB9_7: ; %frem.loop_exit28 |
| ; CI-NEXT: s_add_i32 s5, s5, -10 |
| ; CI-NEXT: v_mov_b32_e32 v2, s5 |
| ; CI-NEXT: v_ldexp_f32_e32 v2, s7, v2 |
| ; CI-NEXT: v_mul_f32_e32 v1, v2, v1 |
| ; CI-NEXT: v_rndne_f32_e32 v1, v1 |
| ; CI-NEXT: v_fma_f32 v1, -v1, v0, v2 |
| ; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1 |
| ; CI-NEXT: s_or_b64 s[6:7], vcc, vcc |
| ; CI-NEXT: v_add_f32_e32 v0, v1, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s5, v1 |
| ; CI-NEXT: v_readfirstlane_b32 s6, v0 |
| ; CI-NEXT: s_cselect_b32 s5, s6, s5 |
| ; CI-NEXT: v_mov_b32_e32 v0, s4 |
| ; CI-NEXT: v_ldexp_f32_e32 v0, s5, v0 |
| ; CI-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; CI-NEXT: s_and_b32 s5, s2, 0xffff8000 |
| ; CI-NEXT: v_readfirstlane_b32 s4, v0 |
| ; CI-NEXT: s_and_b32 s4, s4, 0x7fff |
| ; CI-NEXT: s_or_b32 s4, s4, s5 |
| ; CI-NEXT: .LBB9_8: ; %Flow58 |
| ; CI-NEXT: s_lshr_b32 s5, s2, 16 |
| ; CI-NEXT: s_lshr_b32 s6, s3, 16 |
| ; CI-NEXT: v_cvt_f32_f16_e64 v1, |s5| |
| ; CI-NEXT: v_cvt_f32_f16_e64 v0, |s6| |
| ; CI-NEXT: ; implicit-def: $sgpr7 |
| ; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v1, v0 |
| ; CI-NEXT: s_or_b64 s[8:9], vcc, vcc |
| ; CI-NEXT: s_mov_b32 s8, 1 |
| ; CI-NEXT: s_cbranch_scc0 .LBB9_10 |
| ; CI-NEXT: ; %bb.9: ; %frem.else |
| ; CI-NEXT: s_and_b32 s7, s5, 0xffff8000 |
| ; CI-NEXT: v_cmp_eq_f32_e32 vcc, v1, v0 |
| ; CI-NEXT: s_or_b64 s[10:11], vcc, vcc |
| ; CI-NEXT: s_mov_b32 s8, 0 |
| ; CI-NEXT: s_cselect_b32 s7, s7, s5 |
| ; CI-NEXT: .LBB9_10: ; %Flow53 |
| ; CI-NEXT: s_xor_b32 s8, s8, 1 |
| ; CI-NEXT: s_cmp_lg_u32 s8, 0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB9_16 |
| ; CI-NEXT: ; %bb.11: ; %frem.compute |
| ; CI-NEXT: v_frexp_mant_f32_e32 v2, v1 |
| ; CI-NEXT: v_frexp_exp_i32_f32_e32 v1, v1 |
| ; CI-NEXT: v_readfirstlane_b32 s10, v1 |
| ; CI-NEXT: v_ldexp_f32_e64 v1, v2, 11 |
| ; CI-NEXT: v_readfirstlane_b32 s9, v1 |
| ; CI-NEXT: v_frexp_mant_f32_e32 v1, v0 |
| ; CI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s11, v0 |
| ; CI-NEXT: v_ldexp_f32_e64 v0, v1, 1 |
| ; CI-NEXT: v_div_scale_f32 v1, s[12:13], v0, v0, 1.0 |
| ; CI-NEXT: s_add_i32 s8, s10, -1 |
| ; CI-NEXT: s_add_i32 s7, s11, -1 |
| ; CI-NEXT: s_sub_i32 s8, s8, s7 |
| ; CI-NEXT: v_div_scale_f32 v2, s[12:13], 1.0, v0, 1.0 |
| ; CI-NEXT: s_or_b64 s[12:13], s[12:13], s[12:13] |
| ; CI-NEXT: v_rcp_f32_e32 v3, v1 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 |
| ; CI-NEXT: v_fma_f32 v3, v4, v3, v3 |
| ; CI-NEXT: v_mul_f32_e32 v4, v2, v3 |
| ; CI-NEXT: v_fma_f32 v5, -v1, v4, v2 |
| ; CI-NEXT: v_fma_f32 v4, v5, v3, v4 |
| ; CI-NEXT: v_fma_f32 v1, -v1, v4, v2 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; CI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 |
| ; CI-NEXT: s_cmp_le_i32 s8, 11 |
| ; CI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB9_14 |
| ; CI-NEXT: ; %bb.12: ; %frem.loop_body.preheader |
| ; CI-NEXT: s_add_i32 s10, s10, 11 |
| ; CI-NEXT: s_sub_i32 s8, s10, s11 |
| ; CI-NEXT: .LBB9_13: ; %frem.loop_body |
| ; CI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; CI-NEXT: v_mul_f32_e32 v2, s9, v1 |
| ; CI-NEXT: v_rndne_f32_e32 v2, v2 |
| ; CI-NEXT: v_fma_f32 v2, -v2, v0, s9 |
| ; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 |
| ; CI-NEXT: v_readfirstlane_b32 s12, v2 |
| ; CI-NEXT: s_or_b64 s[10:11], vcc, vcc |
| ; CI-NEXT: v_add_f32_e32 v2, v2, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s10, v2 |
| ; CI-NEXT: s_cselect_b32 s10, s10, s12 |
| ; CI-NEXT: v_ldexp_f32_e64 v2, s10, 11 |
| ; CI-NEXT: v_readfirstlane_b32 s11, v2 |
| ; CI-NEXT: s_add_i32 s8, s8, -11 |
| ; CI-NEXT: s_cmp_gt_i32 s8, 11 |
| ; CI-NEXT: s_mov_b32 s10, s9 |
| ; CI-NEXT: s_mov_b32 s9, s11 |
| ; CI-NEXT: s_cbranch_scc1 .LBB9_13 |
| ; CI-NEXT: s_branch .LBB9_15 |
| ; CI-NEXT: .LBB9_14: |
| ; CI-NEXT: s_mov_b32 s10, s9 |
| ; CI-NEXT: .LBB9_15: ; %frem.loop_exit |
| ; CI-NEXT: s_add_i32 s8, s8, -10 |
| ; CI-NEXT: v_mov_b32_e32 v2, s8 |
| ; CI-NEXT: v_ldexp_f32_e32 v2, s10, v2 |
| ; CI-NEXT: v_mul_f32_e32 v1, v2, v1 |
| ; CI-NEXT: v_rndne_f32_e32 v1, v1 |
| ; CI-NEXT: v_fma_f32 v1, -v1, v0, v2 |
| ; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1 |
| ; CI-NEXT: s_or_b64 s[8:9], vcc, vcc |
| ; CI-NEXT: v_add_f32_e32 v0, v1, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s10, v1 |
| ; CI-NEXT: v_readfirstlane_b32 s8, v0 |
| ; CI-NEXT: s_cselect_b32 s8, s8, s10 |
| ; CI-NEXT: v_mov_b32_e32 v0, s7 |
| ; CI-NEXT: v_ldexp_f32_e32 v0, s8, v0 |
| ; CI-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; CI-NEXT: s_and_b32 s8, s5, 0xffff8000 |
| ; CI-NEXT: v_readfirstlane_b32 s7, v0 |
| ; CI-NEXT: s_and_b32 s7, s7, 0x7fff |
| ; CI-NEXT: s_or_b32 s7, s7, s8 |
| ; CI-NEXT: .LBB9_16: ; %Flow54 |
| ; CI-NEXT: v_cvt_f32_f16_e32 v0, s3 |
| ; CI-NEXT: v_mov_b32_e32 v1, 0x7f800000 |
| ; CI-NEXT: v_cmp_nlg_f32_e32 vcc, 0, v0 |
| ; CI-NEXT: v_cvt_f32_f16_e64 v0, |s2| |
| ; CI-NEXT: s_or_b64 s[8:9], vcc, vcc |
| ; CI-NEXT: s_cselect_b32 s8, 1, 0 |
| ; CI-NEXT: s_movk_i32 s9, 0x7e00 |
| ; CI-NEXT: v_cmp_nge_f32_e32 vcc, v0, v1 |
| ; CI-NEXT: v_cvt_f32_f16_e32 v0, s6 |
| ; CI-NEXT: s_or_b64 s[2:3], vcc, vcc |
| ; CI-NEXT: s_cselect_b32 s10, 1, 0 |
| ; CI-NEXT: v_cmp_nlg_f32_e32 vcc, 0, v0 |
| ; CI-NEXT: v_cvt_f32_f16_e64 v0, |s5| |
| ; CI-NEXT: s_or_b64 s[2:3], vcc, vcc |
| ; CI-NEXT: s_cselect_b32 s6, 1, 0 |
| ; CI-NEXT: v_cmp_nge_f32_e32 vcc, v0, v1 |
| ; CI-NEXT: s_or_b64 s[2:3], vcc, vcc |
| ; CI-NEXT: s_cselect_b32 s2, 1, 0 |
| ; CI-NEXT: s_bfe_u32 s3, s9, 0x100000 |
| ; CI-NEXT: s_bfe_u32 s4, s4, 0x100000 |
| ; CI-NEXT: s_cmp_lg_u32 s8, 0 |
| ; CI-NEXT: s_cselect_b32 s4, s3, s4 |
| ; CI-NEXT: s_cmp_lg_u32 s10, 0 |
| ; CI-NEXT: s_cselect_b32 s4, s4, s3 |
| ; CI-NEXT: s_bfe_u32 s5, s7, 0x100000 |
| ; CI-NEXT: s_cmp_lg_u32 s6, 0 |
| ; CI-NEXT: s_cselect_b32 s5, s3, s5 |
| ; CI-NEXT: s_cmp_lg_u32 s2, 0 |
| ; CI-NEXT: s_cselect_b32 s2, s5, s3 |
| ; CI-NEXT: s_lshl_b32 s2, s2, 16 |
| ; CI-NEXT: s_or_b32 s2, s4, s2 |
| ; CI-NEXT: v_mov_b32_e32 v0, s2 |
| ; CI-NEXT: s_mov_b32 s2, -1 |
| ; CI-NEXT: s_mov_b32 s3, 0xf000 |
| ; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: frem_v2f16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_load_dword s2, s[2:3], 0x0 |
| ; VI-NEXT: s_load_dword s3, s[4:5], 0x10 |
| ; VI-NEXT: s_mov_b32 s5, 1 |
| ; VI-NEXT: ; implicit-def: $sgpr4 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_cvt_f32_f16_e64 v1, |s2| |
| ; VI-NEXT: v_cvt_f32_f16_e64 v0, |s3| |
| ; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v1, v0 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: s_cbranch_scc0 .LBB9_2 |
| ; VI-NEXT: ; %bb.1: ; %frem.else20 |
| ; VI-NEXT: s_and_b32 s4, s2, 0xffff8000 |
| ; VI-NEXT: v_cmp_eq_f32_e32 vcc, v1, v0 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: s_mov_b32 s5, 0 |
| ; VI-NEXT: s_cselect_b32 s4, s4, s2 |
| ; VI-NEXT: .LBB9_2: ; %Flow57 |
| ; VI-NEXT: s_xor_b32 s5, s5, 1 |
| ; VI-NEXT: s_cmp_lg_u32 s5, 0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB9_8 |
| ; VI-NEXT: ; %bb.3: ; %frem.compute19 |
| ; VI-NEXT: v_frexp_mant_f32_e32 v2, v1 |
| ; VI-NEXT: v_frexp_exp_i32_f32_e32 v1, v1 |
| ; VI-NEXT: v_readfirstlane_b32 s7, v1 |
| ; VI-NEXT: v_ldexp_f32 v1, v2, 11 |
| ; VI-NEXT: v_readfirstlane_b32 s6, v1 |
| ; VI-NEXT: v_frexp_mant_f32_e32 v1, v0 |
| ; VI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s8, v0 |
| ; VI-NEXT: v_ldexp_f32 v0, v1, 1 |
| ; VI-NEXT: v_div_scale_f32 v1, s[10:11], v0, v0, 1.0 |
| ; VI-NEXT: s_add_i32 s5, s7, -1 |
| ; VI-NEXT: s_add_i32 s4, s8, -1 |
| ; VI-NEXT: s_sub_i32 s5, s5, s4 |
| ; VI-NEXT: v_div_scale_f32 v2, s[10:11], 1.0, v0, 1.0 |
| ; VI-NEXT: s_cmp_lg_u64 s[10:11], 0 |
| ; VI-NEXT: v_rcp_f32_e32 v3, v1 |
| ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 |
| ; VI-NEXT: v_fma_f32 v3, v4, v3, v3 |
| ; VI-NEXT: v_mul_f32_e32 v4, v2, v3 |
| ; VI-NEXT: v_fma_f32 v5, -v1, v4, v2 |
| ; VI-NEXT: v_fma_f32 v4, v5, v3, v4 |
| ; VI-NEXT: v_fma_f32 v1, -v1, v4, v2 |
| ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; VI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 |
| ; VI-NEXT: s_cmp_le_i32 s5, 11 |
| ; VI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB9_6 |
| ; VI-NEXT: ; %bb.4: ; %frem.loop_body27.preheader |
| ; VI-NEXT: s_add_i32 s7, s7, 11 |
| ; VI-NEXT: s_sub_i32 s5, s7, s8 |
| ; VI-NEXT: .LBB9_5: ; %frem.loop_body27 |
| ; VI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; VI-NEXT: v_mul_f32_e32 v2, s6, v1 |
| ; VI-NEXT: v_rndne_f32_e32 v2, v2 |
| ; VI-NEXT: v_fma_f32 v2, -v2, v0, s6 |
| ; VI-NEXT: v_readfirstlane_b32 s7, v2 |
| ; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 |
| ; VI-NEXT: v_add_f32_e32 v2, v2, v0 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s8, v2 |
| ; VI-NEXT: s_cselect_b32 s7, s8, s7 |
| ; VI-NEXT: v_ldexp_f32 v2, s7, 11 |
| ; VI-NEXT: v_readfirstlane_b32 s8, v2 |
| ; VI-NEXT: s_add_i32 s5, s5, -11 |
| ; VI-NEXT: s_cmp_gt_i32 s5, 11 |
| ; VI-NEXT: s_mov_b32 s7, s6 |
| ; VI-NEXT: s_mov_b32 s6, s8 |
| ; VI-NEXT: s_cbranch_scc1 .LBB9_5 |
| ; VI-NEXT: s_branch .LBB9_7 |
| ; VI-NEXT: .LBB9_6: |
| ; VI-NEXT: s_mov_b32 s7, s6 |
| ; VI-NEXT: .LBB9_7: ; %frem.loop_exit28 |
| ; VI-NEXT: s_add_i32 s5, s5, -10 |
| ; VI-NEXT: v_mov_b32_e32 v2, s5 |
| ; VI-NEXT: v_ldexp_f32 v2, s7, v2 |
| ; VI-NEXT: v_mul_f32_e32 v1, v2, v1 |
| ; VI-NEXT: v_rndne_f32_e32 v1, v1 |
| ; VI-NEXT: v_fma_f32 v1, -v1, v0, v2 |
| ; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1 |
| ; VI-NEXT: v_add_f32_e32 v0, v1, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s5, v1 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s6, v0 |
| ; VI-NEXT: s_cselect_b32 s5, s6, s5 |
| ; VI-NEXT: v_mov_b32_e32 v0, s4 |
| ; VI-NEXT: v_ldexp_f32 v0, s5, v0 |
| ; VI-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; VI-NEXT: s_and_b32 s5, s2, 0xffff8000 |
| ; VI-NEXT: v_readfirstlane_b32 s4, v0 |
| ; VI-NEXT: s_and_b32 s4, s4, 0x7fff |
| ; VI-NEXT: s_or_b32 s4, s4, s5 |
| ; VI-NEXT: .LBB9_8: ; %Flow58 |
| ; VI-NEXT: s_lshr_b32 s5, s2, 16 |
| ; VI-NEXT: s_lshr_b32 s6, s3, 16 |
| ; VI-NEXT: v_cvt_f32_f16_e64 v1, |s5| |
| ; VI-NEXT: v_cvt_f32_f16_e64 v0, |s6| |
| ; VI-NEXT: s_mov_b32 s8, 1 |
| ; VI-NEXT: ; implicit-def: $sgpr7 |
| ; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v1, v0 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: s_cbranch_scc0 .LBB9_10 |
| ; VI-NEXT: ; %bb.9: ; %frem.else |
| ; VI-NEXT: s_and_b32 s7, s5, 0xffff8000 |
| ; VI-NEXT: v_cmp_eq_f32_e32 vcc, v1, v0 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: s_mov_b32 s8, 0 |
| ; VI-NEXT: s_cselect_b32 s7, s7, s5 |
| ; VI-NEXT: .LBB9_10: ; %Flow53 |
| ; VI-NEXT: s_xor_b32 s8, s8, 1 |
| ; VI-NEXT: s_cmp_lg_u32 s8, 0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB9_16 |
| ; VI-NEXT: ; %bb.11: ; %frem.compute |
| ; VI-NEXT: v_frexp_mant_f32_e32 v2, v1 |
| ; VI-NEXT: v_frexp_exp_i32_f32_e32 v1, v1 |
| ; VI-NEXT: v_readfirstlane_b32 s10, v1 |
| ; VI-NEXT: v_ldexp_f32 v1, v2, 11 |
| ; VI-NEXT: v_readfirstlane_b32 s9, v1 |
| ; VI-NEXT: v_frexp_mant_f32_e32 v1, v0 |
| ; VI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s11, v0 |
| ; VI-NEXT: v_ldexp_f32 v0, v1, 1 |
| ; VI-NEXT: v_div_scale_f32 v1, s[12:13], v0, v0, 1.0 |
| ; VI-NEXT: s_add_i32 s8, s10, -1 |
| ; VI-NEXT: s_add_i32 s7, s11, -1 |
| ; VI-NEXT: s_sub_i32 s8, s8, s7 |
| ; VI-NEXT: v_div_scale_f32 v2, s[12:13], 1.0, v0, 1.0 |
| ; VI-NEXT: s_cmp_lg_u64 s[12:13], 0 |
| ; VI-NEXT: v_rcp_f32_e32 v3, v1 |
| ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 |
| ; VI-NEXT: v_fma_f32 v3, v4, v3, v3 |
| ; VI-NEXT: v_mul_f32_e32 v4, v2, v3 |
| ; VI-NEXT: v_fma_f32 v5, -v1, v4, v2 |
| ; VI-NEXT: v_fma_f32 v4, v5, v3, v4 |
| ; VI-NEXT: v_fma_f32 v1, -v1, v4, v2 |
| ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; VI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 |
| ; VI-NEXT: s_cmp_le_i32 s8, 11 |
| ; VI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB9_14 |
| ; VI-NEXT: ; %bb.12: ; %frem.loop_body.preheader |
| ; VI-NEXT: s_add_i32 s10, s10, 11 |
| ; VI-NEXT: s_sub_i32 s8, s10, s11 |
| ; VI-NEXT: .LBB9_13: ; %frem.loop_body |
| ; VI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; VI-NEXT: v_mul_f32_e32 v2, s9, v1 |
| ; VI-NEXT: v_rndne_f32_e32 v2, v2 |
| ; VI-NEXT: v_fma_f32 v2, -v2, v0, s9 |
| ; VI-NEXT: v_readfirstlane_b32 s10, v2 |
| ; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 |
| ; VI-NEXT: v_add_f32_e32 v2, v2, v0 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s11, v2 |
| ; VI-NEXT: s_cselect_b32 s10, s11, s10 |
| ; VI-NEXT: v_ldexp_f32 v2, s10, 11 |
| ; VI-NEXT: v_readfirstlane_b32 s11, v2 |
| ; VI-NEXT: s_add_i32 s8, s8, -11 |
| ; VI-NEXT: s_cmp_gt_i32 s8, 11 |
| ; VI-NEXT: s_mov_b32 s10, s9 |
| ; VI-NEXT: s_mov_b32 s9, s11 |
| ; VI-NEXT: s_cbranch_scc1 .LBB9_13 |
| ; VI-NEXT: s_branch .LBB9_15 |
| ; VI-NEXT: .LBB9_14: |
| ; VI-NEXT: s_mov_b32 s10, s9 |
| ; VI-NEXT: .LBB9_15: ; %frem.loop_exit |
| ; VI-NEXT: s_add_i32 s8, s8, -10 |
| ; VI-NEXT: v_mov_b32_e32 v2, s8 |
| ; VI-NEXT: v_ldexp_f32 v2, s10, v2 |
| ; VI-NEXT: v_mul_f32_e32 v1, v2, v1 |
| ; VI-NEXT: v_rndne_f32_e32 v1, v1 |
| ; VI-NEXT: v_fma_f32 v1, -v1, v0, v2 |
| ; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1 |
| ; VI-NEXT: v_add_f32_e32 v0, v1, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s8, v1 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s9, v0 |
| ; VI-NEXT: s_cselect_b32 s8, s9, s8 |
| ; VI-NEXT: v_mov_b32_e32 v0, s7 |
| ; VI-NEXT: v_ldexp_f32 v0, s8, v0 |
| ; VI-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; VI-NEXT: s_and_b32 s8, s5, 0xffff8000 |
| ; VI-NEXT: v_readfirstlane_b32 s7, v0 |
| ; VI-NEXT: s_and_b32 s7, s7, 0x7fff |
| ; VI-NEXT: s_or_b32 s7, s7, s8 |
| ; VI-NEXT: .LBB9_16: ; %Flow54 |
| ; VI-NEXT: v_cmp_nlg_f16_e64 s[8:9], s3, 0 |
| ; VI-NEXT: v_mov_b32_e32 v0, 0x7c00 |
| ; VI-NEXT: s_cmp_lg_u64 s[8:9], 0 |
| ; VI-NEXT: v_cmp_nge_f16_e64 s[2:3], |s2|, v0 |
| ; VI-NEXT: s_cselect_b32 s8, 1, 0 |
| ; VI-NEXT: s_cmp_lg_u64 s[2:3], 0 |
| ; VI-NEXT: v_cmp_nlg_f16_e64 s[2:3], s6, 0 |
| ; VI-NEXT: s_cselect_b32 s10, 1, 0 |
| ; VI-NEXT: s_cmp_lg_u64 s[2:3], 0 |
| ; VI-NEXT: v_cmp_nge_f16_e64 s[2:3], |s5|, v0 |
| ; VI-NEXT: s_movk_i32 s9, 0x7e00 |
| ; VI-NEXT: s_cselect_b32 s6, 1, 0 |
| ; VI-NEXT: s_cmp_lg_u64 s[2:3], 0 |
| ; VI-NEXT: s_cselect_b32 s2, 1, 0 |
| ; VI-NEXT: s_bfe_u32 s3, s9, 0x100000 |
| ; VI-NEXT: s_bfe_u32 s4, s4, 0x100000 |
| ; VI-NEXT: s_cmp_lg_u32 s8, 0 |
| ; VI-NEXT: s_cselect_b32 s4, s3, s4 |
| ; VI-NEXT: s_cmp_lg_u32 s10, 0 |
| ; VI-NEXT: s_cselect_b32 s4, s4, s3 |
| ; VI-NEXT: s_bfe_u32 s5, s7, 0x100000 |
| ; VI-NEXT: s_cmp_lg_u32 s6, 0 |
| ; VI-NEXT: s_cselect_b32 s5, s3, s5 |
| ; VI-NEXT: s_cmp_lg_u32 s2, 0 |
| ; VI-NEXT: s_cselect_b32 s2, s5, s3 |
| ; VI-NEXT: s_lshl_b32 s2, s2, 16 |
| ; VI-NEXT: s_or_b32 s2, s4, s2 |
| ; VI-NEXT: v_mov_b32_e32 v2, s2 |
| ; VI-NEXT: v_mov_b32_e32 v0, s0 |
| ; VI-NEXT: v_mov_b32_e32 v1, s1 |
| ; VI-NEXT: flat_store_dword v[0:1], v2 |
| ; VI-NEXT: s_endpgm |
| %gep2 = getelementptr <2 x half>, ptr addrspace(1) %in2, i32 4 |
| %r0 = load <2 x half>, ptr addrspace(1) %in1, align 8 |
| %r1 = load <2 x half>, ptr addrspace(1) %gep2, align 8 |
| %r2 = frem <2 x half> %r0, %r1 |
| store <2 x half> %r2, ptr addrspace(1) %out, align 8 |
| ret void |
| } |
| |
| define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 { |
| ; CI-LABEL: frem_v4f16: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 |
| ; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 |
| ; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x8 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_cvt_f32_f16_e64 v1, |s2| |
| ; CI-NEXT: v_cvt_f32_f16_e64 v0, |s4| |
| ; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v1, v0 |
| ; CI-NEXT: s_or_b64 s[6:7], vcc, vcc |
| ; CI-NEXT: s_mov_b32 s7, 1 |
| ; CI-NEXT: ; implicit-def: $sgpr6 |
| ; CI-NEXT: s_cbranch_scc0 .LBB10_2 |
| ; CI-NEXT: ; %bb.1: ; %frem.else86 |
| ; CI-NEXT: s_and_b32 s6, s2, 0xffff8000 |
| ; CI-NEXT: v_cmp_eq_f32_e32 vcc, v1, v0 |
| ; CI-NEXT: s_or_b64 s[8:9], vcc, vcc |
| ; CI-NEXT: s_mov_b32 s7, 0 |
| ; CI-NEXT: s_cselect_b32 s6, s6, s2 |
| ; CI-NEXT: .LBB10_2: ; %Flow135 |
| ; CI-NEXT: s_xor_b32 s7, s7, 1 |
| ; CI-NEXT: s_cmp_lg_u32 s7, 0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB10_8 |
| ; CI-NEXT: ; %bb.3: ; %frem.compute85 |
| ; CI-NEXT: v_frexp_mant_f32_e32 v2, v1 |
| ; CI-NEXT: v_frexp_exp_i32_f32_e32 v1, v1 |
| ; CI-NEXT: v_readfirstlane_b32 s9, v1 |
| ; CI-NEXT: v_ldexp_f32_e64 v1, v2, 11 |
| ; CI-NEXT: v_readfirstlane_b32 s8, v1 |
| ; CI-NEXT: v_frexp_mant_f32_e32 v1, v0 |
| ; CI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s10, v0 |
| ; CI-NEXT: v_ldexp_f32_e64 v0, v1, 1 |
| ; CI-NEXT: v_div_scale_f32 v1, s[12:13], v0, v0, 1.0 |
| ; CI-NEXT: s_add_i32 s7, s9, -1 |
| ; CI-NEXT: s_add_i32 s6, s10, -1 |
| ; CI-NEXT: s_sub_i32 s7, s7, s6 |
| ; CI-NEXT: v_div_scale_f32 v2, s[12:13], 1.0, v0, 1.0 |
| ; CI-NEXT: s_or_b64 s[12:13], s[12:13], s[12:13] |
| ; CI-NEXT: v_rcp_f32_e32 v3, v1 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 |
| ; CI-NEXT: v_fma_f32 v3, v4, v3, v3 |
| ; CI-NEXT: v_mul_f32_e32 v4, v2, v3 |
| ; CI-NEXT: v_fma_f32 v5, -v1, v4, v2 |
| ; CI-NEXT: v_fma_f32 v4, v5, v3, v4 |
| ; CI-NEXT: v_fma_f32 v1, -v1, v4, v2 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; CI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 |
| ; CI-NEXT: s_cmp_le_i32 s7, 11 |
| ; CI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB10_6 |
| ; CI-NEXT: ; %bb.4: ; %frem.loop_body93.preheader |
| ; CI-NEXT: s_add_i32 s9, s9, 11 |
| ; CI-NEXT: s_sub_i32 s7, s9, s10 |
| ; CI-NEXT: .LBB10_5: ; %frem.loop_body93 |
| ; CI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; CI-NEXT: v_mul_f32_e32 v2, s8, v1 |
| ; CI-NEXT: v_rndne_f32_e32 v2, v2 |
| ; CI-NEXT: v_fma_f32 v2, -v2, v0, s8 |
| ; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 |
| ; CI-NEXT: v_readfirstlane_b32 s9, v2 |
| ; CI-NEXT: s_or_b64 s[10:11], vcc, vcc |
| ; CI-NEXT: v_add_f32_e32 v2, v2, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s10, v2 |
| ; CI-NEXT: s_cselect_b32 s9, s10, s9 |
| ; CI-NEXT: v_ldexp_f32_e64 v2, s9, 11 |
| ; CI-NEXT: v_readfirstlane_b32 s10, v2 |
| ; CI-NEXT: s_add_i32 s7, s7, -11 |
| ; CI-NEXT: s_cmp_gt_i32 s7, 11 |
| ; CI-NEXT: s_mov_b32 s9, s8 |
| ; CI-NEXT: s_mov_b32 s8, s10 |
| ; CI-NEXT: s_cbranch_scc1 .LBB10_5 |
| ; CI-NEXT: s_branch .LBB10_7 |
| ; CI-NEXT: .LBB10_6: |
| ; CI-NEXT: s_mov_b32 s9, s8 |
| ; CI-NEXT: .LBB10_7: ; %frem.loop_exit94 |
| ; CI-NEXT: s_add_i32 s7, s7, -10 |
| ; CI-NEXT: v_mov_b32_e32 v2, s7 |
| ; CI-NEXT: v_ldexp_f32_e32 v2, s9, v2 |
| ; CI-NEXT: v_mul_f32_e32 v1, v2, v1 |
| ; CI-NEXT: v_rndne_f32_e32 v1, v1 |
| ; CI-NEXT: v_fma_f32 v1, -v1, v0, v2 |
| ; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1 |
| ; CI-NEXT: s_or_b64 s[8:9], vcc, vcc |
| ; CI-NEXT: v_add_f32_e32 v0, v1, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s7, v1 |
| ; CI-NEXT: v_readfirstlane_b32 s8, v0 |
| ; CI-NEXT: s_cselect_b32 s7, s8, s7 |
| ; CI-NEXT: v_mov_b32_e32 v0, s6 |
| ; CI-NEXT: v_ldexp_f32_e32 v0, s7, v0 |
| ; CI-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; CI-NEXT: s_and_b32 s7, s2, 0xffff8000 |
| ; CI-NEXT: v_readfirstlane_b32 s6, v0 |
| ; CI-NEXT: s_and_b32 s6, s6, 0x7fff |
| ; CI-NEXT: s_or_b32 s6, s6, s7 |
| ; CI-NEXT: .LBB10_8: ; %Flow136 |
| ; CI-NEXT: s_lshr_b32 s7, s2, 16 |
| ; CI-NEXT: s_lshr_b32 s8, s4, 16 |
| ; CI-NEXT: v_cvt_f32_f16_e64 v1, |s7| |
| ; CI-NEXT: v_cvt_f32_f16_e64 v0, |s8| |
| ; CI-NEXT: ; implicit-def: $sgpr9 |
| ; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v1, v0 |
| ; CI-NEXT: s_or_b64 s[10:11], vcc, vcc |
| ; CI-NEXT: s_mov_b32 s10, 1 |
| ; CI-NEXT: s_cbranch_scc0 .LBB10_10 |
| ; CI-NEXT: ; %bb.9: ; %frem.else53 |
| ; CI-NEXT: s_and_b32 s9, s7, 0xffff8000 |
| ; CI-NEXT: v_cmp_eq_f32_e32 vcc, v1, v0 |
| ; CI-NEXT: s_or_b64 s[12:13], vcc, vcc |
| ; CI-NEXT: s_mov_b32 s10, 0 |
| ; CI-NEXT: s_cselect_b32 s9, s9, s7 |
| ; CI-NEXT: .LBB10_10: ; %Flow131 |
| ; CI-NEXT: s_xor_b32 s10, s10, 1 |
| ; CI-NEXT: s_cmp_lg_u32 s10, 0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB10_16 |
| ; CI-NEXT: ; %bb.11: ; %frem.compute52 |
| ; CI-NEXT: v_frexp_mant_f32_e32 v2, v1 |
| ; CI-NEXT: v_frexp_exp_i32_f32_e32 v1, v1 |
| ; CI-NEXT: v_readfirstlane_b32 s12, v1 |
| ; CI-NEXT: v_ldexp_f32_e64 v1, v2, 11 |
| ; CI-NEXT: v_readfirstlane_b32 s11, v1 |
| ; CI-NEXT: v_frexp_mant_f32_e32 v1, v0 |
| ; CI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s13, v0 |
| ; CI-NEXT: v_ldexp_f32_e64 v0, v1, 1 |
| ; CI-NEXT: v_div_scale_f32 v1, s[14:15], v0, v0, 1.0 |
| ; CI-NEXT: s_add_i32 s10, s12, -1 |
| ; CI-NEXT: s_add_i32 s9, s13, -1 |
| ; CI-NEXT: s_sub_i32 s10, s10, s9 |
| ; CI-NEXT: v_div_scale_f32 v2, s[14:15], 1.0, v0, 1.0 |
| ; CI-NEXT: s_or_b64 s[14:15], s[14:15], s[14:15] |
| ; CI-NEXT: v_rcp_f32_e32 v3, v1 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 |
| ; CI-NEXT: v_fma_f32 v3, v4, v3, v3 |
| ; CI-NEXT: v_mul_f32_e32 v4, v2, v3 |
| ; CI-NEXT: v_fma_f32 v5, -v1, v4, v2 |
| ; CI-NEXT: v_fma_f32 v4, v5, v3, v4 |
| ; CI-NEXT: v_fma_f32 v1, -v1, v4, v2 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; CI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 |
| ; CI-NEXT: s_cmp_le_i32 s10, 11 |
| ; CI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB10_14 |
| ; CI-NEXT: ; %bb.12: ; %frem.loop_body60.preheader |
| ; CI-NEXT: s_add_i32 s12, s12, 11 |
| ; CI-NEXT: s_sub_i32 s10, s12, s13 |
| ; CI-NEXT: .LBB10_13: ; %frem.loop_body60 |
| ; CI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; CI-NEXT: v_mul_f32_e32 v2, s11, v1 |
| ; CI-NEXT: v_rndne_f32_e32 v2, v2 |
| ; CI-NEXT: v_fma_f32 v2, -v2, v0, s11 |
| ; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 |
| ; CI-NEXT: v_readfirstlane_b32 s14, v2 |
| ; CI-NEXT: s_or_b64 s[12:13], vcc, vcc |
| ; CI-NEXT: v_add_f32_e32 v2, v2, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s12, v2 |
| ; CI-NEXT: s_cselect_b32 s12, s12, s14 |
| ; CI-NEXT: v_ldexp_f32_e64 v2, s12, 11 |
| ; CI-NEXT: v_readfirstlane_b32 s13, v2 |
| ; CI-NEXT: s_add_i32 s10, s10, -11 |
| ; CI-NEXT: s_cmp_gt_i32 s10, 11 |
| ; CI-NEXT: s_mov_b32 s12, s11 |
| ; CI-NEXT: s_mov_b32 s11, s13 |
| ; CI-NEXT: s_cbranch_scc1 .LBB10_13 |
| ; CI-NEXT: s_branch .LBB10_15 |
| ; CI-NEXT: .LBB10_14: |
| ; CI-NEXT: s_mov_b32 s12, s11 |
| ; CI-NEXT: .LBB10_15: ; %frem.loop_exit61 |
| ; CI-NEXT: s_add_i32 s10, s10, -10 |
| ; CI-NEXT: v_mov_b32_e32 v2, s10 |
| ; CI-NEXT: v_ldexp_f32_e32 v2, s12, v2 |
| ; CI-NEXT: v_mul_f32_e32 v1, v2, v1 |
| ; CI-NEXT: v_rndne_f32_e32 v1, v1 |
| ; CI-NEXT: v_fma_f32 v1, -v1, v0, v2 |
| ; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1 |
| ; CI-NEXT: s_or_b64 s[10:11], vcc, vcc |
| ; CI-NEXT: v_add_f32_e32 v0, v1, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s12, v1 |
| ; CI-NEXT: v_readfirstlane_b32 s10, v0 |
| ; CI-NEXT: s_cselect_b32 s10, s10, s12 |
| ; CI-NEXT: v_mov_b32_e32 v0, s9 |
| ; CI-NEXT: v_ldexp_f32_e32 v0, s10, v0 |
| ; CI-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; CI-NEXT: s_and_b32 s10, s7, 0xffff8000 |
| ; CI-NEXT: v_readfirstlane_b32 s9, v0 |
| ; CI-NEXT: s_and_b32 s9, s9, 0x7fff |
| ; CI-NEXT: s_or_b32 s9, s9, s10 |
| ; CI-NEXT: .LBB10_16: ; %Flow132 |
| ; CI-NEXT: v_cvt_f32_f16_e64 v1, |s3| |
| ; CI-NEXT: v_cvt_f32_f16_e64 v0, |s5| |
| ; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v1, v0 |
| ; CI-NEXT: s_or_b64 s[10:11], vcc, vcc |
| ; CI-NEXT: s_mov_b32 s11, 1 |
| ; CI-NEXT: ; implicit-def: $sgpr10 |
| ; CI-NEXT: s_cbranch_scc0 .LBB10_18 |
| ; CI-NEXT: ; %bb.17: ; %frem.else20 |
| ; CI-NEXT: s_and_b32 s10, s3, 0xffff8000 |
| ; CI-NEXT: v_cmp_eq_f32_e32 vcc, v1, v0 |
| ; CI-NEXT: s_or_b64 s[12:13], vcc, vcc |
| ; CI-NEXT: s_mov_b32 s11, 0 |
| ; CI-NEXT: s_cselect_b32 s10, s10, s3 |
| ; CI-NEXT: .LBB10_18: ; %Flow127 |
| ; CI-NEXT: s_xor_b32 s11, s11, 1 |
| ; CI-NEXT: s_cmp_lg_u32 s11, 0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB10_24 |
| ; CI-NEXT: ; %bb.19: ; %frem.compute19 |
| ; CI-NEXT: v_frexp_mant_f32_e32 v2, v1 |
| ; CI-NEXT: v_frexp_exp_i32_f32_e32 v1, v1 |
| ; CI-NEXT: v_readfirstlane_b32 s13, v1 |
| ; CI-NEXT: v_ldexp_f32_e64 v1, v2, 11 |
| ; CI-NEXT: v_readfirstlane_b32 s12, v1 |
| ; CI-NEXT: v_frexp_mant_f32_e32 v1, v0 |
| ; CI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s14, v0 |
| ; CI-NEXT: v_ldexp_f32_e64 v0, v1, 1 |
| ; CI-NEXT: v_div_scale_f32 v1, s[16:17], v0, v0, 1.0 |
| ; CI-NEXT: s_add_i32 s11, s13, -1 |
| ; CI-NEXT: s_add_i32 s10, s14, -1 |
| ; CI-NEXT: s_sub_i32 s11, s11, s10 |
| ; CI-NEXT: v_div_scale_f32 v2, s[16:17], 1.0, v0, 1.0 |
| ; CI-NEXT: s_or_b64 s[16:17], s[16:17], s[16:17] |
| ; CI-NEXT: v_rcp_f32_e32 v3, v1 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 |
| ; CI-NEXT: v_fma_f32 v3, v4, v3, v3 |
| ; CI-NEXT: v_mul_f32_e32 v4, v2, v3 |
| ; CI-NEXT: v_fma_f32 v5, -v1, v4, v2 |
| ; CI-NEXT: v_fma_f32 v4, v5, v3, v4 |
| ; CI-NEXT: v_fma_f32 v1, -v1, v4, v2 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; CI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 |
| ; CI-NEXT: s_cmp_le_i32 s11, 11 |
| ; CI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB10_22 |
| ; CI-NEXT: ; %bb.20: ; %frem.loop_body27.preheader |
| ; CI-NEXT: s_add_i32 s13, s13, 11 |
| ; CI-NEXT: s_sub_i32 s11, s13, s14 |
| ; CI-NEXT: .LBB10_21: ; %frem.loop_body27 |
| ; CI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; CI-NEXT: v_mul_f32_e32 v2, s12, v1 |
| ; CI-NEXT: v_rndne_f32_e32 v2, v2 |
| ; CI-NEXT: v_fma_f32 v2, -v2, v0, s12 |
| ; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 |
| ; CI-NEXT: v_readfirstlane_b32 s13, v2 |
| ; CI-NEXT: s_or_b64 s[14:15], vcc, vcc |
| ; CI-NEXT: v_add_f32_e32 v2, v2, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s14, v2 |
| ; CI-NEXT: s_cselect_b32 s13, s14, s13 |
| ; CI-NEXT: v_ldexp_f32_e64 v2, s13, 11 |
| ; CI-NEXT: v_readfirstlane_b32 s14, v2 |
| ; CI-NEXT: s_add_i32 s11, s11, -11 |
| ; CI-NEXT: s_cmp_gt_i32 s11, 11 |
| ; CI-NEXT: s_mov_b32 s13, s12 |
| ; CI-NEXT: s_mov_b32 s12, s14 |
| ; CI-NEXT: s_cbranch_scc1 .LBB10_21 |
| ; CI-NEXT: s_branch .LBB10_23 |
| ; CI-NEXT: .LBB10_22: |
| ; CI-NEXT: s_mov_b32 s13, s12 |
| ; CI-NEXT: .LBB10_23: ; %frem.loop_exit28 |
| ; CI-NEXT: s_add_i32 s11, s11, -10 |
| ; CI-NEXT: v_mov_b32_e32 v2, s11 |
| ; CI-NEXT: v_ldexp_f32_e32 v2, s13, v2 |
| ; CI-NEXT: v_mul_f32_e32 v1, v2, v1 |
| ; CI-NEXT: v_rndne_f32_e32 v1, v1 |
| ; CI-NEXT: v_fma_f32 v1, -v1, v0, v2 |
| ; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1 |
| ; CI-NEXT: s_or_b64 s[12:13], vcc, vcc |
| ; CI-NEXT: v_add_f32_e32 v0, v1, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s11, v1 |
| ; CI-NEXT: v_readfirstlane_b32 s12, v0 |
| ; CI-NEXT: s_cselect_b32 s11, s12, s11 |
| ; CI-NEXT: v_mov_b32_e32 v0, s10 |
| ; CI-NEXT: v_ldexp_f32_e32 v0, s11, v0 |
| ; CI-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; CI-NEXT: s_and_b32 s11, s3, 0xffff8000 |
| ; CI-NEXT: v_readfirstlane_b32 s10, v0 |
| ; CI-NEXT: s_and_b32 s10, s10, 0x7fff |
| ; CI-NEXT: s_or_b32 s10, s10, s11 |
| ; CI-NEXT: .LBB10_24: ; %Flow128 |
| ; CI-NEXT: s_lshr_b32 s11, s3, 16 |
| ; CI-NEXT: s_lshr_b32 s12, s5, 16 |
| ; CI-NEXT: v_cvt_f32_f16_e64 v1, |s11| |
| ; CI-NEXT: v_cvt_f32_f16_e64 v0, |s12| |
| ; CI-NEXT: ; implicit-def: $sgpr13 |
| ; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v1, v0 |
| ; CI-NEXT: s_or_b64 s[14:15], vcc, vcc |
| ; CI-NEXT: s_mov_b32 s14, 1 |
| ; CI-NEXT: s_cbranch_scc0 .LBB10_26 |
| ; CI-NEXT: ; %bb.25: ; %frem.else |
| ; CI-NEXT: s_and_b32 s13, s11, 0xffff8000 |
| ; CI-NEXT: v_cmp_eq_f32_e32 vcc, v1, v0 |
| ; CI-NEXT: s_or_b64 s[16:17], vcc, vcc |
| ; CI-NEXT: s_mov_b32 s14, 0 |
| ; CI-NEXT: s_cselect_b32 s13, s13, s11 |
| ; CI-NEXT: .LBB10_26: ; %Flow123 |
| ; CI-NEXT: s_xor_b32 s14, s14, 1 |
| ; CI-NEXT: s_cmp_lg_u32 s14, 0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB10_32 |
| ; CI-NEXT: ; %bb.27: ; %frem.compute |
| ; CI-NEXT: v_frexp_mant_f32_e32 v2, v1 |
| ; CI-NEXT: v_frexp_exp_i32_f32_e32 v1, v1 |
| ; CI-NEXT: v_readfirstlane_b32 s16, v1 |
| ; CI-NEXT: v_ldexp_f32_e64 v1, v2, 11 |
| ; CI-NEXT: v_readfirstlane_b32 s15, v1 |
| ; CI-NEXT: v_frexp_mant_f32_e32 v1, v0 |
| ; CI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s17, v0 |
| ; CI-NEXT: v_ldexp_f32_e64 v0, v1, 1 |
| ; CI-NEXT: v_div_scale_f32 v1, s[18:19], v0, v0, 1.0 |
| ; CI-NEXT: s_add_i32 s14, s16, -1 |
| ; CI-NEXT: s_add_i32 s13, s17, -1 |
| ; CI-NEXT: s_sub_i32 s14, s14, s13 |
| ; CI-NEXT: v_div_scale_f32 v2, s[18:19], 1.0, v0, 1.0 |
| ; CI-NEXT: s_or_b64 s[18:19], s[18:19], s[18:19] |
| ; CI-NEXT: v_rcp_f32_e32 v3, v1 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 |
| ; CI-NEXT: v_fma_f32 v3, v4, v3, v3 |
| ; CI-NEXT: v_mul_f32_e32 v4, v2, v3 |
| ; CI-NEXT: v_fma_f32 v5, -v1, v4, v2 |
| ; CI-NEXT: v_fma_f32 v4, v5, v3, v4 |
| ; CI-NEXT: v_fma_f32 v1, -v1, v4, v2 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; CI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 |
| ; CI-NEXT: s_cmp_le_i32 s14, 11 |
| ; CI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB10_30 |
| ; CI-NEXT: ; %bb.28: ; %frem.loop_body.preheader |
| ; CI-NEXT: s_add_i32 s16, s16, 11 |
| ; CI-NEXT: s_sub_i32 s14, s16, s17 |
| ; CI-NEXT: .LBB10_29: ; %frem.loop_body |
| ; CI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; CI-NEXT: v_mul_f32_e32 v2, s15, v1 |
| ; CI-NEXT: v_rndne_f32_e32 v2, v2 |
| ; CI-NEXT: v_fma_f32 v2, -v2, v0, s15 |
| ; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 |
| ; CI-NEXT: v_readfirstlane_b32 s18, v2 |
| ; CI-NEXT: s_or_b64 s[16:17], vcc, vcc |
| ; CI-NEXT: v_add_f32_e32 v2, v2, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s16, v2 |
| ; CI-NEXT: s_cselect_b32 s16, s16, s18 |
| ; CI-NEXT: v_ldexp_f32_e64 v2, s16, 11 |
| ; CI-NEXT: v_readfirstlane_b32 s17, v2 |
| ; CI-NEXT: s_add_i32 s14, s14, -11 |
| ; CI-NEXT: s_cmp_gt_i32 s14, 11 |
| ; CI-NEXT: s_mov_b32 s16, s15 |
| ; CI-NEXT: s_mov_b32 s15, s17 |
| ; CI-NEXT: s_cbranch_scc1 .LBB10_29 |
| ; CI-NEXT: s_branch .LBB10_31 |
| ; CI-NEXT: .LBB10_30: |
| ; CI-NEXT: s_mov_b32 s16, s15 |
| ; CI-NEXT: .LBB10_31: ; %frem.loop_exit |
| ; CI-NEXT: s_add_i32 s14, s14, -10 |
| ; CI-NEXT: v_mov_b32_e32 v2, s14 |
| ; CI-NEXT: v_ldexp_f32_e32 v2, s16, v2 |
| ; CI-NEXT: v_mul_f32_e32 v1, v2, v1 |
| ; CI-NEXT: v_rndne_f32_e32 v1, v1 |
| ; CI-NEXT: v_fma_f32 v1, -v1, v0, v2 |
| ; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1 |
| ; CI-NEXT: s_or_b64 s[14:15], vcc, vcc |
| ; CI-NEXT: v_add_f32_e32 v0, v1, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s16, v1 |
| ; CI-NEXT: v_readfirstlane_b32 s14, v0 |
| ; CI-NEXT: s_cselect_b32 s14, s14, s16 |
| ; CI-NEXT: v_mov_b32_e32 v0, s13 |
| ; CI-NEXT: v_ldexp_f32_e32 v0, s14, v0 |
| ; CI-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; CI-NEXT: s_and_b32 s14, s11, 0xffff8000 |
| ; CI-NEXT: v_readfirstlane_b32 s13, v0 |
| ; CI-NEXT: s_and_b32 s13, s13, 0x7fff |
| ; CI-NEXT: s_or_b32 s13, s13, s14 |
| ; CI-NEXT: .LBB10_32: ; %Flow124 |
| ; CI-NEXT: v_cvt_f32_f16_e32 v0, s4 |
| ; CI-NEXT: v_mov_b32_e32 v1, 0x7f800000 |
| ; CI-NEXT: s_movk_i32 s17, 0x7e00 |
| ; CI-NEXT: v_cmp_nlg_f32_e32 vcc, 0, v0 |
| ; CI-NEXT: v_cvt_f32_f16_e64 v0, |s2| |
| ; CI-NEXT: s_or_b64 s[14:15], vcc, vcc |
| ; CI-NEXT: s_cselect_b32 s16, 1, 0 |
| ; CI-NEXT: v_cmp_nge_f32_e32 vcc, v0, v1 |
| ; CI-NEXT: v_cvt_f32_f16_e32 v0, s8 |
| ; CI-NEXT: s_or_b64 s[14:15], vcc, vcc |
| ; CI-NEXT: s_cselect_b32 s18, 1, 0 |
| ; CI-NEXT: v_cmp_nlg_f32_e32 vcc, 0, v0 |
| ; CI-NEXT: v_cvt_f32_f16_e64 v0, |s7| |
| ; CI-NEXT: s_or_b64 s[14:15], vcc, vcc |
| ; CI-NEXT: s_cselect_b32 s8, 1, 0 |
| ; CI-NEXT: v_cmp_nge_f32_e32 vcc, v0, v1 |
| ; CI-NEXT: v_cvt_f32_f16_e32 v0, s5 |
| ; CI-NEXT: s_or_b64 s[14:15], vcc, vcc |
| ; CI-NEXT: s_cselect_b32 s7, 1, 0 |
| ; CI-NEXT: v_cmp_nlg_f32_e32 vcc, 0, v0 |
| ; CI-NEXT: v_cvt_f32_f16_e64 v0, |s3| |
| ; CI-NEXT: s_or_b64 s[4:5], vcc, vcc |
| ; CI-NEXT: s_cselect_b32 s4, 1, 0 |
| ; CI-NEXT: v_cmp_nge_f32_e32 vcc, v0, v1 |
| ; CI-NEXT: v_cvt_f32_f16_e32 v0, s12 |
| ; CI-NEXT: s_or_b64 s[2:3], vcc, vcc |
| ; CI-NEXT: s_cselect_b32 s5, 1, 0 |
| ; CI-NEXT: v_cmp_nlg_f32_e32 vcc, 0, v0 |
| ; CI-NEXT: v_cvt_f32_f16_e64 v0, |s11| |
| ; CI-NEXT: s_or_b64 s[2:3], vcc, vcc |
| ; CI-NEXT: s_cselect_b32 s12, 1, 0 |
| ; CI-NEXT: v_cmp_nge_f32_e32 vcc, v0, v1 |
| ; CI-NEXT: s_or_b64 s[2:3], vcc, vcc |
| ; CI-NEXT: s_cselect_b32 s3, 1, 0 |
| ; CI-NEXT: s_bfe_u32 s11, s17, 0x100000 |
| ; CI-NEXT: s_bfe_u32 s2, s6, 0x100000 |
| ; CI-NEXT: s_cmp_lg_u32 s16, 0 |
| ; CI-NEXT: s_cselect_b32 s2, s11, s2 |
| ; CI-NEXT: s_cmp_lg_u32 s18, 0 |
| ; CI-NEXT: s_cselect_b32 s2, s2, s11 |
| ; CI-NEXT: s_bfe_u32 s6, s9, 0x100000 |
| ; CI-NEXT: s_cmp_lg_u32 s8, 0 |
| ; CI-NEXT: s_cselect_b32 s6, s11, s6 |
| ; CI-NEXT: s_cmp_lg_u32 s7, 0 |
| ; CI-NEXT: s_cselect_b32 s6, s6, s11 |
| ; CI-NEXT: s_lshl_b32 s6, s6, 16 |
| ; CI-NEXT: s_or_b32 s2, s2, s6 |
| ; CI-NEXT: s_bfe_u32 s6, s10, 0x100000 |
| ; CI-NEXT: s_cmp_lg_u32 s4, 0 |
| ; CI-NEXT: s_cselect_b32 s4, s11, s6 |
| ; CI-NEXT: s_cmp_lg_u32 s5, 0 |
| ; CI-NEXT: s_cselect_b32 s4, s4, s11 |
| ; CI-NEXT: s_bfe_u32 s5, s13, 0x100000 |
| ; CI-NEXT: s_cmp_lg_u32 s12, 0 |
| ; CI-NEXT: s_cselect_b32 s5, s11, s5 |
| ; CI-NEXT: s_cmp_lg_u32 s3, 0 |
| ; CI-NEXT: s_cselect_b32 s3, s5, s11 |
| ; CI-NEXT: s_lshl_b32 s3, s3, 16 |
| ; CI-NEXT: s_or_b32 s3, s4, s3 |
| ; CI-NEXT: v_mov_b32_e32 v0, s2 |
| ; CI-NEXT: v_mov_b32_e32 v1, s3 |
| ; CI-NEXT: s_mov_b32 s2, -1 |
| ; CI-NEXT: s_mov_b32 s3, 0xf000 |
| ; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: frem_v4f16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34 |
| ; VI-NEXT: s_mov_b32 s7, 1 |
| ; VI-NEXT: ; implicit-def: $sgpr6 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 |
| ; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x20 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_cvt_f32_f16_e64 v1, |s2| |
| ; VI-NEXT: v_cvt_f32_f16_e64 v0, |s4| |
| ; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v1, v0 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: s_cbranch_scc0 .LBB10_2 |
| ; VI-NEXT: ; %bb.1: ; %frem.else86 |
| ; VI-NEXT: s_and_b32 s6, s2, 0xffff8000 |
| ; VI-NEXT: v_cmp_eq_f32_e32 vcc, v1, v0 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: s_mov_b32 s7, 0 |
| ; VI-NEXT: s_cselect_b32 s6, s6, s2 |
| ; VI-NEXT: .LBB10_2: ; %Flow135 |
| ; VI-NEXT: s_xor_b32 s7, s7, 1 |
| ; VI-NEXT: s_cmp_lg_u32 s7, 0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB10_8 |
| ; VI-NEXT: ; %bb.3: ; %frem.compute85 |
| ; VI-NEXT: v_frexp_mant_f32_e32 v2, v1 |
| ; VI-NEXT: v_frexp_exp_i32_f32_e32 v1, v1 |
| ; VI-NEXT: v_readfirstlane_b32 s9, v1 |
| ; VI-NEXT: v_ldexp_f32 v1, v2, 11 |
| ; VI-NEXT: v_readfirstlane_b32 s8, v1 |
| ; VI-NEXT: v_frexp_mant_f32_e32 v1, v0 |
| ; VI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s10, v0 |
| ; VI-NEXT: v_ldexp_f32 v0, v1, 1 |
| ; VI-NEXT: v_div_scale_f32 v1, s[12:13], v0, v0, 1.0 |
| ; VI-NEXT: s_add_i32 s7, s9, -1 |
| ; VI-NEXT: s_add_i32 s6, s10, -1 |
| ; VI-NEXT: s_sub_i32 s7, s7, s6 |
| ; VI-NEXT: v_div_scale_f32 v2, s[12:13], 1.0, v0, 1.0 |
| ; VI-NEXT: s_cmp_lg_u64 s[12:13], 0 |
| ; VI-NEXT: v_rcp_f32_e32 v3, v1 |
| ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 |
| ; VI-NEXT: v_fma_f32 v3, v4, v3, v3 |
| ; VI-NEXT: v_mul_f32_e32 v4, v2, v3 |
| ; VI-NEXT: v_fma_f32 v5, -v1, v4, v2 |
| ; VI-NEXT: v_fma_f32 v4, v5, v3, v4 |
| ; VI-NEXT: v_fma_f32 v1, -v1, v4, v2 |
| ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; VI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 |
| ; VI-NEXT: s_cmp_le_i32 s7, 11 |
| ; VI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB10_6 |
| ; VI-NEXT: ; %bb.4: ; %frem.loop_body93.preheader |
| ; VI-NEXT: s_add_i32 s9, s9, 11 |
| ; VI-NEXT: s_sub_i32 s7, s9, s10 |
| ; VI-NEXT: .LBB10_5: ; %frem.loop_body93 |
| ; VI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; VI-NEXT: v_mul_f32_e32 v2, s8, v1 |
| ; VI-NEXT: v_rndne_f32_e32 v2, v2 |
| ; VI-NEXT: v_fma_f32 v2, -v2, v0, s8 |
| ; VI-NEXT: v_readfirstlane_b32 s9, v2 |
| ; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 |
| ; VI-NEXT: v_add_f32_e32 v2, v2, v0 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s10, v2 |
| ; VI-NEXT: s_cselect_b32 s9, s10, s9 |
| ; VI-NEXT: v_ldexp_f32 v2, s9, 11 |
| ; VI-NEXT: v_readfirstlane_b32 s10, v2 |
| ; VI-NEXT: s_add_i32 s7, s7, -11 |
| ; VI-NEXT: s_cmp_gt_i32 s7, 11 |
| ; VI-NEXT: s_mov_b32 s9, s8 |
| ; VI-NEXT: s_mov_b32 s8, s10 |
| ; VI-NEXT: s_cbranch_scc1 .LBB10_5 |
| ; VI-NEXT: s_branch .LBB10_7 |
| ; VI-NEXT: .LBB10_6: |
| ; VI-NEXT: s_mov_b32 s9, s8 |
| ; VI-NEXT: .LBB10_7: ; %frem.loop_exit94 |
| ; VI-NEXT: s_add_i32 s7, s7, -10 |
| ; VI-NEXT: v_mov_b32_e32 v2, s7 |
| ; VI-NEXT: v_ldexp_f32 v2, s9, v2 |
| ; VI-NEXT: v_mul_f32_e32 v1, v2, v1 |
| ; VI-NEXT: v_rndne_f32_e32 v1, v1 |
| ; VI-NEXT: v_fma_f32 v1, -v1, v0, v2 |
| ; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1 |
| ; VI-NEXT: v_add_f32_e32 v0, v1, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s7, v1 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s8, v0 |
| ; VI-NEXT: s_cselect_b32 s7, s8, s7 |
| ; VI-NEXT: v_mov_b32_e32 v0, s6 |
| ; VI-NEXT: v_ldexp_f32 v0, s7, v0 |
| ; VI-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; VI-NEXT: s_and_b32 s7, s2, 0xffff8000 |
| ; VI-NEXT: v_readfirstlane_b32 s6, v0 |
| ; VI-NEXT: s_and_b32 s6, s6, 0x7fff |
| ; VI-NEXT: s_or_b32 s6, s6, s7 |
| ; VI-NEXT: .LBB10_8: ; %Flow136 |
| ; VI-NEXT: s_lshr_b32 s7, s2, 16 |
| ; VI-NEXT: s_lshr_b32 s8, s4, 16 |
| ; VI-NEXT: v_cvt_f32_f16_e64 v1, |s7| |
| ; VI-NEXT: v_cvt_f32_f16_e64 v0, |s8| |
| ; VI-NEXT: s_mov_b32 s10, 1 |
| ; VI-NEXT: ; implicit-def: $sgpr9 |
| ; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v1, v0 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: s_cbranch_scc0 .LBB10_10 |
| ; VI-NEXT: ; %bb.9: ; %frem.else53 |
| ; VI-NEXT: s_and_b32 s9, s7, 0xffff8000 |
| ; VI-NEXT: v_cmp_eq_f32_e32 vcc, v1, v0 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: s_mov_b32 s10, 0 |
| ; VI-NEXT: s_cselect_b32 s9, s9, s7 |
| ; VI-NEXT: .LBB10_10: ; %Flow131 |
| ; VI-NEXT: s_xor_b32 s10, s10, 1 |
| ; VI-NEXT: s_cmp_lg_u32 s10, 0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB10_16 |
| ; VI-NEXT: ; %bb.11: ; %frem.compute52 |
| ; VI-NEXT: v_frexp_mant_f32_e32 v2, v1 |
| ; VI-NEXT: v_frexp_exp_i32_f32_e32 v1, v1 |
| ; VI-NEXT: v_readfirstlane_b32 s12, v1 |
| ; VI-NEXT: v_ldexp_f32 v1, v2, 11 |
| ; VI-NEXT: v_readfirstlane_b32 s11, v1 |
| ; VI-NEXT: v_frexp_mant_f32_e32 v1, v0 |
| ; VI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s13, v0 |
| ; VI-NEXT: v_ldexp_f32 v0, v1, 1 |
| ; VI-NEXT: v_div_scale_f32 v1, s[14:15], v0, v0, 1.0 |
| ; VI-NEXT: s_add_i32 s10, s12, -1 |
| ; VI-NEXT: s_add_i32 s9, s13, -1 |
| ; VI-NEXT: s_sub_i32 s10, s10, s9 |
| ; VI-NEXT: v_div_scale_f32 v2, s[14:15], 1.0, v0, 1.0 |
| ; VI-NEXT: s_cmp_lg_u64 s[14:15], 0 |
| ; VI-NEXT: v_rcp_f32_e32 v3, v1 |
| ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 |
| ; VI-NEXT: v_fma_f32 v3, v4, v3, v3 |
| ; VI-NEXT: v_mul_f32_e32 v4, v2, v3 |
| ; VI-NEXT: v_fma_f32 v5, -v1, v4, v2 |
| ; VI-NEXT: v_fma_f32 v4, v5, v3, v4 |
| ; VI-NEXT: v_fma_f32 v1, -v1, v4, v2 |
| ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; VI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 |
| ; VI-NEXT: s_cmp_le_i32 s10, 11 |
| ; VI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB10_14 |
| ; VI-NEXT: ; %bb.12: ; %frem.loop_body60.preheader |
| ; VI-NEXT: s_add_i32 s12, s12, 11 |
| ; VI-NEXT: s_sub_i32 s10, s12, s13 |
| ; VI-NEXT: .LBB10_13: ; %frem.loop_body60 |
| ; VI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; VI-NEXT: v_mul_f32_e32 v2, s11, v1 |
| ; VI-NEXT: v_rndne_f32_e32 v2, v2 |
| ; VI-NEXT: v_fma_f32 v2, -v2, v0, s11 |
| ; VI-NEXT: v_readfirstlane_b32 s12, v2 |
| ; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 |
| ; VI-NEXT: v_add_f32_e32 v2, v2, v0 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s13, v2 |
| ; VI-NEXT: s_cselect_b32 s12, s13, s12 |
| ; VI-NEXT: v_ldexp_f32 v2, s12, 11 |
| ; VI-NEXT: v_readfirstlane_b32 s13, v2 |
| ; VI-NEXT: s_add_i32 s10, s10, -11 |
| ; VI-NEXT: s_cmp_gt_i32 s10, 11 |
| ; VI-NEXT: s_mov_b32 s12, s11 |
| ; VI-NEXT: s_mov_b32 s11, s13 |
| ; VI-NEXT: s_cbranch_scc1 .LBB10_13 |
| ; VI-NEXT: s_branch .LBB10_15 |
| ; VI-NEXT: .LBB10_14: |
| ; VI-NEXT: s_mov_b32 s12, s11 |
| ; VI-NEXT: .LBB10_15: ; %frem.loop_exit61 |
| ; VI-NEXT: s_add_i32 s10, s10, -10 |
| ; VI-NEXT: v_mov_b32_e32 v2, s10 |
| ; VI-NEXT: v_ldexp_f32 v2, s12, v2 |
| ; VI-NEXT: v_mul_f32_e32 v1, v2, v1 |
| ; VI-NEXT: v_rndne_f32_e32 v1, v1 |
| ; VI-NEXT: v_fma_f32 v1, -v1, v0, v2 |
| ; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1 |
| ; VI-NEXT: v_add_f32_e32 v0, v1, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s10, v1 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s11, v0 |
| ; VI-NEXT: s_cselect_b32 s10, s11, s10 |
| ; VI-NEXT: v_mov_b32_e32 v0, s9 |
| ; VI-NEXT: v_ldexp_f32 v0, s10, v0 |
| ; VI-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; VI-NEXT: s_and_b32 s10, s7, 0xffff8000 |
| ; VI-NEXT: v_readfirstlane_b32 s9, v0 |
| ; VI-NEXT: s_and_b32 s9, s9, 0x7fff |
| ; VI-NEXT: s_or_b32 s9, s9, s10 |
| ; VI-NEXT: .LBB10_16: ; %Flow132 |
| ; VI-NEXT: v_cvt_f32_f16_e64 v1, |s3| |
| ; VI-NEXT: v_cvt_f32_f16_e64 v0, |s5| |
| ; VI-NEXT: s_mov_b32 s11, 1 |
| ; VI-NEXT: ; implicit-def: $sgpr10 |
| ; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v1, v0 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: s_cbranch_scc0 .LBB10_18 |
| ; VI-NEXT: ; %bb.17: ; %frem.else20 |
| ; VI-NEXT: s_and_b32 s10, s3, 0xffff8000 |
| ; VI-NEXT: v_cmp_eq_f32_e32 vcc, v1, v0 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: s_mov_b32 s11, 0 |
| ; VI-NEXT: s_cselect_b32 s10, s10, s3 |
| ; VI-NEXT: .LBB10_18: ; %Flow127 |
| ; VI-NEXT: s_xor_b32 s11, s11, 1 |
| ; VI-NEXT: s_cmp_lg_u32 s11, 0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB10_24 |
| ; VI-NEXT: ; %bb.19: ; %frem.compute19 |
| ; VI-NEXT: v_frexp_mant_f32_e32 v2, v1 |
| ; VI-NEXT: v_frexp_exp_i32_f32_e32 v1, v1 |
| ; VI-NEXT: v_readfirstlane_b32 s13, v1 |
| ; VI-NEXT: v_ldexp_f32 v1, v2, 11 |
| ; VI-NEXT: v_readfirstlane_b32 s12, v1 |
| ; VI-NEXT: v_frexp_mant_f32_e32 v1, v0 |
| ; VI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s14, v0 |
| ; VI-NEXT: v_ldexp_f32 v0, v1, 1 |
| ; VI-NEXT: v_div_scale_f32 v1, s[16:17], v0, v0, 1.0 |
| ; VI-NEXT: s_add_i32 s11, s13, -1 |
| ; VI-NEXT: s_add_i32 s10, s14, -1 |
| ; VI-NEXT: s_sub_i32 s11, s11, s10 |
| ; VI-NEXT: v_div_scale_f32 v2, s[16:17], 1.0, v0, 1.0 |
| ; VI-NEXT: s_cmp_lg_u64 s[16:17], 0 |
| ; VI-NEXT: v_rcp_f32_e32 v3, v1 |
| ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 |
| ; VI-NEXT: v_fma_f32 v3, v4, v3, v3 |
| ; VI-NEXT: v_mul_f32_e32 v4, v2, v3 |
| ; VI-NEXT: v_fma_f32 v5, -v1, v4, v2 |
| ; VI-NEXT: v_fma_f32 v4, v5, v3, v4 |
| ; VI-NEXT: v_fma_f32 v1, -v1, v4, v2 |
| ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; VI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 |
| ; VI-NEXT: s_cmp_le_i32 s11, 11 |
| ; VI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB10_22 |
| ; VI-NEXT: ; %bb.20: ; %frem.loop_body27.preheader |
| ; VI-NEXT: s_add_i32 s13, s13, 11 |
| ; VI-NEXT: s_sub_i32 s11, s13, s14 |
| ; VI-NEXT: .LBB10_21: ; %frem.loop_body27 |
| ; VI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; VI-NEXT: v_mul_f32_e32 v2, s12, v1 |
| ; VI-NEXT: v_rndne_f32_e32 v2, v2 |
| ; VI-NEXT: v_fma_f32 v2, -v2, v0, s12 |
| ; VI-NEXT: v_readfirstlane_b32 s13, v2 |
| ; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 |
| ; VI-NEXT: v_add_f32_e32 v2, v2, v0 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s14, v2 |
| ; VI-NEXT: s_cselect_b32 s13, s14, s13 |
| ; VI-NEXT: v_ldexp_f32 v2, s13, 11 |
| ; VI-NEXT: v_readfirstlane_b32 s14, v2 |
| ; VI-NEXT: s_add_i32 s11, s11, -11 |
| ; VI-NEXT: s_cmp_gt_i32 s11, 11 |
| ; VI-NEXT: s_mov_b32 s13, s12 |
| ; VI-NEXT: s_mov_b32 s12, s14 |
| ; VI-NEXT: s_cbranch_scc1 .LBB10_21 |
| ; VI-NEXT: s_branch .LBB10_23 |
| ; VI-NEXT: .LBB10_22: |
| ; VI-NEXT: s_mov_b32 s13, s12 |
| ; VI-NEXT: .LBB10_23: ; %frem.loop_exit28 |
| ; VI-NEXT: s_add_i32 s11, s11, -10 |
| ; VI-NEXT: v_mov_b32_e32 v2, s11 |
| ; VI-NEXT: v_ldexp_f32 v2, s13, v2 |
| ; VI-NEXT: v_mul_f32_e32 v1, v2, v1 |
| ; VI-NEXT: v_rndne_f32_e32 v1, v1 |
| ; VI-NEXT: v_fma_f32 v1, -v1, v0, v2 |
| ; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1 |
| ; VI-NEXT: v_add_f32_e32 v0, v1, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s11, v1 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s12, v0 |
| ; VI-NEXT: s_cselect_b32 s11, s12, s11 |
| ; VI-NEXT: v_mov_b32_e32 v0, s10 |
| ; VI-NEXT: v_ldexp_f32 v0, s11, v0 |
| ; VI-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; VI-NEXT: s_and_b32 s11, s3, 0xffff8000 |
| ; VI-NEXT: v_readfirstlane_b32 s10, v0 |
| ; VI-NEXT: s_and_b32 s10, s10, 0x7fff |
| ; VI-NEXT: s_or_b32 s10, s10, s11 |
| ; VI-NEXT: .LBB10_24: ; %Flow128 |
| ; VI-NEXT: s_lshr_b32 s11, s3, 16 |
| ; VI-NEXT: s_lshr_b32 s12, s5, 16 |
| ; VI-NEXT: v_cvt_f32_f16_e64 v1, |s11| |
| ; VI-NEXT: v_cvt_f32_f16_e64 v0, |s12| |
| ; VI-NEXT: s_mov_b32 s14, 1 |
| ; VI-NEXT: ; implicit-def: $sgpr13 |
| ; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v1, v0 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: s_cbranch_scc0 .LBB10_26 |
| ; VI-NEXT: ; %bb.25: ; %frem.else |
| ; VI-NEXT: s_and_b32 s13, s11, 0xffff8000 |
| ; VI-NEXT: v_cmp_eq_f32_e32 vcc, v1, v0 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: s_mov_b32 s14, 0 |
| ; VI-NEXT: s_cselect_b32 s13, s13, s11 |
| ; VI-NEXT: .LBB10_26: ; %Flow123 |
| ; VI-NEXT: s_xor_b32 s14, s14, 1 |
| ; VI-NEXT: s_cmp_lg_u32 s14, 0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB10_32 |
| ; VI-NEXT: ; %bb.27: ; %frem.compute |
| ; VI-NEXT: v_frexp_mant_f32_e32 v2, v1 |
| ; VI-NEXT: v_frexp_exp_i32_f32_e32 v1, v1 |
| ; VI-NEXT: v_readfirstlane_b32 s16, v1 |
| ; VI-NEXT: v_ldexp_f32 v1, v2, 11 |
| ; VI-NEXT: v_readfirstlane_b32 s15, v1 |
| ; VI-NEXT: v_frexp_mant_f32_e32 v1, v0 |
| ; VI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s17, v0 |
| ; VI-NEXT: v_ldexp_f32 v0, v1, 1 |
| ; VI-NEXT: v_div_scale_f32 v1, s[18:19], v0, v0, 1.0 |
| ; VI-NEXT: s_add_i32 s14, s16, -1 |
| ; VI-NEXT: s_add_i32 s13, s17, -1 |
| ; VI-NEXT: s_sub_i32 s14, s14, s13 |
| ; VI-NEXT: v_div_scale_f32 v2, s[18:19], 1.0, v0, 1.0 |
| ; VI-NEXT: s_cmp_lg_u64 s[18:19], 0 |
| ; VI-NEXT: v_rcp_f32_e32 v3, v1 |
| ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 |
| ; VI-NEXT: v_fma_f32 v3, v4, v3, v3 |
| ; VI-NEXT: v_mul_f32_e32 v4, v2, v3 |
| ; VI-NEXT: v_fma_f32 v5, -v1, v4, v2 |
| ; VI-NEXT: v_fma_f32 v4, v5, v3, v4 |
| ; VI-NEXT: v_fma_f32 v1, -v1, v4, v2 |
| ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; VI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 |
| ; VI-NEXT: s_cmp_le_i32 s14, 11 |
| ; VI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB10_30 |
| ; VI-NEXT: ; %bb.28: ; %frem.loop_body.preheader |
| ; VI-NEXT: s_add_i32 s16, s16, 11 |
| ; VI-NEXT: s_sub_i32 s14, s16, s17 |
| ; VI-NEXT: .LBB10_29: ; %frem.loop_body |
| ; VI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; VI-NEXT: v_mul_f32_e32 v2, s15, v1 |
| ; VI-NEXT: v_rndne_f32_e32 v2, v2 |
| ; VI-NEXT: v_fma_f32 v2, -v2, v0, s15 |
| ; VI-NEXT: v_readfirstlane_b32 s16, v2 |
| ; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 |
| ; VI-NEXT: v_add_f32_e32 v2, v2, v0 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s17, v2 |
| ; VI-NEXT: s_cselect_b32 s16, s17, s16 |
| ; VI-NEXT: v_ldexp_f32 v2, s16, 11 |
| ; VI-NEXT: v_readfirstlane_b32 s17, v2 |
| ; VI-NEXT: s_add_i32 s14, s14, -11 |
| ; VI-NEXT: s_cmp_gt_i32 s14, 11 |
| ; VI-NEXT: s_mov_b32 s16, s15 |
| ; VI-NEXT: s_mov_b32 s15, s17 |
| ; VI-NEXT: s_cbranch_scc1 .LBB10_29 |
| ; VI-NEXT: s_branch .LBB10_31 |
| ; VI-NEXT: .LBB10_30: |
| ; VI-NEXT: s_mov_b32 s16, s15 |
| ; VI-NEXT: .LBB10_31: ; %frem.loop_exit |
| ; VI-NEXT: s_add_i32 s14, s14, -10 |
| ; VI-NEXT: v_mov_b32_e32 v2, s14 |
| ; VI-NEXT: v_ldexp_f32 v2, s16, v2 |
| ; VI-NEXT: v_mul_f32_e32 v1, v2, v1 |
| ; VI-NEXT: v_rndne_f32_e32 v1, v1 |
| ; VI-NEXT: v_fma_f32 v1, -v1, v0, v2 |
| ; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1 |
| ; VI-NEXT: v_add_f32_e32 v0, v1, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s14, v1 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s15, v0 |
| ; VI-NEXT: s_cselect_b32 s14, s15, s14 |
| ; VI-NEXT: v_mov_b32_e32 v0, s13 |
| ; VI-NEXT: v_ldexp_f32 v0, s14, v0 |
| ; VI-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; VI-NEXT: s_and_b32 s14, s11, 0xffff8000 |
| ; VI-NEXT: v_readfirstlane_b32 s13, v0 |
| ; VI-NEXT: s_and_b32 s13, s13, 0x7fff |
| ; VI-NEXT: s_or_b32 s13, s13, s14 |
| ; VI-NEXT: .LBB10_32: ; %Flow124 |
| ; VI-NEXT: v_cmp_nlg_f16_e64 s[14:15], s4, 0 |
| ; VI-NEXT: v_mov_b32_e32 v0, 0x7c00 |
| ; VI-NEXT: s_cmp_lg_u64 s[14:15], 0 |
| ; VI-NEXT: v_cmp_nge_f16_e64 s[14:15], |s2|, v0 |
| ; VI-NEXT: s_cselect_b32 s16, 1, 0 |
| ; VI-NEXT: s_cmp_lg_u64 s[14:15], 0 |
| ; VI-NEXT: v_cmp_nlg_f16_e64 s[14:15], s8, 0 |
| ; VI-NEXT: s_cselect_b32 s18, 1, 0 |
| ; VI-NEXT: s_cmp_lg_u64 s[14:15], 0 |
| ; VI-NEXT: v_cmp_nge_f16_e64 s[14:15], |s7|, v0 |
| ; VI-NEXT: s_cselect_b32 s8, 1, 0 |
| ; VI-NEXT: s_cmp_lg_u64 s[14:15], 0 |
| ; VI-NEXT: v_cmp_nlg_f16_e64 s[4:5], s5, 0 |
| ; VI-NEXT: s_cselect_b32 s7, 1, 0 |
| ; VI-NEXT: s_cmp_lg_u64 s[4:5], 0 |
| ; VI-NEXT: v_cmp_nge_f16_e64 s[2:3], |s3|, v0 |
| ; VI-NEXT: s_cselect_b32 s4, 1, 0 |
| ; VI-NEXT: s_cmp_lg_u64 s[2:3], 0 |
| ; VI-NEXT: v_cmp_nlg_f16_e64 s[2:3], s12, 0 |
| ; VI-NEXT: s_cselect_b32 s5, 1, 0 |
| ; VI-NEXT: s_cmp_lg_u64 s[2:3], 0 |
| ; VI-NEXT: v_cmp_nge_f16_e64 s[2:3], |s11|, v0 |
| ; VI-NEXT: s_movk_i32 s17, 0x7e00 |
| ; VI-NEXT: s_cselect_b32 s12, 1, 0 |
| ; VI-NEXT: s_cmp_lg_u64 s[2:3], 0 |
| ; VI-NEXT: s_cselect_b32 s3, 1, 0 |
| ; VI-NEXT: s_bfe_u32 s11, s17, 0x100000 |
| ; VI-NEXT: s_bfe_u32 s2, s6, 0x100000 |
| ; VI-NEXT: s_cmp_lg_u32 s16, 0 |
| ; VI-NEXT: s_cselect_b32 s2, s11, s2 |
| ; VI-NEXT: s_cmp_lg_u32 s18, 0 |
| ; VI-NEXT: s_cselect_b32 s2, s2, s11 |
| ; VI-NEXT: s_bfe_u32 s6, s9, 0x100000 |
| ; VI-NEXT: s_cmp_lg_u32 s8, 0 |
| ; VI-NEXT: s_cselect_b32 s6, s11, s6 |
| ; VI-NEXT: s_cmp_lg_u32 s7, 0 |
| ; VI-NEXT: s_cselect_b32 s6, s6, s11 |
| ; VI-NEXT: s_lshl_b32 s6, s6, 16 |
| ; VI-NEXT: s_or_b32 s2, s2, s6 |
| ; VI-NEXT: s_bfe_u32 s6, s10, 0x100000 |
| ; VI-NEXT: s_cmp_lg_u32 s4, 0 |
| ; VI-NEXT: s_cselect_b32 s4, s11, s6 |
| ; VI-NEXT: s_cmp_lg_u32 s5, 0 |
| ; VI-NEXT: s_cselect_b32 s4, s4, s11 |
| ; VI-NEXT: s_bfe_u32 s5, s13, 0x100000 |
| ; VI-NEXT: s_cmp_lg_u32 s12, 0 |
| ; VI-NEXT: s_cselect_b32 s5, s11, s5 |
| ; VI-NEXT: s_cmp_lg_u32 s3, 0 |
| ; VI-NEXT: s_cselect_b32 s3, s5, s11 |
| ; VI-NEXT: s_lshl_b32 s3, s3, 16 |
| ; VI-NEXT: s_or_b32 s3, s4, s3 |
| ; VI-NEXT: v_mov_b32_e32 v0, s2 |
| ; VI-NEXT: v_mov_b32_e32 v1, s3 |
| ; VI-NEXT: v_mov_b32_e32 v3, s1 |
| ; VI-NEXT: v_mov_b32_e32 v2, s0 |
| ; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] |
| ; VI-NEXT: s_endpgm |
| %gep2 = getelementptr <4 x half>, ptr addrspace(1) %in2, i32 4 |
| %r0 = load <4 x half>, ptr addrspace(1) %in1, align 16 |
| %r1 = load <4 x half>, ptr addrspace(1) %gep2, align 16 |
| %r2 = frem <4 x half> %r0, %r1 |
| store <4 x half> %r2, ptr addrspace(1) %out, align 16 |
| ret void |
| } |
| |
| define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 { |
| ; CI-LABEL: frem_v2f32: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 |
| ; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 |
| ; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x8 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_mov_b32_e32 v0, s4 |
| ; CI-NEXT: v_cmp_ngt_f32_e64 s[6:7], |s2|, |v0| |
| ; CI-NEXT: s_or_b64 s[6:7], s[6:7], s[6:7] |
| ; CI-NEXT: s_mov_b32 s7, 1 |
| ; CI-NEXT: ; implicit-def: $sgpr6 |
| ; CI-NEXT: s_cbranch_scc0 .LBB11_2 |
| ; CI-NEXT: ; %bb.1: ; %frem.else16 |
| ; CI-NEXT: v_mov_b32_e32 v0, s4 |
| ; CI-NEXT: s_and_b32 s6, s2, 0x80000000 |
| ; CI-NEXT: v_cmp_eq_f32_e64 s[8:9], |s2|, |v0| |
| ; CI-NEXT: s_or_b64 s[8:9], s[8:9], s[8:9] |
| ; CI-NEXT: s_mov_b32 s7, 0 |
| ; CI-NEXT: s_cselect_b32 s6, s6, s2 |
| ; CI-NEXT: .LBB11_2: ; %Flow53 |
| ; CI-NEXT: s_xor_b32 s7, s7, 1 |
| ; CI-NEXT: s_cmp_lg_u32 s7, 0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB11_8 |
| ; CI-NEXT: ; %bb.3: ; %frem.compute15 |
| ; CI-NEXT: v_frexp_mant_f32_e64 v0, |s2| |
| ; CI-NEXT: v_ldexp_f32_e64 v0, v0, 12 |
| ; CI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s2| |
| ; CI-NEXT: v_readfirstlane_b32 s8, v0 |
| ; CI-NEXT: v_frexp_mant_f32_e64 v0, |s4| |
| ; CI-NEXT: v_readfirstlane_b32 s9, v1 |
| ; CI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s4| |
| ; CI-NEXT: v_ldexp_f32_e64 v0, v0, 1 |
| ; CI-NEXT: v_readfirstlane_b32 s10, v1 |
| ; CI-NEXT: v_div_scale_f32 v1, s[12:13], v0, v0, 1.0 |
| ; CI-NEXT: s_add_i32 s7, s9, -1 |
| ; CI-NEXT: s_add_i32 s6, s10, -1 |
| ; CI-NEXT: s_sub_i32 s7, s7, s6 |
| ; CI-NEXT: v_div_scale_f32 v2, s[12:13], 1.0, v0, 1.0 |
| ; CI-NEXT: s_or_b64 s[12:13], s[12:13], s[12:13] |
| ; CI-NEXT: v_rcp_f32_e32 v3, v1 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 |
| ; CI-NEXT: v_fma_f32 v3, v4, v3, v3 |
| ; CI-NEXT: v_mul_f32_e32 v4, v2, v3 |
| ; CI-NEXT: v_fma_f32 v5, -v1, v4, v2 |
| ; CI-NEXT: v_fma_f32 v4, v5, v3, v4 |
| ; CI-NEXT: v_fma_f32 v1, -v1, v4, v2 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; CI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 |
| ; CI-NEXT: s_cmp_le_i32 s7, 12 |
| ; CI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB11_6 |
| ; CI-NEXT: ; %bb.4: ; %frem.loop_body23.preheader |
| ; CI-NEXT: s_add_i32 s9, s9, 12 |
| ; CI-NEXT: s_sub_i32 s7, s9, s10 |
| ; CI-NEXT: .LBB11_5: ; %frem.loop_body23 |
| ; CI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; CI-NEXT: v_mul_f32_e32 v2, s8, v1 |
| ; CI-NEXT: v_rndne_f32_e32 v2, v2 |
| ; CI-NEXT: v_fma_f32 v2, -v2, v0, s8 |
| ; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 |
| ; CI-NEXT: v_readfirstlane_b32 s9, v2 |
| ; CI-NEXT: s_or_b64 s[10:11], vcc, vcc |
| ; CI-NEXT: v_add_f32_e32 v2, v2, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s10, v2 |
| ; CI-NEXT: s_cselect_b32 s9, s10, s9 |
| ; CI-NEXT: v_ldexp_f32_e64 v2, s9, 12 |
| ; CI-NEXT: v_readfirstlane_b32 s10, v2 |
| ; CI-NEXT: s_add_i32 s7, s7, -12 |
| ; CI-NEXT: s_cmp_gt_i32 s7, 12 |
| ; CI-NEXT: s_mov_b32 s9, s8 |
| ; CI-NEXT: s_mov_b32 s8, s10 |
| ; CI-NEXT: s_cbranch_scc1 .LBB11_5 |
| ; CI-NEXT: s_branch .LBB11_7 |
| ; CI-NEXT: .LBB11_6: |
| ; CI-NEXT: s_mov_b32 s9, s8 |
| ; CI-NEXT: .LBB11_7: ; %frem.loop_exit24 |
| ; CI-NEXT: s_add_i32 s7, s7, -11 |
| ; CI-NEXT: v_mov_b32_e32 v2, s7 |
| ; CI-NEXT: v_ldexp_f32_e32 v2, s9, v2 |
| ; CI-NEXT: v_mul_f32_e32 v1, v2, v1 |
| ; CI-NEXT: v_rndne_f32_e32 v1, v1 |
| ; CI-NEXT: v_fma_f32 v1, -v1, v0, v2 |
| ; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1 |
| ; CI-NEXT: s_or_b64 s[8:9], vcc, vcc |
| ; CI-NEXT: v_add_f32_e32 v0, v1, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s7, v1 |
| ; CI-NEXT: v_readfirstlane_b32 s8, v0 |
| ; CI-NEXT: s_cselect_b32 s7, s8, s7 |
| ; CI-NEXT: v_mov_b32_e32 v0, s6 |
| ; CI-NEXT: v_ldexp_f32_e32 v0, s7, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s6, v0 |
| ; CI-NEXT: s_bitset0_b32 s6, 31 |
| ; CI-NEXT: s_and_b32 s7, s2, 0x80000000 |
| ; CI-NEXT: s_or_b32 s6, s6, s7 |
| ; CI-NEXT: .LBB11_8: ; %Flow54 |
| ; CI-NEXT: v_mov_b32_e32 v0, s5 |
| ; CI-NEXT: v_cmp_ngt_f32_e64 s[8:9], |s3|, |v0| |
| ; CI-NEXT: s_or_b64 s[8:9], s[8:9], s[8:9] |
| ; CI-NEXT: s_mov_b32 s8, 1 |
| ; CI-NEXT: ; implicit-def: $sgpr7 |
| ; CI-NEXT: s_cbranch_scc0 .LBB11_10 |
| ; CI-NEXT: ; %bb.9: ; %frem.else |
| ; CI-NEXT: v_mov_b32_e32 v0, s5 |
| ; CI-NEXT: s_and_b32 s7, s3, 0x80000000 |
| ; CI-NEXT: v_cmp_eq_f32_e64 s[10:11], |s3|, |v0| |
| ; CI-NEXT: s_or_b64 s[10:11], s[10:11], s[10:11] |
| ; CI-NEXT: s_mov_b32 s8, 0 |
| ; CI-NEXT: s_cselect_b32 s7, s7, s3 |
| ; CI-NEXT: .LBB11_10: ; %Flow49 |
| ; CI-NEXT: s_xor_b32 s8, s8, 1 |
| ; CI-NEXT: s_cmp_lg_u32 s8, 0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB11_16 |
| ; CI-NEXT: ; %bb.11: ; %frem.compute |
| ; CI-NEXT: v_frexp_mant_f32_e64 v0, |s3| |
| ; CI-NEXT: v_ldexp_f32_e64 v0, v0, 12 |
| ; CI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s3| |
| ; CI-NEXT: v_readfirstlane_b32 s9, v0 |
| ; CI-NEXT: v_frexp_mant_f32_e64 v0, |s5| |
| ; CI-NEXT: v_readfirstlane_b32 s10, v1 |
| ; CI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s5| |
| ; CI-NEXT: v_ldexp_f32_e64 v0, v0, 1 |
| ; CI-NEXT: v_readfirstlane_b32 s11, v1 |
| ; CI-NEXT: v_div_scale_f32 v1, s[12:13], v0, v0, 1.0 |
| ; CI-NEXT: s_add_i32 s8, s10, -1 |
| ; CI-NEXT: s_add_i32 s7, s11, -1 |
| ; CI-NEXT: s_sub_i32 s8, s8, s7 |
| ; CI-NEXT: v_div_scale_f32 v2, s[12:13], 1.0, v0, 1.0 |
| ; CI-NEXT: s_or_b64 s[12:13], s[12:13], s[12:13] |
| ; CI-NEXT: v_rcp_f32_e32 v3, v1 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 |
| ; CI-NEXT: v_fma_f32 v3, v4, v3, v3 |
| ; CI-NEXT: v_mul_f32_e32 v4, v2, v3 |
| ; CI-NEXT: v_fma_f32 v5, -v1, v4, v2 |
| ; CI-NEXT: v_fma_f32 v4, v5, v3, v4 |
| ; CI-NEXT: v_fma_f32 v1, -v1, v4, v2 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; CI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 |
| ; CI-NEXT: s_cmp_le_i32 s8, 12 |
| ; CI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB11_14 |
| ; CI-NEXT: ; %bb.12: ; %frem.loop_body.preheader |
| ; CI-NEXT: s_add_i32 s10, s10, 12 |
| ; CI-NEXT: s_sub_i32 s8, s10, s11 |
| ; CI-NEXT: .LBB11_13: ; %frem.loop_body |
| ; CI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; CI-NEXT: v_mul_f32_e32 v2, s9, v1 |
| ; CI-NEXT: v_rndne_f32_e32 v2, v2 |
| ; CI-NEXT: v_fma_f32 v2, -v2, v0, s9 |
| ; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 |
| ; CI-NEXT: v_readfirstlane_b32 s12, v2 |
| ; CI-NEXT: s_or_b64 s[10:11], vcc, vcc |
| ; CI-NEXT: v_add_f32_e32 v2, v2, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s10, v2 |
| ; CI-NEXT: s_cselect_b32 s10, s10, s12 |
| ; CI-NEXT: v_ldexp_f32_e64 v2, s10, 12 |
| ; CI-NEXT: v_readfirstlane_b32 s11, v2 |
| ; CI-NEXT: s_add_i32 s8, s8, -12 |
| ; CI-NEXT: s_cmp_gt_i32 s8, 12 |
| ; CI-NEXT: s_mov_b32 s10, s9 |
| ; CI-NEXT: s_mov_b32 s9, s11 |
| ; CI-NEXT: s_cbranch_scc1 .LBB11_13 |
| ; CI-NEXT: s_branch .LBB11_15 |
| ; CI-NEXT: .LBB11_14: |
| ; CI-NEXT: s_mov_b32 s10, s9 |
| ; CI-NEXT: .LBB11_15: ; %frem.loop_exit |
| ; CI-NEXT: s_add_i32 s8, s8, -11 |
| ; CI-NEXT: v_mov_b32_e32 v2, s8 |
| ; CI-NEXT: v_ldexp_f32_e32 v2, s10, v2 |
| ; CI-NEXT: v_mul_f32_e32 v1, v2, v1 |
| ; CI-NEXT: v_rndne_f32_e32 v1, v1 |
| ; CI-NEXT: v_fma_f32 v1, -v1, v0, v2 |
| ; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1 |
| ; CI-NEXT: s_or_b64 s[8:9], vcc, vcc |
| ; CI-NEXT: v_add_f32_e32 v0, v1, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s10, v1 |
| ; CI-NEXT: v_readfirstlane_b32 s8, v0 |
| ; CI-NEXT: s_cselect_b32 s8, s8, s10 |
| ; CI-NEXT: v_mov_b32_e32 v0, s7 |
| ; CI-NEXT: v_ldexp_f32_e32 v0, s8, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s7, v0 |
| ; CI-NEXT: s_bitset0_b32 s7, 31 |
| ; CI-NEXT: s_and_b32 s8, s3, 0x80000000 |
| ; CI-NEXT: s_or_b32 s7, s7, s8 |
| ; CI-NEXT: .LBB11_16: ; %Flow50 |
| ; CI-NEXT: v_cmp_nlg_f32_e64 s[8:9], s4, 0 |
| ; CI-NEXT: s_or_b64 s[8:9], s[8:9], s[8:9] |
| ; CI-NEXT: v_mov_b32_e32 v0, 0x7f800000 |
| ; CI-NEXT: v_cmp_nge_f32_e64 s[8:9], |s2|, v0 |
| ; CI-NEXT: s_cselect_b32 s4, 0x7fc00000, s6 |
| ; CI-NEXT: s_or_b64 s[8:9], s[8:9], s[8:9] |
| ; CI-NEXT: s_cselect_b32 s2, s4, 0x7fc00000 |
| ; CI-NEXT: v_cmp_nlg_f32_e64 s[4:5], s5, 0 |
| ; CI-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5] |
| ; CI-NEXT: v_cmp_nge_f32_e64 s[4:5], |s3|, v0 |
| ; CI-NEXT: s_cselect_b32 s6, 0x7fc00000, s7 |
| ; CI-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5] |
| ; CI-NEXT: s_cselect_b32 s3, s6, 0x7fc00000 |
| ; CI-NEXT: v_mov_b32_e32 v0, s2 |
| ; CI-NEXT: v_mov_b32_e32 v1, s3 |
| ; CI-NEXT: s_mov_b32 s2, -1 |
| ; CI-NEXT: s_mov_b32 s3, 0xf000 |
| ; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: frem_v2f32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 |
| ; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x20 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v0, s4 |
| ; VI-NEXT: v_cmp_ngt_f32_e64 s[6:7], |s2|, |v0| |
| ; VI-NEXT: s_cmp_lg_u64 s[6:7], 0 |
| ; VI-NEXT: s_mov_b32 s7, 1 |
| ; VI-NEXT: ; implicit-def: $sgpr6 |
| ; VI-NEXT: s_cbranch_scc0 .LBB11_2 |
| ; VI-NEXT: ; %bb.1: ; %frem.else16 |
| ; VI-NEXT: v_mov_b32_e32 v0, s4 |
| ; VI-NEXT: s_and_b32 s6, s2, 0x80000000 |
| ; VI-NEXT: v_cmp_eq_f32_e64 s[8:9], |s2|, |v0| |
| ; VI-NEXT: s_cmp_lg_u64 s[8:9], 0 |
| ; VI-NEXT: s_mov_b32 s7, 0 |
| ; VI-NEXT: s_cselect_b32 s6, s6, s2 |
| ; VI-NEXT: .LBB11_2: ; %Flow53 |
| ; VI-NEXT: s_xor_b32 s7, s7, 1 |
| ; VI-NEXT: s_cmp_lg_u32 s7, 0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB11_8 |
| ; VI-NEXT: ; %bb.3: ; %frem.compute15 |
| ; VI-NEXT: v_frexp_mant_f32_e64 v0, |s2| |
| ; VI-NEXT: v_ldexp_f32 v0, v0, 12 |
| ; VI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s2| |
| ; VI-NEXT: v_readfirstlane_b32 s8, v0 |
| ; VI-NEXT: v_frexp_mant_f32_e64 v0, |s4| |
| ; VI-NEXT: v_readfirstlane_b32 s9, v1 |
| ; VI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s4| |
| ; VI-NEXT: v_ldexp_f32 v0, v0, 1 |
| ; VI-NEXT: v_readfirstlane_b32 s10, v1 |
| ; VI-NEXT: v_div_scale_f32 v1, s[12:13], v0, v0, 1.0 |
| ; VI-NEXT: s_add_i32 s7, s9, -1 |
| ; VI-NEXT: s_add_i32 s6, s10, -1 |
| ; VI-NEXT: s_sub_i32 s7, s7, s6 |
| ; VI-NEXT: v_div_scale_f32 v2, s[12:13], 1.0, v0, 1.0 |
| ; VI-NEXT: s_cmp_lg_u64 s[12:13], 0 |
| ; VI-NEXT: v_rcp_f32_e32 v3, v1 |
| ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 |
| ; VI-NEXT: v_fma_f32 v3, v4, v3, v3 |
| ; VI-NEXT: v_mul_f32_e32 v4, v2, v3 |
| ; VI-NEXT: v_fma_f32 v5, -v1, v4, v2 |
| ; VI-NEXT: v_fma_f32 v4, v5, v3, v4 |
| ; VI-NEXT: v_fma_f32 v1, -v1, v4, v2 |
| ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; VI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 |
| ; VI-NEXT: s_cmp_le_i32 s7, 12 |
| ; VI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB11_6 |
| ; VI-NEXT: ; %bb.4: ; %frem.loop_body23.preheader |
| ; VI-NEXT: s_add_i32 s9, s9, 12 |
| ; VI-NEXT: s_sub_i32 s7, s9, s10 |
| ; VI-NEXT: .LBB11_5: ; %frem.loop_body23 |
| ; VI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; VI-NEXT: v_mul_f32_e32 v2, s8, v1 |
| ; VI-NEXT: v_rndne_f32_e32 v2, v2 |
| ; VI-NEXT: v_fma_f32 v2, -v2, v0, s8 |
| ; VI-NEXT: v_readfirstlane_b32 s9, v2 |
| ; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 |
| ; VI-NEXT: v_add_f32_e32 v2, v2, v0 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s10, v2 |
| ; VI-NEXT: s_cselect_b32 s9, s10, s9 |
| ; VI-NEXT: v_ldexp_f32 v2, s9, 12 |
| ; VI-NEXT: v_readfirstlane_b32 s10, v2 |
| ; VI-NEXT: s_add_i32 s7, s7, -12 |
| ; VI-NEXT: s_cmp_gt_i32 s7, 12 |
| ; VI-NEXT: s_mov_b32 s9, s8 |
| ; VI-NEXT: s_mov_b32 s8, s10 |
| ; VI-NEXT: s_cbranch_scc1 .LBB11_5 |
| ; VI-NEXT: s_branch .LBB11_7 |
| ; VI-NEXT: .LBB11_6: |
| ; VI-NEXT: s_mov_b32 s9, s8 |
| ; VI-NEXT: .LBB11_7: ; %frem.loop_exit24 |
| ; VI-NEXT: s_add_i32 s7, s7, -11 |
| ; VI-NEXT: v_mov_b32_e32 v2, s7 |
| ; VI-NEXT: v_ldexp_f32 v2, s9, v2 |
| ; VI-NEXT: v_mul_f32_e32 v1, v2, v1 |
| ; VI-NEXT: v_rndne_f32_e32 v1, v1 |
| ; VI-NEXT: v_fma_f32 v1, -v1, v0, v2 |
| ; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1 |
| ; VI-NEXT: v_add_f32_e32 v0, v1, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s7, v1 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s8, v0 |
| ; VI-NEXT: s_cselect_b32 s7, s8, s7 |
| ; VI-NEXT: v_mov_b32_e32 v0, s6 |
| ; VI-NEXT: v_ldexp_f32 v0, s7, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s6, v0 |
| ; VI-NEXT: s_bitset0_b32 s6, 31 |
| ; VI-NEXT: s_and_b32 s7, s2, 0x80000000 |
| ; VI-NEXT: s_or_b32 s6, s6, s7 |
| ; VI-NEXT: .LBB11_8: ; %Flow54 |
| ; VI-NEXT: v_mov_b32_e32 v0, s5 |
| ; VI-NEXT: v_cmp_ngt_f32_e64 s[8:9], |s3|, |v0| |
| ; VI-NEXT: s_cmp_lg_u64 s[8:9], 0 |
| ; VI-NEXT: s_mov_b32 s8, 1 |
| ; VI-NEXT: ; implicit-def: $sgpr7 |
| ; VI-NEXT: s_cbranch_scc0 .LBB11_10 |
| ; VI-NEXT: ; %bb.9: ; %frem.else |
| ; VI-NEXT: v_mov_b32_e32 v0, s5 |
| ; VI-NEXT: s_and_b32 s7, s3, 0x80000000 |
| ; VI-NEXT: v_cmp_eq_f32_e64 s[10:11], |s3|, |v0| |
| ; VI-NEXT: s_cmp_lg_u64 s[10:11], 0 |
| ; VI-NEXT: s_mov_b32 s8, 0 |
| ; VI-NEXT: s_cselect_b32 s7, s7, s3 |
| ; VI-NEXT: .LBB11_10: ; %Flow49 |
| ; VI-NEXT: s_xor_b32 s8, s8, 1 |
| ; VI-NEXT: s_cmp_lg_u32 s8, 0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB11_16 |
| ; VI-NEXT: ; %bb.11: ; %frem.compute |
| ; VI-NEXT: v_frexp_mant_f32_e64 v0, |s3| |
| ; VI-NEXT: v_ldexp_f32 v0, v0, 12 |
| ; VI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s3| |
| ; VI-NEXT: v_readfirstlane_b32 s9, v0 |
| ; VI-NEXT: v_frexp_mant_f32_e64 v0, |s5| |
| ; VI-NEXT: v_readfirstlane_b32 s10, v1 |
| ; VI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s5| |
| ; VI-NEXT: v_ldexp_f32 v0, v0, 1 |
| ; VI-NEXT: v_readfirstlane_b32 s11, v1 |
| ; VI-NEXT: v_div_scale_f32 v1, s[12:13], v0, v0, 1.0 |
| ; VI-NEXT: s_add_i32 s8, s10, -1 |
| ; VI-NEXT: s_add_i32 s7, s11, -1 |
| ; VI-NEXT: s_sub_i32 s8, s8, s7 |
| ; VI-NEXT: v_div_scale_f32 v2, s[12:13], 1.0, v0, 1.0 |
| ; VI-NEXT: s_cmp_lg_u64 s[12:13], 0 |
| ; VI-NEXT: v_rcp_f32_e32 v3, v1 |
| ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 |
| ; VI-NEXT: v_fma_f32 v3, v4, v3, v3 |
| ; VI-NEXT: v_mul_f32_e32 v4, v2, v3 |
| ; VI-NEXT: v_fma_f32 v5, -v1, v4, v2 |
| ; VI-NEXT: v_fma_f32 v4, v5, v3, v4 |
| ; VI-NEXT: v_fma_f32 v1, -v1, v4, v2 |
| ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; VI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 |
| ; VI-NEXT: s_cmp_le_i32 s8, 12 |
| ; VI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB11_14 |
| ; VI-NEXT: ; %bb.12: ; %frem.loop_body.preheader |
| ; VI-NEXT: s_add_i32 s10, s10, 12 |
| ; VI-NEXT: s_sub_i32 s8, s10, s11 |
| ; VI-NEXT: .LBB11_13: ; %frem.loop_body |
| ; VI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; VI-NEXT: v_mul_f32_e32 v2, s9, v1 |
| ; VI-NEXT: v_rndne_f32_e32 v2, v2 |
| ; VI-NEXT: v_fma_f32 v2, -v2, v0, s9 |
| ; VI-NEXT: v_readfirstlane_b32 s10, v2 |
| ; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 |
| ; VI-NEXT: v_add_f32_e32 v2, v2, v0 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s11, v2 |
| ; VI-NEXT: s_cselect_b32 s10, s11, s10 |
| ; VI-NEXT: v_ldexp_f32 v2, s10, 12 |
| ; VI-NEXT: v_readfirstlane_b32 s11, v2 |
| ; VI-NEXT: s_add_i32 s8, s8, -12 |
| ; VI-NEXT: s_cmp_gt_i32 s8, 12 |
| ; VI-NEXT: s_mov_b32 s10, s9 |
| ; VI-NEXT: s_mov_b32 s9, s11 |
| ; VI-NEXT: s_cbranch_scc1 .LBB11_13 |
| ; VI-NEXT: s_branch .LBB11_15 |
| ; VI-NEXT: .LBB11_14: |
| ; VI-NEXT: s_mov_b32 s10, s9 |
| ; VI-NEXT: .LBB11_15: ; %frem.loop_exit |
| ; VI-NEXT: s_add_i32 s8, s8, -11 |
| ; VI-NEXT: v_mov_b32_e32 v2, s8 |
| ; VI-NEXT: v_ldexp_f32 v2, s10, v2 |
| ; VI-NEXT: v_mul_f32_e32 v1, v2, v1 |
| ; VI-NEXT: v_rndne_f32_e32 v1, v1 |
| ; VI-NEXT: v_fma_f32 v1, -v1, v0, v2 |
| ; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1 |
| ; VI-NEXT: v_add_f32_e32 v0, v1, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s8, v1 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s9, v0 |
| ; VI-NEXT: s_cselect_b32 s8, s9, s8 |
| ; VI-NEXT: v_mov_b32_e32 v0, s7 |
| ; VI-NEXT: v_ldexp_f32 v0, s8, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s7, v0 |
| ; VI-NEXT: s_bitset0_b32 s7, 31 |
| ; VI-NEXT: s_and_b32 s8, s3, 0x80000000 |
| ; VI-NEXT: s_or_b32 s7, s7, s8 |
| ; VI-NEXT: .LBB11_16: ; %Flow50 |
| ; VI-NEXT: v_cmp_nlg_f32_e64 s[8:9], s4, 0 |
| ; VI-NEXT: v_mov_b32_e32 v0, 0x7f800000 |
| ; VI-NEXT: s_cmp_lg_u64 s[8:9], 0 |
| ; VI-NEXT: v_cmp_nge_f32_e64 s[8:9], |s2|, v0 |
| ; VI-NEXT: s_cselect_b32 s4, 0x7fc00000, s6 |
| ; VI-NEXT: s_cmp_lg_u64 s[8:9], 0 |
| ; VI-NEXT: s_cselect_b32 s2, s4, 0x7fc00000 |
| ; VI-NEXT: v_cmp_nlg_f32_e64 s[4:5], s5, 0 |
| ; VI-NEXT: s_cmp_lg_u64 s[4:5], 0 |
| ; VI-NEXT: v_cmp_nge_f32_e64 s[4:5], |s3|, v0 |
| ; VI-NEXT: s_cselect_b32 s6, 0x7fc00000, s7 |
| ; VI-NEXT: s_cmp_lg_u64 s[4:5], 0 |
| ; VI-NEXT: s_cselect_b32 s3, s6, 0x7fc00000 |
| ; VI-NEXT: v_mov_b32_e32 v0, s2 |
| ; VI-NEXT: v_mov_b32_e32 v1, s3 |
| ; VI-NEXT: v_mov_b32_e32 v3, s1 |
| ; VI-NEXT: v_mov_b32_e32 v2, s0 |
| ; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] |
| ; VI-NEXT: s_endpgm |
| %gep2 = getelementptr <2 x float>, ptr addrspace(1) %in2, i32 4 |
| %r0 = load <2 x float>, ptr addrspace(1) %in1, align 8 |
| %r1 = load <2 x float>, ptr addrspace(1) %gep2, align 8 |
| %r2 = frem <2 x float> %r0, %r1 |
| store <2 x float> %r2, ptr addrspace(1) %out, align 8 |
| ret void |
| } |
| |
| define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 { |
| ; CI-LABEL: frem_v4f32: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 |
| ; CI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0 |
| ; CI-NEXT: s_load_dwordx4 s[8:11], s[8:9], 0x10 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_mov_b32_e32 v0, s8 |
| ; CI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |s4|, |v0| |
| ; CI-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3] |
| ; CI-NEXT: s_mov_b32 s3, 1 |
| ; CI-NEXT: ; implicit-def: $sgpr2 |
| ; CI-NEXT: s_cbranch_scc0 .LBB12_2 |
| ; CI-NEXT: ; %bb.1: ; %frem.else78 |
| ; CI-NEXT: v_mov_b32_e32 v0, s8 |
| ; CI-NEXT: s_and_b32 s2, s4, 0x80000000 |
| ; CI-NEXT: v_cmp_eq_f32_e64 s[12:13], |s4|, |v0| |
| ; CI-NEXT: s_or_b64 s[12:13], s[12:13], s[12:13] |
| ; CI-NEXT: s_mov_b32 s3, 0 |
| ; CI-NEXT: s_cselect_b32 s2, s2, s4 |
| ; CI-NEXT: .LBB12_2: ; %Flow127 |
| ; CI-NEXT: s_xor_b32 s3, s3, 1 |
| ; CI-NEXT: s_cmp_lg_u32 s3, 0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB12_8 |
| ; CI-NEXT: ; %bb.3: ; %frem.compute77 |
| ; CI-NEXT: v_frexp_mant_f32_e64 v0, |s4| |
| ; CI-NEXT: v_ldexp_f32_e64 v0, v0, 12 |
| ; CI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s4| |
| ; CI-NEXT: v_readfirstlane_b32 s12, v0 |
| ; CI-NEXT: v_frexp_mant_f32_e64 v0, |s8| |
| ; CI-NEXT: v_readfirstlane_b32 s13, v1 |
| ; CI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s8| |
| ; CI-NEXT: v_ldexp_f32_e64 v0, v0, 1 |
| ; CI-NEXT: v_readfirstlane_b32 s14, v1 |
| ; CI-NEXT: v_div_scale_f32 v1, s[16:17], v0, v0, 1.0 |
| ; CI-NEXT: s_add_i32 s3, s13, -1 |
| ; CI-NEXT: s_add_i32 s2, s14, -1 |
| ; CI-NEXT: s_sub_i32 s3, s3, s2 |
| ; CI-NEXT: v_div_scale_f32 v2, s[16:17], 1.0, v0, 1.0 |
| ; CI-NEXT: s_or_b64 s[16:17], s[16:17], s[16:17] |
| ; CI-NEXT: v_rcp_f32_e32 v3, v1 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 |
| ; CI-NEXT: v_fma_f32 v3, v4, v3, v3 |
| ; CI-NEXT: v_mul_f32_e32 v4, v2, v3 |
| ; CI-NEXT: v_fma_f32 v5, -v1, v4, v2 |
| ; CI-NEXT: v_fma_f32 v4, v5, v3, v4 |
| ; CI-NEXT: v_fma_f32 v1, -v1, v4, v2 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; CI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 |
| ; CI-NEXT: s_cmp_le_i32 s3, 12 |
| ; CI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB12_6 |
| ; CI-NEXT: ; %bb.4: ; %frem.loop_body85.preheader |
| ; CI-NEXT: s_add_i32 s13, s13, 12 |
| ; CI-NEXT: s_sub_i32 s3, s13, s14 |
| ; CI-NEXT: .LBB12_5: ; %frem.loop_body85 |
| ; CI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; CI-NEXT: v_mul_f32_e32 v2, s12, v1 |
| ; CI-NEXT: v_rndne_f32_e32 v2, v2 |
| ; CI-NEXT: v_fma_f32 v2, -v2, v0, s12 |
| ; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 |
| ; CI-NEXT: v_readfirstlane_b32 s13, v2 |
| ; CI-NEXT: s_or_b64 s[14:15], vcc, vcc |
| ; CI-NEXT: v_add_f32_e32 v2, v2, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s14, v2 |
| ; CI-NEXT: s_cselect_b32 s13, s14, s13 |
| ; CI-NEXT: v_ldexp_f32_e64 v2, s13, 12 |
| ; CI-NEXT: v_readfirstlane_b32 s14, v2 |
| ; CI-NEXT: s_add_i32 s3, s3, -12 |
| ; CI-NEXT: s_cmp_gt_i32 s3, 12 |
| ; CI-NEXT: s_mov_b32 s13, s12 |
| ; CI-NEXT: s_mov_b32 s12, s14 |
| ; CI-NEXT: s_cbranch_scc1 .LBB12_5 |
| ; CI-NEXT: s_branch .LBB12_7 |
| ; CI-NEXT: .LBB12_6: |
| ; CI-NEXT: s_mov_b32 s13, s12 |
| ; CI-NEXT: .LBB12_7: ; %frem.loop_exit86 |
| ; CI-NEXT: s_add_i32 s3, s3, -11 |
| ; CI-NEXT: v_mov_b32_e32 v2, s3 |
| ; CI-NEXT: v_ldexp_f32_e32 v2, s13, v2 |
| ; CI-NEXT: v_mul_f32_e32 v1, v2, v1 |
| ; CI-NEXT: v_rndne_f32_e32 v1, v1 |
| ; CI-NEXT: v_fma_f32 v1, -v1, v0, v2 |
| ; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1 |
| ; CI-NEXT: s_or_b64 s[12:13], vcc, vcc |
| ; CI-NEXT: v_add_f32_e32 v0, v1, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s3, v1 |
| ; CI-NEXT: v_readfirstlane_b32 s12, v0 |
| ; CI-NEXT: s_cselect_b32 s3, s12, s3 |
| ; CI-NEXT: v_mov_b32_e32 v0, s2 |
| ; CI-NEXT: v_ldexp_f32_e32 v0, s3, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s2, v0 |
| ; CI-NEXT: s_bitset0_b32 s2, 31 |
| ; CI-NEXT: s_and_b32 s3, s4, 0x80000000 |
| ; CI-NEXT: s_or_b32 s2, s2, s3 |
| ; CI-NEXT: .LBB12_8: ; %Flow128 |
| ; CI-NEXT: v_mov_b32_e32 v0, s9 |
| ; CI-NEXT: v_cmp_ngt_f32_e64 s[12:13], |s5|, |v0| |
| ; CI-NEXT: s_or_b64 s[12:13], s[12:13], s[12:13] |
| ; CI-NEXT: s_mov_b32 s12, 1 |
| ; CI-NEXT: ; implicit-def: $sgpr3 |
| ; CI-NEXT: s_cbranch_scc0 .LBB12_10 |
| ; CI-NEXT: ; %bb.9: ; %frem.else47 |
| ; CI-NEXT: v_mov_b32_e32 v0, s9 |
| ; CI-NEXT: s_and_b32 s3, s5, 0x80000000 |
| ; CI-NEXT: v_cmp_eq_f32_e64 s[14:15], |s5|, |v0| |
| ; CI-NEXT: s_or_b64 s[14:15], s[14:15], s[14:15] |
| ; CI-NEXT: s_mov_b32 s12, 0 |
| ; CI-NEXT: s_cselect_b32 s3, s3, s5 |
| ; CI-NEXT: .LBB12_10: ; %Flow123 |
| ; CI-NEXT: s_xor_b32 s12, s12, 1 |
| ; CI-NEXT: s_cmp_lg_u32 s12, 0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB12_16 |
| ; CI-NEXT: ; %bb.11: ; %frem.compute46 |
| ; CI-NEXT: v_frexp_mant_f32_e64 v0, |s5| |
| ; CI-NEXT: v_ldexp_f32_e64 v0, v0, 12 |
| ; CI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s5| |
| ; CI-NEXT: v_readfirstlane_b32 s13, v0 |
| ; CI-NEXT: v_frexp_mant_f32_e64 v0, |s9| |
| ; CI-NEXT: v_readfirstlane_b32 s14, v1 |
| ; CI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s9| |
| ; CI-NEXT: v_ldexp_f32_e64 v0, v0, 1 |
| ; CI-NEXT: v_readfirstlane_b32 s15, v1 |
| ; CI-NEXT: v_div_scale_f32 v1, s[16:17], v0, v0, 1.0 |
| ; CI-NEXT: s_add_i32 s12, s14, -1 |
| ; CI-NEXT: s_add_i32 s3, s15, -1 |
| ; CI-NEXT: s_sub_i32 s12, s12, s3 |
| ; CI-NEXT: v_div_scale_f32 v2, s[16:17], 1.0, v0, 1.0 |
| ; CI-NEXT: s_or_b64 s[16:17], s[16:17], s[16:17] |
| ; CI-NEXT: v_rcp_f32_e32 v3, v1 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 |
| ; CI-NEXT: v_fma_f32 v3, v4, v3, v3 |
| ; CI-NEXT: v_mul_f32_e32 v4, v2, v3 |
| ; CI-NEXT: v_fma_f32 v5, -v1, v4, v2 |
| ; CI-NEXT: v_fma_f32 v4, v5, v3, v4 |
| ; CI-NEXT: v_fma_f32 v1, -v1, v4, v2 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; CI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 |
| ; CI-NEXT: s_cmp_le_i32 s12, 12 |
| ; CI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB12_14 |
| ; CI-NEXT: ; %bb.12: ; %frem.loop_body54.preheader |
| ; CI-NEXT: s_add_i32 s14, s14, 12 |
| ; CI-NEXT: s_sub_i32 s12, s14, s15 |
| ; CI-NEXT: .LBB12_13: ; %frem.loop_body54 |
| ; CI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; CI-NEXT: v_mul_f32_e32 v2, s13, v1 |
| ; CI-NEXT: v_rndne_f32_e32 v2, v2 |
| ; CI-NEXT: v_fma_f32 v2, -v2, v0, s13 |
| ; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 |
| ; CI-NEXT: v_readfirstlane_b32 s16, v2 |
| ; CI-NEXT: s_or_b64 s[14:15], vcc, vcc |
| ; CI-NEXT: v_add_f32_e32 v2, v2, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s14, v2 |
| ; CI-NEXT: s_cselect_b32 s14, s14, s16 |
| ; CI-NEXT: v_ldexp_f32_e64 v2, s14, 12 |
| ; CI-NEXT: v_readfirstlane_b32 s15, v2 |
| ; CI-NEXT: s_add_i32 s12, s12, -12 |
| ; CI-NEXT: s_cmp_gt_i32 s12, 12 |
| ; CI-NEXT: s_mov_b32 s14, s13 |
| ; CI-NEXT: s_mov_b32 s13, s15 |
| ; CI-NEXT: s_cbranch_scc1 .LBB12_13 |
| ; CI-NEXT: s_branch .LBB12_15 |
| ; CI-NEXT: .LBB12_14: |
| ; CI-NEXT: s_mov_b32 s14, s13 |
| ; CI-NEXT: .LBB12_15: ; %frem.loop_exit55 |
| ; CI-NEXT: s_add_i32 s12, s12, -11 |
| ; CI-NEXT: v_mov_b32_e32 v2, s12 |
| ; CI-NEXT: v_ldexp_f32_e32 v2, s14, v2 |
| ; CI-NEXT: v_mul_f32_e32 v1, v2, v1 |
| ; CI-NEXT: v_rndne_f32_e32 v1, v1 |
| ; CI-NEXT: v_fma_f32 v1, -v1, v0, v2 |
| ; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1 |
| ; CI-NEXT: s_or_b64 s[12:13], vcc, vcc |
| ; CI-NEXT: v_add_f32_e32 v0, v1, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s14, v1 |
| ; CI-NEXT: v_readfirstlane_b32 s12, v0 |
| ; CI-NEXT: s_cselect_b32 s12, s12, s14 |
| ; CI-NEXT: v_mov_b32_e32 v0, s3 |
| ; CI-NEXT: v_ldexp_f32_e32 v0, s12, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s3, v0 |
| ; CI-NEXT: s_bitset0_b32 s3, 31 |
| ; CI-NEXT: s_and_b32 s12, s5, 0x80000000 |
| ; CI-NEXT: s_or_b32 s3, s3, s12 |
| ; CI-NEXT: .LBB12_16: ; %Flow124 |
| ; CI-NEXT: v_mov_b32_e32 v0, s10 |
| ; CI-NEXT: v_cmp_ngt_f32_e64 s[12:13], |s6|, |v0| |
| ; CI-NEXT: s_or_b64 s[12:13], s[12:13], s[12:13] |
| ; CI-NEXT: s_mov_b32 s13, 1 |
| ; CI-NEXT: ; implicit-def: $sgpr12 |
| ; CI-NEXT: s_cbranch_scc0 .LBB12_18 |
| ; CI-NEXT: ; %bb.17: ; %frem.else16 |
| ; CI-NEXT: v_mov_b32_e32 v0, s10 |
| ; CI-NEXT: s_and_b32 s12, s6, 0x80000000 |
| ; CI-NEXT: v_cmp_eq_f32_e64 s[14:15], |s6|, |v0| |
| ; CI-NEXT: s_or_b64 s[14:15], s[14:15], s[14:15] |
| ; CI-NEXT: s_mov_b32 s13, 0 |
| ; CI-NEXT: s_cselect_b32 s12, s12, s6 |
| ; CI-NEXT: .LBB12_18: ; %Flow119 |
| ; CI-NEXT: s_xor_b32 s13, s13, 1 |
| ; CI-NEXT: s_cmp_lg_u32 s13, 0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB12_24 |
| ; CI-NEXT: ; %bb.19: ; %frem.compute15 |
| ; CI-NEXT: v_frexp_mant_f32_e64 v0, |s6| |
| ; CI-NEXT: v_ldexp_f32_e64 v0, v0, 12 |
| ; CI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s6| |
| ; CI-NEXT: v_readfirstlane_b32 s14, v0 |
| ; CI-NEXT: v_frexp_mant_f32_e64 v0, |s10| |
| ; CI-NEXT: v_readfirstlane_b32 s15, v1 |
| ; CI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s10| |
| ; CI-NEXT: v_ldexp_f32_e64 v0, v0, 1 |
| ; CI-NEXT: v_readfirstlane_b32 s16, v1 |
| ; CI-NEXT: v_div_scale_f32 v1, s[18:19], v0, v0, 1.0 |
| ; CI-NEXT: s_add_i32 s13, s15, -1 |
| ; CI-NEXT: s_add_i32 s12, s16, -1 |
| ; CI-NEXT: s_sub_i32 s13, s13, s12 |
| ; CI-NEXT: v_div_scale_f32 v2, s[18:19], 1.0, v0, 1.0 |
| ; CI-NEXT: s_or_b64 s[18:19], s[18:19], s[18:19] |
| ; CI-NEXT: v_rcp_f32_e32 v3, v1 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 |
| ; CI-NEXT: v_fma_f32 v3, v4, v3, v3 |
| ; CI-NEXT: v_mul_f32_e32 v4, v2, v3 |
| ; CI-NEXT: v_fma_f32 v5, -v1, v4, v2 |
| ; CI-NEXT: v_fma_f32 v4, v5, v3, v4 |
| ; CI-NEXT: v_fma_f32 v1, -v1, v4, v2 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; CI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 |
| ; CI-NEXT: s_cmp_le_i32 s13, 12 |
| ; CI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB12_22 |
| ; CI-NEXT: ; %bb.20: ; %frem.loop_body23.preheader |
| ; CI-NEXT: s_add_i32 s15, s15, 12 |
| ; CI-NEXT: s_sub_i32 s13, s15, s16 |
| ; CI-NEXT: .LBB12_21: ; %frem.loop_body23 |
| ; CI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; CI-NEXT: v_mul_f32_e32 v2, s14, v1 |
| ; CI-NEXT: v_rndne_f32_e32 v2, v2 |
| ; CI-NEXT: v_fma_f32 v2, -v2, v0, s14 |
| ; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 |
| ; CI-NEXT: v_readfirstlane_b32 s15, v2 |
| ; CI-NEXT: s_or_b64 s[16:17], vcc, vcc |
| ; CI-NEXT: v_add_f32_e32 v2, v2, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s16, v2 |
| ; CI-NEXT: s_cselect_b32 s15, s16, s15 |
| ; CI-NEXT: v_ldexp_f32_e64 v2, s15, 12 |
| ; CI-NEXT: v_readfirstlane_b32 s16, v2 |
| ; CI-NEXT: s_add_i32 s13, s13, -12 |
| ; CI-NEXT: s_cmp_gt_i32 s13, 12 |
| ; CI-NEXT: s_mov_b32 s15, s14 |
| ; CI-NEXT: s_mov_b32 s14, s16 |
| ; CI-NEXT: s_cbranch_scc1 .LBB12_21 |
| ; CI-NEXT: s_branch .LBB12_23 |
| ; CI-NEXT: .LBB12_22: |
| ; CI-NEXT: s_mov_b32 s15, s14 |
| ; CI-NEXT: .LBB12_23: ; %frem.loop_exit24 |
| ; CI-NEXT: s_add_i32 s13, s13, -11 |
| ; CI-NEXT: v_mov_b32_e32 v2, s13 |
| ; CI-NEXT: v_ldexp_f32_e32 v2, s15, v2 |
| ; CI-NEXT: v_mul_f32_e32 v1, v2, v1 |
| ; CI-NEXT: v_rndne_f32_e32 v1, v1 |
| ; CI-NEXT: v_fma_f32 v1, -v1, v0, v2 |
| ; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1 |
| ; CI-NEXT: s_or_b64 s[14:15], vcc, vcc |
| ; CI-NEXT: v_add_f32_e32 v0, v1, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s13, v1 |
| ; CI-NEXT: v_readfirstlane_b32 s14, v0 |
| ; CI-NEXT: s_cselect_b32 s13, s14, s13 |
| ; CI-NEXT: v_mov_b32_e32 v0, s12 |
| ; CI-NEXT: v_ldexp_f32_e32 v0, s13, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s12, v0 |
| ; CI-NEXT: s_bitset0_b32 s12, 31 |
| ; CI-NEXT: s_and_b32 s13, s6, 0x80000000 |
| ; CI-NEXT: s_or_b32 s12, s12, s13 |
| ; CI-NEXT: .LBB12_24: ; %Flow120 |
| ; CI-NEXT: v_mov_b32_e32 v0, s11 |
| ; CI-NEXT: v_cmp_ngt_f32_e64 s[14:15], |s7|, |v0| |
| ; CI-NEXT: s_or_b64 s[14:15], s[14:15], s[14:15] |
| ; CI-NEXT: s_mov_b32 s14, 1 |
| ; CI-NEXT: ; implicit-def: $sgpr13 |
| ; CI-NEXT: s_cbranch_scc0 .LBB12_26 |
| ; CI-NEXT: ; %bb.25: ; %frem.else |
| ; CI-NEXT: v_mov_b32_e32 v0, s11 |
| ; CI-NEXT: s_and_b32 s13, s7, 0x80000000 |
| ; CI-NEXT: v_cmp_eq_f32_e64 s[16:17], |s7|, |v0| |
| ; CI-NEXT: s_or_b64 s[16:17], s[16:17], s[16:17] |
| ; CI-NEXT: s_mov_b32 s14, 0 |
| ; CI-NEXT: s_cselect_b32 s13, s13, s7 |
| ; CI-NEXT: .LBB12_26: ; %Flow115 |
| ; CI-NEXT: s_xor_b32 s14, s14, 1 |
| ; CI-NEXT: s_cmp_lg_u32 s14, 0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB12_32 |
| ; CI-NEXT: ; %bb.27: ; %frem.compute |
| ; CI-NEXT: v_frexp_mant_f32_e64 v0, |s7| |
| ; CI-NEXT: v_ldexp_f32_e64 v0, v0, 12 |
| ; CI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s7| |
| ; CI-NEXT: v_readfirstlane_b32 s15, v0 |
| ; CI-NEXT: v_frexp_mant_f32_e64 v0, |s11| |
| ; CI-NEXT: v_readfirstlane_b32 s16, v1 |
| ; CI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s11| |
| ; CI-NEXT: v_ldexp_f32_e64 v0, v0, 1 |
| ; CI-NEXT: v_readfirstlane_b32 s17, v1 |
| ; CI-NEXT: v_div_scale_f32 v1, s[18:19], v0, v0, 1.0 |
| ; CI-NEXT: s_add_i32 s14, s16, -1 |
| ; CI-NEXT: s_add_i32 s13, s17, -1 |
| ; CI-NEXT: s_sub_i32 s14, s14, s13 |
| ; CI-NEXT: v_div_scale_f32 v2, s[18:19], 1.0, v0, 1.0 |
| ; CI-NEXT: s_or_b64 s[18:19], s[18:19], s[18:19] |
| ; CI-NEXT: v_rcp_f32_e32 v3, v1 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 |
| ; CI-NEXT: v_fma_f32 v3, v4, v3, v3 |
| ; CI-NEXT: v_mul_f32_e32 v4, v2, v3 |
| ; CI-NEXT: v_fma_f32 v5, -v1, v4, v2 |
| ; CI-NEXT: v_fma_f32 v4, v5, v3, v4 |
| ; CI-NEXT: v_fma_f32 v1, -v1, v4, v2 |
| ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; CI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 |
| ; CI-NEXT: s_cmp_le_i32 s14, 12 |
| ; CI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB12_30 |
| ; CI-NEXT: ; %bb.28: ; %frem.loop_body.preheader |
| ; CI-NEXT: s_add_i32 s16, s16, 12 |
| ; CI-NEXT: s_sub_i32 s14, s16, s17 |
| ; CI-NEXT: .LBB12_29: ; %frem.loop_body |
| ; CI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; CI-NEXT: v_mul_f32_e32 v2, s15, v1 |
| ; CI-NEXT: v_rndne_f32_e32 v2, v2 |
| ; CI-NEXT: v_fma_f32 v2, -v2, v0, s15 |
| ; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 |
| ; CI-NEXT: v_readfirstlane_b32 s18, v2 |
| ; CI-NEXT: s_or_b64 s[16:17], vcc, vcc |
| ; CI-NEXT: v_add_f32_e32 v2, v2, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s16, v2 |
| ; CI-NEXT: s_cselect_b32 s16, s16, s18 |
| ; CI-NEXT: v_ldexp_f32_e64 v2, s16, 12 |
| ; CI-NEXT: v_readfirstlane_b32 s17, v2 |
| ; CI-NEXT: s_add_i32 s14, s14, -12 |
| ; CI-NEXT: s_cmp_gt_i32 s14, 12 |
| ; CI-NEXT: s_mov_b32 s16, s15 |
| ; CI-NEXT: s_mov_b32 s15, s17 |
| ; CI-NEXT: s_cbranch_scc1 .LBB12_29 |
| ; CI-NEXT: s_branch .LBB12_31 |
| ; CI-NEXT: .LBB12_30: |
| ; CI-NEXT: s_mov_b32 s16, s15 |
| ; CI-NEXT: .LBB12_31: ; %frem.loop_exit |
| ; CI-NEXT: s_add_i32 s14, s14, -11 |
| ; CI-NEXT: v_mov_b32_e32 v2, s14 |
| ; CI-NEXT: v_ldexp_f32_e32 v2, s16, v2 |
| ; CI-NEXT: v_mul_f32_e32 v1, v2, v1 |
| ; CI-NEXT: v_rndne_f32_e32 v1, v1 |
| ; CI-NEXT: v_fma_f32 v1, -v1, v0, v2 |
| ; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1 |
| ; CI-NEXT: s_or_b64 s[14:15], vcc, vcc |
| ; CI-NEXT: v_add_f32_e32 v0, v1, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s16, v1 |
| ; CI-NEXT: v_readfirstlane_b32 s14, v0 |
| ; CI-NEXT: s_cselect_b32 s14, s14, s16 |
| ; CI-NEXT: v_mov_b32_e32 v0, s13 |
| ; CI-NEXT: v_ldexp_f32_e32 v0, s14, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s13, v0 |
| ; CI-NEXT: s_bitset0_b32 s13, 31 |
| ; CI-NEXT: s_and_b32 s14, s7, 0x80000000 |
| ; CI-NEXT: s_or_b32 s13, s13, s14 |
| ; CI-NEXT: .LBB12_32: ; %Flow116 |
| ; CI-NEXT: v_cmp_nlg_f32_e64 s[14:15], s8, 0 |
| ; CI-NEXT: s_or_b64 s[14:15], s[14:15], s[14:15] |
| ; CI-NEXT: v_mov_b32_e32 v0, 0x7f800000 |
| ; CI-NEXT: v_cmp_nge_f32_e64 s[14:15], |s4|, v0 |
| ; CI-NEXT: s_cselect_b32 s2, 0x7fc00000, s2 |
| ; CI-NEXT: s_or_b64 s[14:15], s[14:15], s[14:15] |
| ; CI-NEXT: v_cmp_nlg_f32_e64 s[8:9], s9, 0 |
| ; CI-NEXT: s_cselect_b32 s4, s2, 0x7fc00000 |
| ; CI-NEXT: s_or_b64 s[8:9], s[8:9], s[8:9] |
| ; CI-NEXT: s_cselect_b32 s8, 0x7fc00000, s3 |
| ; CI-NEXT: v_cmp_nge_f32_e64 s[2:3], |s5|, v0 |
| ; CI-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3] |
| ; CI-NEXT: v_cmp_nlg_f32_e64 s[2:3], s10, 0 |
| ; CI-NEXT: s_cselect_b32 s5, s8, 0x7fc00000 |
| ; CI-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3] |
| ; CI-NEXT: v_cmp_nge_f32_e64 s[2:3], |s6|, v0 |
| ; CI-NEXT: s_cselect_b32 s8, 0x7fc00000, s12 |
| ; CI-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3] |
| ; CI-NEXT: v_cmp_nlg_f32_e64 s[2:3], s11, 0 |
| ; CI-NEXT: s_cselect_b32 s6, s8, 0x7fc00000 |
| ; CI-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3] |
| ; CI-NEXT: v_cmp_nge_f32_e64 s[2:3], |s7|, v0 |
| ; CI-NEXT: s_cselect_b32 s8, 0x7fc00000, s13 |
| ; CI-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3] |
| ; CI-NEXT: s_cselect_b32 s7, s8, 0x7fc00000 |
| ; CI-NEXT: v_mov_b32_e32 v0, s4 |
| ; CI-NEXT: v_mov_b32_e32 v1, s5 |
| ; CI-NEXT: v_mov_b32_e32 v2, s6 |
| ; CI-NEXT: v_mov_b32_e32 v3, s7 |
| ; CI-NEXT: s_mov_b32 s2, -1 |
| ; CI-NEXT: s_mov_b32 s3, 0xf000 |
| ; CI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: frem_v4f32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; VI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x34 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0 |
| ; VI-NEXT: s_load_dwordx4 s[8:11], s[8:9], 0x40 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v0, s8 |
| ; VI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |s4|, |v0| |
| ; VI-NEXT: s_cmp_lg_u64 s[2:3], 0 |
| ; VI-NEXT: s_mov_b32 s3, 1 |
| ; VI-NEXT: ; implicit-def: $sgpr2 |
| ; VI-NEXT: s_cbranch_scc0 .LBB12_2 |
| ; VI-NEXT: ; %bb.1: ; %frem.else78 |
| ; VI-NEXT: v_mov_b32_e32 v0, s8 |
| ; VI-NEXT: s_and_b32 s2, s4, 0x80000000 |
| ; VI-NEXT: v_cmp_eq_f32_e64 s[12:13], |s4|, |v0| |
| ; VI-NEXT: s_cmp_lg_u64 s[12:13], 0 |
| ; VI-NEXT: s_mov_b32 s3, 0 |
| ; VI-NEXT: s_cselect_b32 s2, s2, s4 |
| ; VI-NEXT: .LBB12_2: ; %Flow127 |
| ; VI-NEXT: s_xor_b32 s3, s3, 1 |
| ; VI-NEXT: s_cmp_lg_u32 s3, 0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB12_8 |
| ; VI-NEXT: ; %bb.3: ; %frem.compute77 |
| ; VI-NEXT: v_frexp_mant_f32_e64 v0, |s4| |
| ; VI-NEXT: v_ldexp_f32 v0, v0, 12 |
| ; VI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s4| |
| ; VI-NEXT: v_readfirstlane_b32 s12, v0 |
| ; VI-NEXT: v_frexp_mant_f32_e64 v0, |s8| |
| ; VI-NEXT: v_readfirstlane_b32 s13, v1 |
| ; VI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s8| |
| ; VI-NEXT: v_ldexp_f32 v0, v0, 1 |
| ; VI-NEXT: v_readfirstlane_b32 s14, v1 |
| ; VI-NEXT: v_div_scale_f32 v1, s[16:17], v0, v0, 1.0 |
| ; VI-NEXT: s_add_i32 s3, s13, -1 |
| ; VI-NEXT: s_add_i32 s2, s14, -1 |
| ; VI-NEXT: s_sub_i32 s3, s3, s2 |
| ; VI-NEXT: v_div_scale_f32 v2, s[16:17], 1.0, v0, 1.0 |
| ; VI-NEXT: s_cmp_lg_u64 s[16:17], 0 |
| ; VI-NEXT: v_rcp_f32_e32 v3, v1 |
| ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 |
| ; VI-NEXT: v_fma_f32 v3, v4, v3, v3 |
| ; VI-NEXT: v_mul_f32_e32 v4, v2, v3 |
| ; VI-NEXT: v_fma_f32 v5, -v1, v4, v2 |
| ; VI-NEXT: v_fma_f32 v4, v5, v3, v4 |
| ; VI-NEXT: v_fma_f32 v1, -v1, v4, v2 |
| ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; VI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 |
| ; VI-NEXT: s_cmp_le_i32 s3, 12 |
| ; VI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB12_6 |
| ; VI-NEXT: ; %bb.4: ; %frem.loop_body85.preheader |
| ; VI-NEXT: s_add_i32 s13, s13, 12 |
| ; VI-NEXT: s_sub_i32 s3, s13, s14 |
| ; VI-NEXT: .LBB12_5: ; %frem.loop_body85 |
| ; VI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; VI-NEXT: v_mul_f32_e32 v2, s12, v1 |
| ; VI-NEXT: v_rndne_f32_e32 v2, v2 |
| ; VI-NEXT: v_fma_f32 v2, -v2, v0, s12 |
| ; VI-NEXT: v_readfirstlane_b32 s13, v2 |
| ; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 |
| ; VI-NEXT: v_add_f32_e32 v2, v2, v0 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s14, v2 |
| ; VI-NEXT: s_cselect_b32 s13, s14, s13 |
| ; VI-NEXT: v_ldexp_f32 v2, s13, 12 |
| ; VI-NEXT: v_readfirstlane_b32 s14, v2 |
| ; VI-NEXT: s_add_i32 s3, s3, -12 |
| ; VI-NEXT: s_cmp_gt_i32 s3, 12 |
| ; VI-NEXT: s_mov_b32 s13, s12 |
| ; VI-NEXT: s_mov_b32 s12, s14 |
| ; VI-NEXT: s_cbranch_scc1 .LBB12_5 |
| ; VI-NEXT: s_branch .LBB12_7 |
| ; VI-NEXT: .LBB12_6: |
| ; VI-NEXT: s_mov_b32 s13, s12 |
| ; VI-NEXT: .LBB12_7: ; %frem.loop_exit86 |
| ; VI-NEXT: s_add_i32 s3, s3, -11 |
| ; VI-NEXT: v_mov_b32_e32 v2, s3 |
| ; VI-NEXT: v_ldexp_f32 v2, s13, v2 |
| ; VI-NEXT: v_mul_f32_e32 v1, v2, v1 |
| ; VI-NEXT: v_rndne_f32_e32 v1, v1 |
| ; VI-NEXT: v_fma_f32 v1, -v1, v0, v2 |
| ; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1 |
| ; VI-NEXT: v_add_f32_e32 v0, v1, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s3, v1 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s12, v0 |
| ; VI-NEXT: s_cselect_b32 s3, s12, s3 |
| ; VI-NEXT: v_mov_b32_e32 v0, s2 |
| ; VI-NEXT: v_ldexp_f32 v0, s3, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s2, v0 |
| ; VI-NEXT: s_bitset0_b32 s2, 31 |
| ; VI-NEXT: s_and_b32 s3, s4, 0x80000000 |
| ; VI-NEXT: s_or_b32 s2, s2, s3 |
| ; VI-NEXT: .LBB12_8: ; %Flow128 |
| ; VI-NEXT: v_mov_b32_e32 v0, s9 |
| ; VI-NEXT: v_cmp_ngt_f32_e64 s[12:13], |s5|, |v0| |
| ; VI-NEXT: s_cmp_lg_u64 s[12:13], 0 |
| ; VI-NEXT: s_mov_b32 s12, 1 |
| ; VI-NEXT: ; implicit-def: $sgpr3 |
| ; VI-NEXT: s_cbranch_scc0 .LBB12_10 |
| ; VI-NEXT: ; %bb.9: ; %frem.else47 |
| ; VI-NEXT: v_mov_b32_e32 v0, s9 |
| ; VI-NEXT: s_and_b32 s3, s5, 0x80000000 |
| ; VI-NEXT: v_cmp_eq_f32_e64 s[14:15], |s5|, |v0| |
| ; VI-NEXT: s_cmp_lg_u64 s[14:15], 0 |
| ; VI-NEXT: s_mov_b32 s12, 0 |
| ; VI-NEXT: s_cselect_b32 s3, s3, s5 |
| ; VI-NEXT: .LBB12_10: ; %Flow123 |
| ; VI-NEXT: s_xor_b32 s12, s12, 1 |
| ; VI-NEXT: s_cmp_lg_u32 s12, 0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB12_16 |
| ; VI-NEXT: ; %bb.11: ; %frem.compute46 |
| ; VI-NEXT: v_frexp_mant_f32_e64 v0, |s5| |
| ; VI-NEXT: v_ldexp_f32 v0, v0, 12 |
| ; VI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s5| |
| ; VI-NEXT: v_readfirstlane_b32 s13, v0 |
| ; VI-NEXT: v_frexp_mant_f32_e64 v0, |s9| |
| ; VI-NEXT: v_readfirstlane_b32 s14, v1 |
| ; VI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s9| |
| ; VI-NEXT: v_ldexp_f32 v0, v0, 1 |
| ; VI-NEXT: v_readfirstlane_b32 s15, v1 |
| ; VI-NEXT: v_div_scale_f32 v1, s[16:17], v0, v0, 1.0 |
| ; VI-NEXT: s_add_i32 s12, s14, -1 |
| ; VI-NEXT: s_add_i32 s3, s15, -1 |
| ; VI-NEXT: s_sub_i32 s12, s12, s3 |
| ; VI-NEXT: v_div_scale_f32 v2, s[16:17], 1.0, v0, 1.0 |
| ; VI-NEXT: s_cmp_lg_u64 s[16:17], 0 |
| ; VI-NEXT: v_rcp_f32_e32 v3, v1 |
| ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 |
| ; VI-NEXT: v_fma_f32 v3, v4, v3, v3 |
| ; VI-NEXT: v_mul_f32_e32 v4, v2, v3 |
| ; VI-NEXT: v_fma_f32 v5, -v1, v4, v2 |
| ; VI-NEXT: v_fma_f32 v4, v5, v3, v4 |
| ; VI-NEXT: v_fma_f32 v1, -v1, v4, v2 |
| ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; VI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 |
| ; VI-NEXT: s_cmp_le_i32 s12, 12 |
| ; VI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB12_14 |
| ; VI-NEXT: ; %bb.12: ; %frem.loop_body54.preheader |
| ; VI-NEXT: s_add_i32 s14, s14, 12 |
| ; VI-NEXT: s_sub_i32 s12, s14, s15 |
| ; VI-NEXT: .LBB12_13: ; %frem.loop_body54 |
| ; VI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; VI-NEXT: v_mul_f32_e32 v2, s13, v1 |
| ; VI-NEXT: v_rndne_f32_e32 v2, v2 |
| ; VI-NEXT: v_fma_f32 v2, -v2, v0, s13 |
| ; VI-NEXT: v_readfirstlane_b32 s14, v2 |
| ; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 |
| ; VI-NEXT: v_add_f32_e32 v2, v2, v0 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s15, v2 |
| ; VI-NEXT: s_cselect_b32 s14, s15, s14 |
| ; VI-NEXT: v_ldexp_f32 v2, s14, 12 |
| ; VI-NEXT: v_readfirstlane_b32 s15, v2 |
| ; VI-NEXT: s_add_i32 s12, s12, -12 |
| ; VI-NEXT: s_cmp_gt_i32 s12, 12 |
| ; VI-NEXT: s_mov_b32 s14, s13 |
| ; VI-NEXT: s_mov_b32 s13, s15 |
| ; VI-NEXT: s_cbranch_scc1 .LBB12_13 |
| ; VI-NEXT: s_branch .LBB12_15 |
| ; VI-NEXT: .LBB12_14: |
| ; VI-NEXT: s_mov_b32 s14, s13 |
| ; VI-NEXT: .LBB12_15: ; %frem.loop_exit55 |
| ; VI-NEXT: s_add_i32 s12, s12, -11 |
| ; VI-NEXT: v_mov_b32_e32 v2, s12 |
| ; VI-NEXT: v_ldexp_f32 v2, s14, v2 |
| ; VI-NEXT: v_mul_f32_e32 v1, v2, v1 |
| ; VI-NEXT: v_rndne_f32_e32 v1, v1 |
| ; VI-NEXT: v_fma_f32 v1, -v1, v0, v2 |
| ; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1 |
| ; VI-NEXT: v_add_f32_e32 v0, v1, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s12, v1 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s13, v0 |
| ; VI-NEXT: s_cselect_b32 s12, s13, s12 |
| ; VI-NEXT: v_mov_b32_e32 v0, s3 |
| ; VI-NEXT: v_ldexp_f32 v0, s12, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s3, v0 |
| ; VI-NEXT: s_bitset0_b32 s3, 31 |
| ; VI-NEXT: s_and_b32 s12, s5, 0x80000000 |
| ; VI-NEXT: s_or_b32 s3, s3, s12 |
| ; VI-NEXT: .LBB12_16: ; %Flow124 |
| ; VI-NEXT: v_mov_b32_e32 v0, s10 |
| ; VI-NEXT: v_cmp_ngt_f32_e64 s[12:13], |s6|, |v0| |
| ; VI-NEXT: s_cmp_lg_u64 s[12:13], 0 |
| ; VI-NEXT: s_mov_b32 s13, 1 |
| ; VI-NEXT: ; implicit-def: $sgpr12 |
| ; VI-NEXT: s_cbranch_scc0 .LBB12_18 |
| ; VI-NEXT: ; %bb.17: ; %frem.else16 |
| ; VI-NEXT: v_mov_b32_e32 v0, s10 |
| ; VI-NEXT: s_and_b32 s12, s6, 0x80000000 |
| ; VI-NEXT: v_cmp_eq_f32_e64 s[14:15], |s6|, |v0| |
| ; VI-NEXT: s_cmp_lg_u64 s[14:15], 0 |
| ; VI-NEXT: s_mov_b32 s13, 0 |
| ; VI-NEXT: s_cselect_b32 s12, s12, s6 |
| ; VI-NEXT: .LBB12_18: ; %Flow119 |
| ; VI-NEXT: s_xor_b32 s13, s13, 1 |
| ; VI-NEXT: s_cmp_lg_u32 s13, 0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB12_24 |
| ; VI-NEXT: ; %bb.19: ; %frem.compute15 |
| ; VI-NEXT: v_frexp_mant_f32_e64 v0, |s6| |
| ; VI-NEXT: v_ldexp_f32 v0, v0, 12 |
| ; VI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s6| |
| ; VI-NEXT: v_readfirstlane_b32 s14, v0 |
| ; VI-NEXT: v_frexp_mant_f32_e64 v0, |s10| |
| ; VI-NEXT: v_readfirstlane_b32 s15, v1 |
| ; VI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s10| |
| ; VI-NEXT: v_ldexp_f32 v0, v0, 1 |
| ; VI-NEXT: v_readfirstlane_b32 s16, v1 |
| ; VI-NEXT: v_div_scale_f32 v1, s[18:19], v0, v0, 1.0 |
| ; VI-NEXT: s_add_i32 s13, s15, -1 |
| ; VI-NEXT: s_add_i32 s12, s16, -1 |
| ; VI-NEXT: s_sub_i32 s13, s13, s12 |
| ; VI-NEXT: v_div_scale_f32 v2, s[18:19], 1.0, v0, 1.0 |
| ; VI-NEXT: s_cmp_lg_u64 s[18:19], 0 |
| ; VI-NEXT: v_rcp_f32_e32 v3, v1 |
| ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 |
| ; VI-NEXT: v_fma_f32 v3, v4, v3, v3 |
| ; VI-NEXT: v_mul_f32_e32 v4, v2, v3 |
| ; VI-NEXT: v_fma_f32 v5, -v1, v4, v2 |
| ; VI-NEXT: v_fma_f32 v4, v5, v3, v4 |
| ; VI-NEXT: v_fma_f32 v1, -v1, v4, v2 |
| ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; VI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 |
| ; VI-NEXT: s_cmp_le_i32 s13, 12 |
| ; VI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB12_22 |
| ; VI-NEXT: ; %bb.20: ; %frem.loop_body23.preheader |
| ; VI-NEXT: s_add_i32 s15, s15, 12 |
| ; VI-NEXT: s_sub_i32 s13, s15, s16 |
| ; VI-NEXT: .LBB12_21: ; %frem.loop_body23 |
| ; VI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; VI-NEXT: v_mul_f32_e32 v2, s14, v1 |
| ; VI-NEXT: v_rndne_f32_e32 v2, v2 |
| ; VI-NEXT: v_fma_f32 v2, -v2, v0, s14 |
| ; VI-NEXT: v_readfirstlane_b32 s15, v2 |
| ; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 |
| ; VI-NEXT: v_add_f32_e32 v2, v2, v0 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s16, v2 |
| ; VI-NEXT: s_cselect_b32 s15, s16, s15 |
| ; VI-NEXT: v_ldexp_f32 v2, s15, 12 |
| ; VI-NEXT: v_readfirstlane_b32 s16, v2 |
| ; VI-NEXT: s_add_i32 s13, s13, -12 |
| ; VI-NEXT: s_cmp_gt_i32 s13, 12 |
| ; VI-NEXT: s_mov_b32 s15, s14 |
| ; VI-NEXT: s_mov_b32 s14, s16 |
| ; VI-NEXT: s_cbranch_scc1 .LBB12_21 |
| ; VI-NEXT: s_branch .LBB12_23 |
| ; VI-NEXT: .LBB12_22: |
| ; VI-NEXT: s_mov_b32 s15, s14 |
| ; VI-NEXT: .LBB12_23: ; %frem.loop_exit24 |
| ; VI-NEXT: s_add_i32 s13, s13, -11 |
| ; VI-NEXT: v_mov_b32_e32 v2, s13 |
| ; VI-NEXT: v_ldexp_f32 v2, s15, v2 |
| ; VI-NEXT: v_mul_f32_e32 v1, v2, v1 |
| ; VI-NEXT: v_rndne_f32_e32 v1, v1 |
| ; VI-NEXT: v_fma_f32 v1, -v1, v0, v2 |
| ; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1 |
| ; VI-NEXT: v_add_f32_e32 v0, v1, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s13, v1 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s14, v0 |
| ; VI-NEXT: s_cselect_b32 s13, s14, s13 |
| ; VI-NEXT: v_mov_b32_e32 v0, s12 |
| ; VI-NEXT: v_ldexp_f32 v0, s13, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s12, v0 |
| ; VI-NEXT: s_bitset0_b32 s12, 31 |
| ; VI-NEXT: s_and_b32 s13, s6, 0x80000000 |
| ; VI-NEXT: s_or_b32 s12, s12, s13 |
| ; VI-NEXT: .LBB12_24: ; %Flow120 |
| ; VI-NEXT: v_mov_b32_e32 v0, s11 |
| ; VI-NEXT: v_cmp_ngt_f32_e64 s[14:15], |s7|, |v0| |
| ; VI-NEXT: s_cmp_lg_u64 s[14:15], 0 |
| ; VI-NEXT: s_mov_b32 s14, 1 |
| ; VI-NEXT: ; implicit-def: $sgpr13 |
| ; VI-NEXT: s_cbranch_scc0 .LBB12_26 |
| ; VI-NEXT: ; %bb.25: ; %frem.else |
| ; VI-NEXT: v_mov_b32_e32 v0, s11 |
| ; VI-NEXT: s_and_b32 s13, s7, 0x80000000 |
| ; VI-NEXT: v_cmp_eq_f32_e64 s[16:17], |s7|, |v0| |
| ; VI-NEXT: s_cmp_lg_u64 s[16:17], 0 |
| ; VI-NEXT: s_mov_b32 s14, 0 |
| ; VI-NEXT: s_cselect_b32 s13, s13, s7 |
| ; VI-NEXT: .LBB12_26: ; %Flow115 |
| ; VI-NEXT: s_xor_b32 s14, s14, 1 |
| ; VI-NEXT: s_cmp_lg_u32 s14, 0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB12_32 |
| ; VI-NEXT: ; %bb.27: ; %frem.compute |
| ; VI-NEXT: v_frexp_mant_f32_e64 v0, |s7| |
| ; VI-NEXT: v_ldexp_f32 v0, v0, 12 |
| ; VI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s7| |
| ; VI-NEXT: v_readfirstlane_b32 s15, v0 |
| ; VI-NEXT: v_frexp_mant_f32_e64 v0, |s11| |
| ; VI-NEXT: v_readfirstlane_b32 s16, v1 |
| ; VI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s11| |
| ; VI-NEXT: v_ldexp_f32 v0, v0, 1 |
| ; VI-NEXT: v_readfirstlane_b32 s17, v1 |
| ; VI-NEXT: v_div_scale_f32 v1, s[18:19], v0, v0, 1.0 |
| ; VI-NEXT: s_add_i32 s14, s16, -1 |
| ; VI-NEXT: s_add_i32 s13, s17, -1 |
| ; VI-NEXT: s_sub_i32 s14, s14, s13 |
| ; VI-NEXT: v_div_scale_f32 v2, s[18:19], 1.0, v0, 1.0 |
| ; VI-NEXT: s_cmp_lg_u64 s[18:19], 0 |
| ; VI-NEXT: v_rcp_f32_e32 v3, v1 |
| ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 |
| ; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 |
| ; VI-NEXT: v_fma_f32 v3, v4, v3, v3 |
| ; VI-NEXT: v_mul_f32_e32 v4, v2, v3 |
| ; VI-NEXT: v_fma_f32 v5, -v1, v4, v2 |
| ; VI-NEXT: v_fma_f32 v4, v5, v3, v4 |
| ; VI-NEXT: v_fma_f32 v1, -v1, v4, v2 |
| ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 |
| ; VI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 |
| ; VI-NEXT: s_cmp_le_i32 s14, 12 |
| ; VI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB12_30 |
| ; VI-NEXT: ; %bb.28: ; %frem.loop_body.preheader |
| ; VI-NEXT: s_add_i32 s16, s16, 12 |
| ; VI-NEXT: s_sub_i32 s14, s16, s17 |
| ; VI-NEXT: .LBB12_29: ; %frem.loop_body |
| ; VI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; VI-NEXT: v_mul_f32_e32 v2, s15, v1 |
| ; VI-NEXT: v_rndne_f32_e32 v2, v2 |
| ; VI-NEXT: v_fma_f32 v2, -v2, v0, s15 |
| ; VI-NEXT: v_readfirstlane_b32 s16, v2 |
| ; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 |
| ; VI-NEXT: v_add_f32_e32 v2, v2, v0 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s17, v2 |
| ; VI-NEXT: s_cselect_b32 s16, s17, s16 |
| ; VI-NEXT: v_ldexp_f32 v2, s16, 12 |
| ; VI-NEXT: v_readfirstlane_b32 s17, v2 |
| ; VI-NEXT: s_add_i32 s14, s14, -12 |
| ; VI-NEXT: s_cmp_gt_i32 s14, 12 |
| ; VI-NEXT: s_mov_b32 s16, s15 |
| ; VI-NEXT: s_mov_b32 s15, s17 |
| ; VI-NEXT: s_cbranch_scc1 .LBB12_29 |
| ; VI-NEXT: s_branch .LBB12_31 |
| ; VI-NEXT: .LBB12_30: |
| ; VI-NEXT: s_mov_b32 s16, s15 |
| ; VI-NEXT: .LBB12_31: ; %frem.loop_exit |
| ; VI-NEXT: s_add_i32 s14, s14, -11 |
| ; VI-NEXT: v_mov_b32_e32 v2, s14 |
| ; VI-NEXT: v_ldexp_f32 v2, s16, v2 |
| ; VI-NEXT: v_mul_f32_e32 v1, v2, v1 |
| ; VI-NEXT: v_rndne_f32_e32 v1, v1 |
| ; VI-NEXT: v_fma_f32 v1, -v1, v0, v2 |
| ; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1 |
| ; VI-NEXT: v_add_f32_e32 v0, v1, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s14, v1 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s15, v0 |
| ; VI-NEXT: s_cselect_b32 s14, s15, s14 |
| ; VI-NEXT: v_mov_b32_e32 v0, s13 |
| ; VI-NEXT: v_ldexp_f32 v0, s14, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s13, v0 |
| ; VI-NEXT: s_bitset0_b32 s13, 31 |
| ; VI-NEXT: s_and_b32 s14, s7, 0x80000000 |
| ; VI-NEXT: s_or_b32 s13, s13, s14 |
| ; VI-NEXT: .LBB12_32: ; %Flow116 |
| ; VI-NEXT: v_cmp_nlg_f32_e64 s[14:15], s8, 0 |
| ; VI-NEXT: v_mov_b32_e32 v0, 0x7f800000 |
| ; VI-NEXT: s_cmp_lg_u64 s[14:15], 0 |
| ; VI-NEXT: v_cmp_nge_f32_e64 s[14:15], |s4|, v0 |
| ; VI-NEXT: s_cselect_b32 s2, 0x7fc00000, s2 |
| ; VI-NEXT: s_cmp_lg_u64 s[14:15], 0 |
| ; VI-NEXT: v_cmp_nlg_f32_e64 s[8:9], s9, 0 |
| ; VI-NEXT: s_cselect_b32 s4, s2, 0x7fc00000 |
| ; VI-NEXT: s_cmp_lg_u64 s[8:9], 0 |
| ; VI-NEXT: s_cselect_b32 s8, 0x7fc00000, s3 |
| ; VI-NEXT: v_cmp_nge_f32_e64 s[2:3], |s5|, v0 |
| ; VI-NEXT: s_cmp_lg_u64 s[2:3], 0 |
| ; VI-NEXT: v_cmp_nlg_f32_e64 s[2:3], s10, 0 |
| ; VI-NEXT: s_cselect_b32 s5, s8, 0x7fc00000 |
| ; VI-NEXT: s_cmp_lg_u64 s[2:3], 0 |
| ; VI-NEXT: v_cmp_nge_f32_e64 s[2:3], |s6|, v0 |
| ; VI-NEXT: s_cselect_b32 s8, 0x7fc00000, s12 |
| ; VI-NEXT: s_cmp_lg_u64 s[2:3], 0 |
| ; VI-NEXT: v_cmp_nlg_f32_e64 s[2:3], s11, 0 |
| ; VI-NEXT: s_cselect_b32 s6, s8, 0x7fc00000 |
| ; VI-NEXT: s_cmp_lg_u64 s[2:3], 0 |
| ; VI-NEXT: v_cmp_nge_f32_e64 s[2:3], |s7|, v0 |
| ; VI-NEXT: s_cselect_b32 s8, 0x7fc00000, s13 |
| ; VI-NEXT: s_cmp_lg_u64 s[2:3], 0 |
| ; VI-NEXT: s_cselect_b32 s7, s8, 0x7fc00000 |
| ; VI-NEXT: v_mov_b32_e32 v0, s4 |
| ; VI-NEXT: v_mov_b32_e32 v1, s5 |
| ; VI-NEXT: v_mov_b32_e32 v2, s6 |
| ; VI-NEXT: v_mov_b32_e32 v3, s7 |
| ; VI-NEXT: v_mov_b32_e32 v5, s1 |
| ; VI-NEXT: v_mov_b32_e32 v4, s0 |
| ; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] |
| ; VI-NEXT: s_endpgm |
| %gep2 = getelementptr <4 x float>, ptr addrspace(1) %in2, i32 4 |
| %r0 = load <4 x float>, ptr addrspace(1) %in1, align 16 |
| %r1 = load <4 x float>, ptr addrspace(1) %gep2, align 16 |
| %r2 = frem <4 x float> %r0, %r1 |
| store <4 x float> %r2, ptr addrspace(1) %out, align 16 |
| ret void |
| } |
| |
| define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 { |
| ; CI-LABEL: frem_v2f64: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 |
| ; CI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd |
| ; CI-NEXT: s_mov_b32 s13, 1 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0 |
| ; CI-NEXT: s_load_dwordx4 s[8:11], s[8:9], 0x10 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_mov_b32_e32 v0, s8 |
| ; CI-NEXT: v_mov_b32_e32 v1, s9 |
| ; CI-NEXT: v_cmp_ngt_f64_e64 s[2:3], |s[4:5]|, |v[0:1]| |
| ; CI-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3] |
| ; CI-NEXT: ; implicit-def: $sgpr2_sgpr3 |
| ; CI-NEXT: s_cbranch_scc0 .LBB13_2 |
| ; CI-NEXT: ; %bb.1: ; %frem.else16 |
| ; CI-NEXT: v_mov_b32_e32 v0, s8 |
| ; CI-NEXT: v_mov_b32_e32 v1, s9 |
| ; CI-NEXT: v_cmp_eq_f64_e64 s[14:15], |s[4:5]|, |v[0:1]| |
| ; CI-NEXT: s_mov_b64 s[12:13], 0 |
| ; CI-NEXT: s_mov_b32 s2, 0 |
| ; CI-NEXT: s_brev_b32 s3, 1 |
| ; CI-NEXT: s_mov_b32 s13, 0 |
| ; CI-NEXT: s_and_b64 s[2:3], s[4:5], s[2:3] |
| ; CI-NEXT: s_or_b64 s[2:3], s[12:13], s[2:3] |
| ; CI-NEXT: s_or_b64 s[14:15], s[14:15], s[14:15] |
| ; CI-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5] |
| ; CI-NEXT: .LBB13_2: ; %Flow53 |
| ; CI-NEXT: s_xor_b32 s12, s13, 1 |
| ; CI-NEXT: s_cmp_lg_u32 s12, 0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB13_8 |
| ; CI-NEXT: ; %bb.3: ; %frem.compute15 |
| ; CI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[4:5]| |
| ; CI-NEXT: v_frexp_exp_i32_f64_e64 v2, |s[4:5]| |
| ; CI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 26 |
| ; CI-NEXT: v_readfirstlane_b32 s12, v2 |
| ; CI-NEXT: v_frexp_exp_i32_f64_e64 v2, |s[8:9]| |
| ; CI-NEXT: s_add_i32 s15, s12, -1 |
| ; CI-NEXT: v_readfirstlane_b32 s2, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s3, v1 |
| ; CI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[8:9]| |
| ; CI-NEXT: v_readfirstlane_b32 s13, v2 |
| ; CI-NEXT: s_add_i32 s14, s13, -1 |
| ; CI-NEXT: s_sub_i32 s15, s15, s14 |
| ; CI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 1 |
| ; CI-NEXT: v_div_scale_f64 v[2:3], s[16:17], v[0:1], v[0:1], 1.0 |
| ; CI-NEXT: v_div_scale_f64 v[8:9], s[16:17], 1.0, v[0:1], 1.0 |
| ; CI-NEXT: s_or_b64 s[16:17], s[16:17], s[16:17] |
| ; CI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; CI-NEXT: s_cmp_le_i32 s15, 26 |
| ; CI-NEXT: v_rcp_f64_e32 v[4:5], v[2:3] |
| ; CI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 |
| ; CI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] |
| ; CI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 |
| ; CI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] |
| ; CI-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5] |
| ; CI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9] |
| ; CI-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7] |
| ; CI-NEXT: v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB13_6 |
| ; CI-NEXT: ; %bb.4: ; %frem.loop_body23.preheader |
| ; CI-NEXT: s_add_i32 s12, s12, 26 |
| ; CI-NEXT: s_sub_i32 s15, s12, s13 |
| ; CI-NEXT: .LBB13_5: ; %frem.loop_body23 |
| ; CI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; CI-NEXT: v_mul_f64 v[4:5], s[2:3], v[2:3] |
| ; CI-NEXT: v_rndne_f64_e32 v[4:5], v[4:5] |
| ; CI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[0:1], s[2:3] |
| ; CI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5] |
| ; CI-NEXT: v_readfirstlane_b32 s12, v4 |
| ; CI-NEXT: v_readfirstlane_b32 s13, v5 |
| ; CI-NEXT: v_add_f64 v[4:5], v[4:5], v[0:1] |
| ; CI-NEXT: s_or_b64 s[16:17], vcc, vcc |
| ; CI-NEXT: v_readfirstlane_b32 s16, v4 |
| ; CI-NEXT: v_readfirstlane_b32 s17, v5 |
| ; CI-NEXT: s_cselect_b64 s[12:13], s[16:17], s[12:13] |
| ; CI-NEXT: v_ldexp_f64 v[4:5], s[12:13], 26 |
| ; CI-NEXT: s_sub_i32 s15, s15, 26 |
| ; CI-NEXT: s_cmp_gt_i32 s15, 26 |
| ; CI-NEXT: s_mov_b64 s[12:13], s[2:3] |
| ; CI-NEXT: v_readfirstlane_b32 s16, v4 |
| ; CI-NEXT: v_readfirstlane_b32 s17, v5 |
| ; CI-NEXT: s_mov_b64 s[2:3], s[16:17] |
| ; CI-NEXT: s_cbranch_scc1 .LBB13_5 |
| ; CI-NEXT: s_branch .LBB13_7 |
| ; CI-NEXT: .LBB13_6: |
| ; CI-NEXT: s_mov_b64 s[12:13], s[2:3] |
| ; CI-NEXT: .LBB13_7: ; %frem.loop_exit24 |
| ; CI-NEXT: s_sub_i32 s2, s15, 25 |
| ; CI-NEXT: v_mov_b32_e32 v4, s2 |
| ; CI-NEXT: v_ldexp_f64 v[4:5], s[12:13], v4 |
| ; CI-NEXT: v_mul_f64 v[2:3], v[4:5], v[2:3] |
| ; CI-NEXT: v_rndne_f64_e32 v[2:3], v[2:3] |
| ; CI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[0:1], v[4:5] |
| ; CI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[2:3] |
| ; CI-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1] |
| ; CI-NEXT: v_readfirstlane_b32 s2, v2 |
| ; CI-NEXT: v_readfirstlane_b32 s3, v3 |
| ; CI-NEXT: s_or_b64 s[12:13], vcc, vcc |
| ; CI-NEXT: v_readfirstlane_b32 s12, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s13, v1 |
| ; CI-NEXT: s_cselect_b64 s[2:3], s[12:13], s[2:3] |
| ; CI-NEXT: v_mov_b32_e32 v0, s14 |
| ; CI-NEXT: v_ldexp_f64 v[0:1], s[2:3], v0 |
| ; CI-NEXT: s_mov_b32 s12, 0 |
| ; CI-NEXT: s_brev_b32 s13, 1 |
| ; CI-NEXT: s_and_b64 s[12:13], s[4:5], s[12:13] |
| ; CI-NEXT: v_readfirstlane_b32 s3, v1 |
| ; CI-NEXT: v_readfirstlane_b32 s2, v0 |
| ; CI-NEXT: s_bitset0_b32 s3, 31 |
| ; CI-NEXT: s_or_b64 s[2:3], s[2:3], s[12:13] |
| ; CI-NEXT: .LBB13_8: ; %Flow54 |
| ; CI-NEXT: v_mov_b32_e32 v0, s10 |
| ; CI-NEXT: v_mov_b32_e32 v1, s11 |
| ; CI-NEXT: v_cmp_ngt_f64_e64 s[12:13], |s[6:7]|, |v[0:1]| |
| ; CI-NEXT: s_mov_b32 s15, 1 |
| ; CI-NEXT: s_or_b64 s[12:13], s[12:13], s[12:13] |
| ; CI-NEXT: ; implicit-def: $sgpr12_sgpr13 |
| ; CI-NEXT: s_cbranch_scc0 .LBB13_10 |
| ; CI-NEXT: ; %bb.9: ; %frem.else |
| ; CI-NEXT: v_mov_b32_e32 v0, s10 |
| ; CI-NEXT: v_mov_b32_e32 v1, s11 |
| ; CI-NEXT: v_cmp_eq_f64_e64 s[16:17], |s[6:7]|, |v[0:1]| |
| ; CI-NEXT: s_mov_b64 s[14:15], 0 |
| ; CI-NEXT: s_mov_b32 s12, 0 |
| ; CI-NEXT: s_brev_b32 s13, 1 |
| ; CI-NEXT: s_mov_b32 s15, 0 |
| ; CI-NEXT: s_and_b64 s[12:13], s[6:7], s[12:13] |
| ; CI-NEXT: s_or_b64 s[12:13], s[14:15], s[12:13] |
| ; CI-NEXT: s_or_b64 s[16:17], s[16:17], s[16:17] |
| ; CI-NEXT: s_cselect_b64 s[12:13], s[12:13], s[6:7] |
| ; CI-NEXT: .LBB13_10: ; %Flow49 |
| ; CI-NEXT: s_xor_b32 s14, s15, 1 |
| ; CI-NEXT: s_cmp_lg_u32 s14, 0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB13_16 |
| ; CI-NEXT: ; %bb.11: ; %frem.compute |
| ; CI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[6:7]| |
| ; CI-NEXT: v_frexp_exp_i32_f64_e64 v2, |s[6:7]| |
| ; CI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 26 |
| ; CI-NEXT: v_readfirstlane_b32 s14, v2 |
| ; CI-NEXT: v_frexp_exp_i32_f64_e64 v2, |s[10:11]| |
| ; CI-NEXT: s_add_i32 s17, s14, -1 |
| ; CI-NEXT: v_readfirstlane_b32 s12, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s13, v1 |
| ; CI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[10:11]| |
| ; CI-NEXT: v_readfirstlane_b32 s15, v2 |
| ; CI-NEXT: s_add_i32 s16, s15, -1 |
| ; CI-NEXT: s_sub_i32 s17, s17, s16 |
| ; CI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 1 |
| ; CI-NEXT: v_div_scale_f64 v[2:3], s[18:19], v[0:1], v[0:1], 1.0 |
| ; CI-NEXT: v_div_scale_f64 v[8:9], s[18:19], 1.0, v[0:1], 1.0 |
| ; CI-NEXT: s_or_b64 s[18:19], s[18:19], s[18:19] |
| ; CI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; CI-NEXT: s_cmp_le_i32 s17, 26 |
| ; CI-NEXT: v_rcp_f64_e32 v[4:5], v[2:3] |
| ; CI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 |
| ; CI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] |
| ; CI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 |
| ; CI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] |
| ; CI-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5] |
| ; CI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9] |
| ; CI-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7] |
| ; CI-NEXT: v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0 |
| ; CI-NEXT: s_cbranch_scc1 .LBB13_14 |
| ; CI-NEXT: ; %bb.12: ; %frem.loop_body.preheader |
| ; CI-NEXT: s_add_i32 s14, s14, 26 |
| ; CI-NEXT: s_sub_i32 s17, s14, s15 |
| ; CI-NEXT: .LBB13_13: ; %frem.loop_body |
| ; CI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; CI-NEXT: v_mul_f64 v[4:5], s[12:13], v[2:3] |
| ; CI-NEXT: v_rndne_f64_e32 v[4:5], v[4:5] |
| ; CI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[0:1], s[12:13] |
| ; CI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5] |
| ; CI-NEXT: v_readfirstlane_b32 s14, v4 |
| ; CI-NEXT: v_readfirstlane_b32 s15, v5 |
| ; CI-NEXT: v_add_f64 v[4:5], v[4:5], v[0:1] |
| ; CI-NEXT: s_or_b64 s[18:19], vcc, vcc |
| ; CI-NEXT: v_readfirstlane_b32 s18, v4 |
| ; CI-NEXT: v_readfirstlane_b32 s19, v5 |
| ; CI-NEXT: s_cselect_b64 s[14:15], s[18:19], s[14:15] |
| ; CI-NEXT: v_ldexp_f64 v[4:5], s[14:15], 26 |
| ; CI-NEXT: s_sub_i32 s17, s17, 26 |
| ; CI-NEXT: s_cmp_gt_i32 s17, 26 |
| ; CI-NEXT: s_mov_b64 s[14:15], s[12:13] |
| ; CI-NEXT: v_readfirstlane_b32 s18, v4 |
| ; CI-NEXT: v_readfirstlane_b32 s19, v5 |
| ; CI-NEXT: s_mov_b64 s[12:13], s[18:19] |
| ; CI-NEXT: s_cbranch_scc1 .LBB13_13 |
| ; CI-NEXT: s_branch .LBB13_15 |
| ; CI-NEXT: .LBB13_14: |
| ; CI-NEXT: s_mov_b64 s[14:15], s[12:13] |
| ; CI-NEXT: .LBB13_15: ; %frem.loop_exit |
| ; CI-NEXT: s_sub_i32 s12, s17, 25 |
| ; CI-NEXT: v_mov_b32_e32 v4, s12 |
| ; CI-NEXT: v_ldexp_f64 v[4:5], s[14:15], v4 |
| ; CI-NEXT: v_mul_f64 v[2:3], v[4:5], v[2:3] |
| ; CI-NEXT: v_rndne_f64_e32 v[2:3], v[2:3] |
| ; CI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[0:1], v[4:5] |
| ; CI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[2:3] |
| ; CI-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1] |
| ; CI-NEXT: v_readfirstlane_b32 s12, v2 |
| ; CI-NEXT: v_readfirstlane_b32 s13, v3 |
| ; CI-NEXT: s_or_b64 s[14:15], vcc, vcc |
| ; CI-NEXT: v_readfirstlane_b32 s14, v0 |
| ; CI-NEXT: v_readfirstlane_b32 s15, v1 |
| ; CI-NEXT: s_cselect_b64 s[12:13], s[14:15], s[12:13] |
| ; CI-NEXT: v_mov_b32_e32 v0, s16 |
| ; CI-NEXT: v_ldexp_f64 v[0:1], s[12:13], v0 |
| ; CI-NEXT: s_mov_b32 s14, 0 |
| ; CI-NEXT: s_brev_b32 s15, 1 |
| ; CI-NEXT: s_and_b64 s[14:15], s[6:7], s[14:15] |
| ; CI-NEXT: v_readfirstlane_b32 s13, v1 |
| ; CI-NEXT: v_readfirstlane_b32 s12, v0 |
| ; CI-NEXT: s_bitset0_b32 s13, 31 |
| ; CI-NEXT: s_or_b64 s[12:13], s[12:13], s[14:15] |
| ; CI-NEXT: .LBB13_16: ; %Flow50 |
| ; CI-NEXT: v_cmp_nlg_f64_e64 s[8:9], s[8:9], 0 |
| ; CI-NEXT: v_mov_b32_e32 v0, 0 |
| ; CI-NEXT: v_mov_b32_e32 v1, 0x7ff00000 |
| ; CI-NEXT: v_cmp_nge_f64_e64 s[4:5], |s[4:5]|, v[0:1] |
| ; CI-NEXT: v_cmp_nge_f64_e64 s[6:7], |s[6:7]|, v[0:1] |
| ; CI-NEXT: s_or_b64 s[8:9], s[8:9], s[8:9] |
| ; CI-NEXT: s_mov_b32 s8, 0 |
| ; CI-NEXT: s_mov_b32 s9, 0x7ff80000 |
| ; CI-NEXT: s_cselect_b64 s[2:3], s[8:9], s[2:3] |
| ; CI-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5] |
| ; CI-NEXT: s_cselect_b64 s[4:5], s[2:3], s[8:9] |
| ; CI-NEXT: v_cmp_nlg_f64_e64 s[2:3], s[10:11], 0 |
| ; CI-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3] |
| ; CI-NEXT: s_cselect_b64 s[2:3], s[8:9], s[12:13] |
| ; CI-NEXT: s_or_b64 s[6:7], s[6:7], s[6:7] |
| ; CI-NEXT: s_cselect_b64 s[6:7], s[2:3], s[8:9] |
| ; CI-NEXT: v_mov_b32_e32 v0, s4 |
| ; CI-NEXT: v_mov_b32_e32 v1, s5 |
| ; CI-NEXT: v_mov_b32_e32 v2, s6 |
| ; CI-NEXT: v_mov_b32_e32 v3, s7 |
| ; CI-NEXT: s_mov_b32 s2, -1 |
| ; CI-NEXT: s_mov_b32 s3, 0xf000 |
| ; CI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: frem_v2f64: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; VI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x34 |
| ; VI-NEXT: s_mov_b32 s13, 1 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0 |
| ; VI-NEXT: s_load_dwordx4 s[8:11], s[8:9], 0x40 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v0, s8 |
| ; VI-NEXT: v_mov_b32_e32 v1, s9 |
| ; VI-NEXT: v_cmp_ngt_f64_e64 s[2:3], |s[4:5]|, |v[0:1]| |
| ; VI-NEXT: s_cmp_lg_u64 s[2:3], 0 |
| ; VI-NEXT: ; implicit-def: $sgpr2_sgpr3 |
| ; VI-NEXT: s_cbranch_scc0 .LBB13_2 |
| ; VI-NEXT: ; %bb.1: ; %frem.else16 |
| ; VI-NEXT: v_mov_b32_e32 v0, s8 |
| ; VI-NEXT: v_mov_b32_e32 v1, s9 |
| ; VI-NEXT: v_cmp_eq_f64_e64 s[14:15], |s[4:5]|, |v[0:1]| |
| ; VI-NEXT: s_mov_b64 s[12:13], 0 |
| ; VI-NEXT: s_mov_b32 s2, 0 |
| ; VI-NEXT: s_brev_b32 s3, 1 |
| ; VI-NEXT: s_mov_b32 s13, 0 |
| ; VI-NEXT: s_and_b64 s[2:3], s[4:5], s[2:3] |
| ; VI-NEXT: s_or_b64 s[2:3], s[12:13], s[2:3] |
| ; VI-NEXT: s_cmp_lg_u64 s[14:15], 0 |
| ; VI-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5] |
| ; VI-NEXT: .LBB13_2: ; %Flow53 |
| ; VI-NEXT: s_xor_b32 s12, s13, 1 |
| ; VI-NEXT: s_cmp_lg_u32 s12, 0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB13_8 |
| ; VI-NEXT: ; %bb.3: ; %frem.compute15 |
| ; VI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[4:5]| |
| ; VI-NEXT: v_frexp_exp_i32_f64_e64 v2, |s[4:5]| |
| ; VI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 26 |
| ; VI-NEXT: v_readfirstlane_b32 s12, v2 |
| ; VI-NEXT: v_frexp_exp_i32_f64_e64 v2, |s[8:9]| |
| ; VI-NEXT: s_add_i32 s15, s12, -1 |
| ; VI-NEXT: v_readfirstlane_b32 s2, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s3, v1 |
| ; VI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[8:9]| |
| ; VI-NEXT: v_readfirstlane_b32 s13, v2 |
| ; VI-NEXT: s_add_i32 s14, s13, -1 |
| ; VI-NEXT: s_sub_i32 s15, s15, s14 |
| ; VI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 1 |
| ; VI-NEXT: v_div_scale_f64 v[2:3], s[16:17], v[0:1], v[0:1], 1.0 |
| ; VI-NEXT: v_div_scale_f64 v[8:9], s[16:17], 1.0, v[0:1], 1.0 |
| ; VI-NEXT: s_cmp_lg_u64 s[16:17], 0 |
| ; VI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; VI-NEXT: s_cmp_le_i32 s15, 26 |
| ; VI-NEXT: v_rcp_f64_e32 v[4:5], v[2:3] |
| ; VI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 |
| ; VI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] |
| ; VI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 |
| ; VI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] |
| ; VI-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5] |
| ; VI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9] |
| ; VI-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7] |
| ; VI-NEXT: v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB13_6 |
| ; VI-NEXT: ; %bb.4: ; %frem.loop_body23.preheader |
| ; VI-NEXT: s_add_i32 s12, s12, 26 |
| ; VI-NEXT: s_sub_i32 s15, s12, s13 |
| ; VI-NEXT: .LBB13_5: ; %frem.loop_body23 |
| ; VI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; VI-NEXT: v_mul_f64 v[4:5], s[2:3], v[2:3] |
| ; VI-NEXT: v_rndne_f64_e32 v[4:5], v[4:5] |
| ; VI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[0:1], s[2:3] |
| ; VI-NEXT: v_readfirstlane_b32 s12, v4 |
| ; VI-NEXT: v_readfirstlane_b32 s13, v5 |
| ; VI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5] |
| ; VI-NEXT: v_add_f64 v[4:5], v[4:5], v[0:1] |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s16, v4 |
| ; VI-NEXT: v_readfirstlane_b32 s17, v5 |
| ; VI-NEXT: s_cselect_b64 s[12:13], s[16:17], s[12:13] |
| ; VI-NEXT: v_ldexp_f64 v[4:5], s[12:13], 26 |
| ; VI-NEXT: s_sub_i32 s15, s15, 26 |
| ; VI-NEXT: s_cmp_gt_i32 s15, 26 |
| ; VI-NEXT: s_mov_b64 s[12:13], s[2:3] |
| ; VI-NEXT: v_readfirstlane_b32 s16, v4 |
| ; VI-NEXT: v_readfirstlane_b32 s17, v5 |
| ; VI-NEXT: s_mov_b64 s[2:3], s[16:17] |
| ; VI-NEXT: s_cbranch_scc1 .LBB13_5 |
| ; VI-NEXT: s_branch .LBB13_7 |
| ; VI-NEXT: .LBB13_6: |
| ; VI-NEXT: s_mov_b64 s[12:13], s[2:3] |
| ; VI-NEXT: .LBB13_7: ; %frem.loop_exit24 |
| ; VI-NEXT: s_sub_i32 s2, s15, 25 |
| ; VI-NEXT: v_mov_b32_e32 v4, s2 |
| ; VI-NEXT: v_ldexp_f64 v[4:5], s[12:13], v4 |
| ; VI-NEXT: v_mul_f64 v[2:3], v[4:5], v[2:3] |
| ; VI-NEXT: v_rndne_f64_e32 v[2:3], v[2:3] |
| ; VI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[0:1], v[4:5] |
| ; VI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[2:3] |
| ; VI-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1] |
| ; VI-NEXT: v_readfirstlane_b32 s2, v2 |
| ; VI-NEXT: v_readfirstlane_b32 s3, v3 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s12, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s13, v1 |
| ; VI-NEXT: s_cselect_b64 s[2:3], s[12:13], s[2:3] |
| ; VI-NEXT: v_mov_b32_e32 v0, s14 |
| ; VI-NEXT: v_ldexp_f64 v[0:1], s[2:3], v0 |
| ; VI-NEXT: s_mov_b32 s12, 0 |
| ; VI-NEXT: s_brev_b32 s13, 1 |
| ; VI-NEXT: s_and_b64 s[12:13], s[4:5], s[12:13] |
| ; VI-NEXT: v_readfirstlane_b32 s3, v1 |
| ; VI-NEXT: v_readfirstlane_b32 s2, v0 |
| ; VI-NEXT: s_bitset0_b32 s3, 31 |
| ; VI-NEXT: s_or_b64 s[2:3], s[2:3], s[12:13] |
| ; VI-NEXT: .LBB13_8: ; %Flow54 |
| ; VI-NEXT: v_mov_b32_e32 v0, s10 |
| ; VI-NEXT: v_mov_b32_e32 v1, s11 |
| ; VI-NEXT: v_cmp_ngt_f64_e64 s[12:13], |s[6:7]|, |v[0:1]| |
| ; VI-NEXT: s_mov_b32 s15, 1 |
| ; VI-NEXT: s_cmp_lg_u64 s[12:13], 0 |
| ; VI-NEXT: ; implicit-def: $sgpr12_sgpr13 |
| ; VI-NEXT: s_cbranch_scc0 .LBB13_10 |
| ; VI-NEXT: ; %bb.9: ; %frem.else |
| ; VI-NEXT: v_mov_b32_e32 v0, s10 |
| ; VI-NEXT: v_mov_b32_e32 v1, s11 |
| ; VI-NEXT: v_cmp_eq_f64_e64 s[16:17], |s[6:7]|, |v[0:1]| |
| ; VI-NEXT: s_mov_b64 s[14:15], 0 |
| ; VI-NEXT: s_mov_b32 s12, 0 |
| ; VI-NEXT: s_brev_b32 s13, 1 |
| ; VI-NEXT: s_mov_b32 s15, 0 |
| ; VI-NEXT: s_and_b64 s[12:13], s[6:7], s[12:13] |
| ; VI-NEXT: s_or_b64 s[12:13], s[14:15], s[12:13] |
| ; VI-NEXT: s_cmp_lg_u64 s[16:17], 0 |
| ; VI-NEXT: s_cselect_b64 s[12:13], s[12:13], s[6:7] |
| ; VI-NEXT: .LBB13_10: ; %Flow49 |
| ; VI-NEXT: s_xor_b32 s14, s15, 1 |
| ; VI-NEXT: s_cmp_lg_u32 s14, 0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB13_16 |
| ; VI-NEXT: ; %bb.11: ; %frem.compute |
| ; VI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[6:7]| |
| ; VI-NEXT: v_frexp_exp_i32_f64_e64 v2, |s[6:7]| |
| ; VI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 26 |
| ; VI-NEXT: v_readfirstlane_b32 s14, v2 |
| ; VI-NEXT: v_frexp_exp_i32_f64_e64 v2, |s[10:11]| |
| ; VI-NEXT: s_add_i32 s17, s14, -1 |
| ; VI-NEXT: v_readfirstlane_b32 s12, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s13, v1 |
| ; VI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[10:11]| |
| ; VI-NEXT: v_readfirstlane_b32 s15, v2 |
| ; VI-NEXT: s_add_i32 s16, s15, -1 |
| ; VI-NEXT: s_sub_i32 s17, s17, s16 |
| ; VI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 1 |
| ; VI-NEXT: v_div_scale_f64 v[2:3], s[18:19], v[0:1], v[0:1], 1.0 |
| ; VI-NEXT: v_div_scale_f64 v[8:9], s[18:19], 1.0, v[0:1], 1.0 |
| ; VI-NEXT: s_cmp_lg_u64 s[18:19], 0 |
| ; VI-NEXT: s_cselect_b64 vcc, exec, 0 |
| ; VI-NEXT: s_cmp_le_i32 s17, 26 |
| ; VI-NEXT: v_rcp_f64_e32 v[4:5], v[2:3] |
| ; VI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 |
| ; VI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] |
| ; VI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 |
| ; VI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] |
| ; VI-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5] |
| ; VI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9] |
| ; VI-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7] |
| ; VI-NEXT: v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0 |
| ; VI-NEXT: s_cbranch_scc1 .LBB13_14 |
| ; VI-NEXT: ; %bb.12: ; %frem.loop_body.preheader |
| ; VI-NEXT: s_add_i32 s14, s14, 26 |
| ; VI-NEXT: s_sub_i32 s17, s14, s15 |
| ; VI-NEXT: .LBB13_13: ; %frem.loop_body |
| ; VI-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; VI-NEXT: v_mul_f64 v[4:5], s[12:13], v[2:3] |
| ; VI-NEXT: v_rndne_f64_e32 v[4:5], v[4:5] |
| ; VI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[0:1], s[12:13] |
| ; VI-NEXT: v_readfirstlane_b32 s14, v4 |
| ; VI-NEXT: v_readfirstlane_b32 s15, v5 |
| ; VI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5] |
| ; VI-NEXT: v_add_f64 v[4:5], v[4:5], v[0:1] |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s18, v4 |
| ; VI-NEXT: v_readfirstlane_b32 s19, v5 |
| ; VI-NEXT: s_cselect_b64 s[14:15], s[18:19], s[14:15] |
| ; VI-NEXT: v_ldexp_f64 v[4:5], s[14:15], 26 |
| ; VI-NEXT: s_sub_i32 s17, s17, 26 |
| ; VI-NEXT: s_cmp_gt_i32 s17, 26 |
| ; VI-NEXT: s_mov_b64 s[14:15], s[12:13] |
| ; VI-NEXT: v_readfirstlane_b32 s18, v4 |
| ; VI-NEXT: v_readfirstlane_b32 s19, v5 |
| ; VI-NEXT: s_mov_b64 s[12:13], s[18:19] |
| ; VI-NEXT: s_cbranch_scc1 .LBB13_13 |
| ; VI-NEXT: s_branch .LBB13_15 |
| ; VI-NEXT: .LBB13_14: |
| ; VI-NEXT: s_mov_b64 s[14:15], s[12:13] |
| ; VI-NEXT: .LBB13_15: ; %frem.loop_exit |
| ; VI-NEXT: s_sub_i32 s12, s17, 25 |
| ; VI-NEXT: v_mov_b32_e32 v4, s12 |
| ; VI-NEXT: v_ldexp_f64 v[4:5], s[14:15], v4 |
| ; VI-NEXT: v_mul_f64 v[2:3], v[4:5], v[2:3] |
| ; VI-NEXT: v_rndne_f64_e32 v[2:3], v[2:3] |
| ; VI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[0:1], v[4:5] |
| ; VI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[2:3] |
| ; VI-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1] |
| ; VI-NEXT: v_readfirstlane_b32 s12, v2 |
| ; VI-NEXT: v_readfirstlane_b32 s13, v3 |
| ; VI-NEXT: s_cmp_lg_u64 vcc, 0 |
| ; VI-NEXT: v_readfirstlane_b32 s14, v0 |
| ; VI-NEXT: v_readfirstlane_b32 s15, v1 |
| ; VI-NEXT: s_cselect_b64 s[12:13], s[14:15], s[12:13] |
| ; VI-NEXT: v_mov_b32_e32 v0, s16 |
| ; VI-NEXT: v_ldexp_f64 v[0:1], s[12:13], v0 |
| ; VI-NEXT: s_mov_b32 s14, 0 |
| ; VI-NEXT: s_brev_b32 s15, 1 |
| ; VI-NEXT: s_and_b64 s[14:15], s[6:7], s[14:15] |
| ; VI-NEXT: v_readfirstlane_b32 s13, v1 |
| ; VI-NEXT: v_readfirstlane_b32 s12, v0 |
| ; VI-NEXT: s_bitset0_b32 s13, 31 |
| ; VI-NEXT: s_or_b64 s[12:13], s[12:13], s[14:15] |
| ; VI-NEXT: .LBB13_16: ; %Flow50 |
| ; VI-NEXT: v_cmp_nlg_f64_e64 s[8:9], s[8:9], 0 |
| ; VI-NEXT: v_mov_b32_e32 v0, 0 |
| ; VI-NEXT: v_mov_b32_e32 v1, 0x7ff00000 |
| ; VI-NEXT: v_cmp_nge_f64_e64 s[4:5], |s[4:5]|, v[0:1] |
| ; VI-NEXT: v_cmp_nge_f64_e64 s[6:7], |s[6:7]|, v[0:1] |
| ; VI-NEXT: v_mov_b32_e32 v5, s1 |
| ; VI-NEXT: v_mov_b32_e32 v4, s0 |
| ; VI-NEXT: s_cmp_lg_u64 s[8:9], 0 |
| ; VI-NEXT: s_mov_b32 s8, 0 |
| ; VI-NEXT: s_mov_b32 s9, 0x7ff80000 |
| ; VI-NEXT: s_cselect_b64 s[2:3], s[8:9], s[2:3] |
| ; VI-NEXT: s_cmp_lg_u64 s[4:5], 0 |
| ; VI-NEXT: s_cselect_b64 s[4:5], s[2:3], s[8:9] |
| ; VI-NEXT: v_cmp_nlg_f64_e64 s[2:3], s[10:11], 0 |
| ; VI-NEXT: s_cmp_lg_u64 s[2:3], 0 |
| ; VI-NEXT: s_cselect_b64 s[2:3], s[8:9], s[12:13] |
| ; VI-NEXT: s_cmp_lg_u64 s[6:7], 0 |
| ; VI-NEXT: s_cselect_b64 s[6:7], s[2:3], s[8:9] |
| ; VI-NEXT: v_mov_b32_e32 v0, s4 |
| ; VI-NEXT: v_mov_b32_e32 v1, s5 |
| ; VI-NEXT: v_mov_b32_e32 v2, s6 |
| ; VI-NEXT: v_mov_b32_e32 v3, s7 |
| ; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] |
| ; VI-NEXT: s_endpgm |
| %gep2 = getelementptr <2 x double>, ptr addrspace(1) %in2, i32 4 |
| %r0 = load <2 x double>, ptr addrspace(1) %in1, align 16 |
| %r1 = load <2 x double>, ptr addrspace(1) %gep2, align 16 |
| %r2 = frem <2 x double> %r0, %r1 |
| store <2 x double> %r2, ptr addrspace(1) %out, align 16 |
| ret void |
| } |
| |
| attributes #0 = { nounwind denormal_fpenv(float: preservesign) } |
| attributes #1 = { nounwind denormal_fpenv(float: preservesign) } |
