llvm/test/CodeGen/AArch64/udiv-by-const-promoted-ops.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s

; This test verifies that udiv by constant works correctly even when type
; legalization promotes constant operands (e.g., i16 -> i32 in BUILD_VECTOR).
; This is a regression test for a bug where v16i16 would be split into two
; v8i16 operations during legalization, the i16 constants would be promoted
; to i32, and then the second DAGCombine round would fail to recognize the
; promoted constants when trying to convert udiv into mul+shift.

define <8 x i16> @udiv_v8i16_by_255(<8 x i16> %x) {
; CHECK-LABEL: udiv_v8i16_by_255:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov w8, #32897 // =0x8081
; CHECK-NEXT:    dup v1.8h, w8
; CHECK-NEXT:    umull2 v2.4s, v0.8h, v1.8h
; CHECK-NEXT:    umull v0.4s, v0.4h, v1.4h
; CHECK-NEXT:    uzp2 v0.8h, v0.8h, v2.8h
; CHECK-NEXT:    ushr v0.8h, v0.8h, #7
; CHECK-NEXT:    ret
  %div = udiv <8 x i16> %x, splat (i16 255)
  ret <8 x i16> %div
}

define <16 x i16> @udiv_v16i16_by_255(<16 x i16> %x) {
; CHECK-LABEL: udiv_v16i16_by_255:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov w8, #32897 // =0x8081
; CHECK-NEXT:    dup v2.8h, w8
; CHECK-NEXT:    umull2 v3.4s, v0.8h, v2.8h
; CHECK-NEXT:    umull v0.4s, v0.4h, v2.4h
; CHECK-NEXT:    umull2 v4.4s, v1.8h, v2.8h
; CHECK-NEXT:    umull v1.4s, v1.4h, v2.4h
; CHECK-NEXT:    uzp2 v0.8h, v0.8h, v3.8h
; CHECK-NEXT:    uzp2 v1.8h, v1.8h, v4.8h
; CHECK-NEXT:    ushr v0.8h, v0.8h, #7
; CHECK-NEXT:    ushr v1.8h, v1.8h, #7
; CHECK-NEXT:    ret
  %div = udiv <16 x i16> %x, splat (i16 255)
  ret <16 x i16> %div
}

define <8 x i16> @urem_v8i16_by_255(<8 x i16> %x) {
; CHECK-LABEL: urem_v8i16_by_255:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov w8, #32897 // =0x8081
; CHECK-NEXT:    dup v1.8h, w8
; CHECK-NEXT:    umull2 v2.4s, v0.8h, v1.8h
; CHECK-NEXT:    umull v1.4s, v0.4h, v1.4h
; CHECK-NEXT:    uzp2 v1.8h, v1.8h, v2.8h
; CHECK-NEXT:    movi v2.2d, #0xff00ff00ff00ff
; CHECK-NEXT:    ushr v1.8h, v1.8h, #7
; CHECK-NEXT:    mls v0.8h, v1.8h, v2.8h
; CHECK-NEXT:    ret
  %rem = urem <8 x i16> %x, splat (i16 255)
  ret <8 x i16> %rem
}

define <16 x i16> @urem_v16i16_by_255(<16 x i16> %x) {
; CHECK-LABEL: urem_v16i16_by_255:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov w8, #32897 // =0x8081
; CHECK-NEXT:    dup v2.8h, w8
; CHECK-NEXT:    umull2 v3.4s, v0.8h, v2.8h
; CHECK-NEXT:    umull v4.4s, v0.4h, v2.4h
; CHECK-NEXT:    umull2 v5.4s, v1.8h, v2.8h
; CHECK-NEXT:    umull v2.4s, v1.4h, v2.4h
; CHECK-NEXT:    uzp2 v3.8h, v4.8h, v3.8h
; CHECK-NEXT:    movi v4.2d, #0xff00ff00ff00ff
; CHECK-NEXT:    uzp2 v2.8h, v2.8h, v5.8h
; CHECK-NEXT:    ushr v3.8h, v3.8h, #7
; CHECK-NEXT:    ushr v2.8h, v2.8h, #7
; CHECK-NEXT:    mls v0.8h, v3.8h, v4.8h
; CHECK-NEXT:    mls v1.8h, v2.8h, v4.8h
; CHECK-NEXT:    ret
  %rem = urem <16 x i16> %x, splat (i16 255)
  ret <16 x i16> %rem
}

define <8 x i16> @udiv_exact_v8i16_by_255(<8 x i16> %x) {
; CHECK-LABEL: udiv_exact_v8i16_by_255:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mvni v1.8h, #1, lsl #8
; CHECK-NEXT:    mul v0.8h, v0.8h, v1.8h
; CHECK-NEXT:    ret
  %div = udiv exact <8 x i16> %x, splat (i16 255)
  ret <8 x i16> %div
}

define <16 x i16> @udiv_exact_v16i16_by_255(<16 x i16> %x) {
; CHECK-LABEL: udiv_exact_v16i16_by_255:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mvni v2.8h, #1, lsl #8
; CHECK-NEXT:    mul v0.8h, v0.8h, v2.8h
; CHECK-NEXT:    mul v1.8h, v1.8h, v2.8h
; CHECK-NEXT:    ret
  %div = udiv exact <16 x i16> %x, splat (i16 255)
  ret <16 x i16> %div
}