llvm/test/CodeGen/AArch64/uaddlp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple aarch64-none-linux-gnu < %s | FileCheck %s

define <8 x i16> @vpaddlq_u8_v1(<16 x i8> %a) {
; CHECK-LABEL: vpaddlq_u8_v1:
; CHECK:       // %bb.0: // %start
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    ret
start:
  %_0 = tail call <8 x i16> @llvm.aarch64.neon.uaddlp.v8i16.v16i8(<16 x i8> %a)
  ret <8 x i16> %_0
}

define <8 x i16> @vpaddlq_v16i8(<16 x i8> %a) {
; CHECK-LABEL: vpaddlq_v16i8:
; CHECK:       // %bb.0: // %start
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    ret
start:
  %0 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
  %1 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
  %2 = zext <8 x i8> %0 to <8 x i16>
  %3 = zext <8 x i8> %1 to <8 x i16>
  %4 = add nuw nsw <8 x i16> %2, %3
  ret <8 x i16> %4
}

define <4 x i32> @vpaddlq_v8i16(<8 x i16> %a) {
; CHECK-LABEL: vpaddlq_v8i16:
; CHECK:       // %bb.0: // %start
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    ret
start:
  %0 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
  %1 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %2 = zext <4 x i16> %0 to <4 x i32>
  %3 = zext <4 x i16> %1 to <4 x i32>
  %4 = add <4 x i32> %2, %3
  ret <4 x i32> %4
}

define <2 x i64> @vpaddlq_v4i32(<4 x i32> %a) {
; CHECK-LABEL: vpaddlq_v4i32:
; CHECK:       // %bb.0: // %start
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    ret
start:
  %0 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 0, i32 2>
  %1 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 1, i32 3>
  %2 = zext <2 x i32> %0 to <2 x i64>
  %3 = zext <2 x i32> %1 to <2 x i64>
  %4 = add <2 x i64> %2, %3
  ret <2 x i64> %4
}

define <8 x i16> @vpaddlq_v16i8_neg(<16 x i8> %a) {
; CHECK-LABEL: vpaddlq_v16i8_neg:
; CHECK:       // %bb.0: // %start
; CHECK-NEXT:    adrp x8, .LCPI4_0
; CHECK-NEXT:    adrp x9, .LCPI4_1
; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI4_0]
; CHECK-NEXT:    ldr d2, [x9, :lo12:.LCPI4_1]
; CHECK-NEXT:    tbl v1.8b, { v0.16b }, v1.8b
; CHECK-NEXT:    tbl v0.8b, { v0.16b }, v2.8b
; CHECK-NEXT:    uaddl v0.8h, v1.8b, v0.8b
; CHECK-NEXT:    ret
start:
  %0 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 0, i32 1, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
  %1 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 2, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
  %2 = zext <8 x i8> %0 to <8 x i16>
  %3 = zext <8 x i8> %1 to <8 x i16>
  %4 = add nuw nsw <8 x i16> %2, %3
  ret <8 x i16> %4
}

define <8 x i16> @vpaddlq_v16i8_zext_shuffle(<16 x i8> %a) unnamed_addr {
; CHECK-LABEL: vpaddlq_v16i8_zext_shuffle:
; CHECK:       // %bb.0: // %start
; CHECK-NEXT:    uaddlp v0.8h, v0.16b
; CHECK-NEXT:    ret
start:
  %0 = zext <16 x i8> %a to <16 x i16>
  %1 = shufflevector <16 x i16> %0, <16 x i16> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
  %2 = shufflevector <16 x i16> %0, <16 x i16> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
  %3 = add nuw nsw <8 x i16> %1, %2
  ret <8 x i16> %3
}

define <4 x i32> @vpaddlq_v8i16_zext_shuffle(<8 x i16> %a) unnamed_addr {
; CHECK-LABEL: vpaddlq_v8i16_zext_shuffle:
; CHECK:       // %bb.0: // %start
; CHECK-NEXT:    uaddlp v0.4s, v0.8h
; CHECK-NEXT:    ret
start:
  %0 = zext <8 x i16> %a to <8 x i32>
  %1 = shufflevector <8 x i32> %0, <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
  %2 = shufflevector <8 x i32> %0, <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %3 = add nuw nsw <4 x i32> %1, %2
  ret <4 x i32> %3
}

define <2 x i64> @vpaddlq_v4i32_zext_shuffle(<4 x i32> %a) unnamed_addr {
; CHECK-LABEL: vpaddlq_v4i32_zext_shuffle:
; CHECK:       // %bb.0: // %start
; CHECK-NEXT:    uaddlp v0.2d, v0.4s
; CHECK-NEXT:    ret
start:
  %0 = zext <4 x i32> %a to <4 x i64>
  %1 = shufflevector <4 x i64> %0, <4 x i64> poison, <2 x i32> <i32 0, i32 2>
  %2 = shufflevector <4 x i64> %0, <4 x i64> poison, <2 x i32> <i32 1, i32 3>
  %3 = add nuw nsw <2 x i64> %1, %2
  ret <2 x i64> %3
}

define <4 x i32> @vpaddlq_v8i16_zext_shuffle_neg(<8 x i16> %a) unnamed_addr {
; CHECK-LABEL: vpaddlq_v8i16_zext_shuffle_neg:
; CHECK:       // %bb.0: // %start
; CHECK-NEXT:    ushll2 v1.4s, v0.8h, #0
; CHECK-NEXT:    ushll v0.4s, v0.4h, #0
; CHECK-NEXT:    uzp1 v2.4s, v0.4s, v1.4s
; CHECK-NEXT:    uzp2 v3.4s, v0.4s, v1.4s
; CHECK-NEXT:    mov v2.s[2], v0.s[3]
; CHECK-NEXT:    mov v3.s[1], v1.s[0]
; CHECK-NEXT:    add v0.4s, v2.4s, v3.4s
; CHECK-NEXT:    ret
start:
  %0 = zext <8 x i16> %a to <8 x i32>
  %1 = shufflevector <8 x i32> %0, <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 3, i32 6>
  %2 = shufflevector <8 x i32> %0, <8 x i32> poison, <4 x i32> <i32 1, i32 4, i32 5, i32 7>
  %3 = add nuw nsw <4 x i32> %1, %2
  ret <4 x i32> %3
}

define <8 x i16> @vpaddlq_v16i8_sext_shuffle(<16 x i8> %a) unnamed_addr {
; CHECK-LABEL: vpaddlq_v16i8_sext_shuffle:
; CHECK:       // %bb.0: // %start
; CHECK-NEXT:    saddlp v0.8h, v0.16b
; CHECK-NEXT:    ret
start:
  %0 = sext <16 x i8> %a to <16 x i16>
  %1 = shufflevector <16 x i16> %0, <16 x i16> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
  %2 = shufflevector <16 x i16> %0, <16 x i16> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
  %3 = add nuw nsw <8 x i16> %1, %2
  ret <8 x i16> %3
}

define <4 x i32> @vpaddlq_v8i16_sext_shuffle(<8 x i16> %a) unnamed_addr {
; CHECK-LABEL: vpaddlq_v8i16_sext_shuffle:
; CHECK:       // %bb.0: // %start
; CHECK-NEXT:    saddlp v0.4s, v0.8h
; CHECK-NEXT:    ret
start:
  %0 = sext <8 x i16> %a to <8 x i32>
  %1 = shufflevector <8 x i32> %0, <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
  %2 = shufflevector <8 x i32> %0, <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %3 = add nuw nsw <4 x i32> %1, %2
  ret <4 x i32> %3
}

define <2 x i64> @vpaddlq_v4i32_sext_shuffle(<4 x i32> %a) unnamed_addr {
; CHECK-LABEL: vpaddlq_v4i32_sext_shuffle:
; CHECK:       // %bb.0: // %start
; CHECK-NEXT:    saddlp v0.2d, v0.4s
; CHECK-NEXT:    ret
start:
  %0 = sext <4 x i32> %a to <4 x i64>
  %1 = shufflevector <4 x i64> %0, <4 x i64> poison, <2 x i32> <i32 0, i32 2>
  %2 = shufflevector <4 x i64> %0, <4 x i64> poison, <2 x i32> <i32 1, i32 3>
  %3 = add nuw nsw <2 x i64> %1, %2
  ret <2 x i64> %3
}

define <2 x i64> @vpaddlq_v4i32_sext_shuffle_neg(<4 x i32> %a) unnamed_addr {
; CHECK-LABEL: vpaddlq_v4i32_sext_shuffle_neg:
; CHECK:       // %bb.0: // %start
; CHECK-NEXT:    sshll v1.2d, v0.2s, #0
; CHECK-NEXT:    saddw2 v0.2d, v1.2d, v0.4s
; CHECK-NEXT:    ret
start:
  %0 = sext <4 x i32> %a to <4 x i64>
  %1 = shufflevector <4 x i64> %0, <4 x i64> poison, <2 x i32> <i32 0, i32 1>
  %2 = shufflevector <4 x i64> %0, <4 x i64> poison, <2 x i32> <i32 2, i32 3>
  %3 = add nuw nsw <2 x i64> %1, %2
  ret <2 x i64> %3
}