llvm/test/CodeGen/AArch64/subreg-liveness-fix-subreg-to-reg-implicit-def.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=aarch64 -run-pass=aarch64-srlt-define-superregs -enable-subreg-liveness -o - %s | FileCheck %s
--- |
  target triple = "aarch64"

  define void @test_implicit_def_w1_to_x1() { entry: unreachable }
  define void @test_implicit_def_dead_w1_to_dead_x1() { entry: unreachable }
  define void @test_implicit_def_d0_to_q0_and_d1_to_q1() { entry: unreachable }
  define void @test_implicit_def_d0_d1_d2_to_q0_q1_q2() { entry: unreachable }
  define void @test_implicit_def_d0_d1_d2_to_z0_z1_z2_with_sve() "target-features"="+sve" { entry: unreachable }

---
name: test_implicit_def_w1_to_x1
isSSA: false
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x1

    ; CHECK-LABEL: name: test_implicit_def_w1_to_x1
    ; CHECK: liveins: $x1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: renamable $x0 = COPY $x1
    ; CHECK-NEXT: renamable $w1 = ORRWrr $wzr, renamable $w0, implicit-def renamable $x1
    ; CHECK-NEXT: RET_ReallyLR implicit $x1, implicit $x0
    renamable $x0 = COPY $x1
    renamable $w1 = ORRWrr $wzr, renamable $w0
    RET_ReallyLR implicit $x1, implicit $x0
...
---
name: test_implicit_def_dead_w1_to_dead_x1
isSSA: false
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x1

    ; CHECK-LABEL: name: test_implicit_def_dead_w1_to_dead_x1
    ; CHECK: liveins: $x1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: renamable $x0 = COPY $x1
    ; CHECK-NEXT: dead renamable $w1 = ORRWrr $wzr, renamable $w0, implicit-def dead renamable $x1
    ; CHECK-NEXT: RET_ReallyLR implicit $x0
    renamable $x0 = COPY $x1
    dead renamable $w1 = ORRWrr $wzr, renamable $w0
    RET_ReallyLR implicit $x0
...
---
name: test_implicit_def_d0_to_q0_and_d1_to_q1
isSSA: false
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $d0, $d1, $x1

    ; CHECK-LABEL: name: test_implicit_def_d0_to_q0_and_d1_to_q1
    ; CHECK: liveins: $d0, $d1, $x1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: early-clobber $x1, renamable $d0, renamable $d1 = LDPDpre renamable $x1, 16, implicit-def renamable $q0, implicit-def renamable $q1 :: (load (s64))
    ; CHECK-NEXT: STPDi renamable $d0, renamable $d1, renamable $x1, 0 :: (store (s64))
    ; CHECK-NEXT: RET undef $lr
    early-clobber $x1, renamable $d0, renamable $d1 = LDPDpre renamable $x1, 16 :: (load (s64))
    STPDi renamable $d0, renamable $d1, renamable $x1, 0 :: (store (s64))
    RET undef $lr
...
---
name: test_implicit_def_d0_d1_d2_to_q0_q1_q2
isSSA: false
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0.entry:
    liveins: $x0, $x1, $lr, $fp

    ; CHECK-LABEL: name: test_implicit_def_d0_d1_d2_to_q0_q1_q2
    ; CHECK: liveins: $x0, $x1, $lr, $fp
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: renamable $x0, renamable $d0_d1_d2 = LD3Threev8b_POST killed renamable $x0, $xzr, implicit-def renamable $q0_q1_q2
    ; CHECK-NEXT: FAKE_USE $x0
    ; CHECK-NEXT: FAKE_USE $d0_d1_d2
    ; CHECK-NEXT: RET undef $lr
    renamable $x0, renamable $d0_d1_d2 = LD3Threev8b_POST killed renamable $x0, $xzr
    FAKE_USE $x0
    FAKE_USE $d0_d1_d2
    RET undef $lr
...
---
name: test_implicit_def_d0_d1_d2_to_z0_z1_z2_with_sve
isSSA: false
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0.entry:
    liveins: $x0, $x1, $lr, $fp

    ; CHECK-LABEL: name: test_implicit_def_d0_d1_d2_to_z0_z1_z2_with_sve
    ; CHECK: liveins: $x0, $x1, $lr, $fp
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: renamable $x0, renamable $d0_d1_d2 = LD3Threev8b_POST killed renamable $x0, $xzr, implicit-def renamable $z0_z1_z2
    ; CHECK-NEXT: FAKE_USE $x0
    ; CHECK-NEXT: FAKE_USE $d0_d1_d2
    ; CHECK-NEXT: RET undef $lr
    renamable $x0, renamable $d0_d1_d2 = LD3Threev8b_POST killed renamable $x0, $xzr
    FAKE_USE $x0
    FAKE_USE $d0_d1_d2
    RET undef $lr
...