llvm/test/CodeGen/AArch64/masked-urem-scalable.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple aarch64 -mattr=+sve < %s | FileCheck %s

define <vscale x 4 x i16> @urem_nxv4i16(<vscale x 4 x i16> %x, <vscale x 4 x i16> %y, <vscale x 4 x i1> %m) {
; CHECK-LABEL: urem_nxv4i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    and z1.s, z1.s, #0xffff
; CHECK-NEXT:    mov z2.s, #1 // =0x1
; CHECK-NEXT:    and z0.s, z0.s, #0xffff
; CHECK-NEXT:    sel z1.s, p0, z1.s, z2.s
; CHECK-NEXT:    ptrue p0.s
; CHECK-NEXT:    movprfx z2, z0
; CHECK-NEXT:    udiv z2.s, p0/m, z2.s, z1.s
; CHECK-NEXT:    mls z0.s, p0/m, z2.s, z1.s
; CHECK-NEXT:    ret
  %res = call <vscale x 4 x i16> @llvm.masked.urem(<vscale x 4 x i16> %x, <vscale x 4 x i16> %y, <vscale x 4 x i1> %m)
  ret <vscale x 4 x i16> %res
}

define <vscale x 4 x i32> @urem_nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i1> %m) {
; CHECK-LABEL: urem_nxv4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov z2.s, #1 // =0x1
; CHECK-NEXT:    sel z1.s, p0, z1.s, z2.s
; CHECK-NEXT:    ptrue p0.s
; CHECK-NEXT:    movprfx z2, z0
; CHECK-NEXT:    udiv z2.s, p0/m, z2.s, z1.s
; CHECK-NEXT:    mls z0.s, p0/m, z2.s, z1.s
; CHECK-NEXT:    ret
  %res = call <vscale x 4 x i32> @llvm.masked.urem(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i1> %m)
  ret <vscale x 4 x i32> %res
}

define <vscale x 8 x i32> @urem_nxv8i32(<vscale x 8 x i32> %x, <vscale x 8 x i32> %y, <vscale x 8 x i1> %m) {
; CHECK-LABEL: urem_nxv8i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov z4.s, #1 // =0x1
; CHECK-NEXT:    punpklo p1.h, p0.b
; CHECK-NEXT:    punpkhi p0.h, p0.b
; CHECK-NEXT:    sel z2.s, p1, z2.s, z4.s
; CHECK-NEXT:    sel z3.s, p0, z3.s, z4.s
; CHECK-NEXT:    ptrue p1.s
; CHECK-NEXT:    movprfx z5, z0
; CHECK-NEXT:    udiv z5.s, p1/m, z5.s, z2.s
; CHECK-NEXT:    movprfx z4, z1
; CHECK-NEXT:    udiv z4.s, p1/m, z4.s, z3.s
; CHECK-NEXT:    mls z0.s, p1/m, z5.s, z2.s
; CHECK-NEXT:    mls z1.s, p1/m, z4.s, z3.s
; CHECK-NEXT:    ret
  %res = call <vscale x 8 x i32> @llvm.masked.urem(<vscale x 8 x i32> %x, <vscale x 8 x i32> %y, <vscale x 8 x i1> %m)
  ret <vscale x 8 x i32> %res
}

define <vscale x 8 x i16> @urem_nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i1> %m) {
; CHECK-LABEL: urem_nxv8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov z2.h, #1 // =0x1
; CHECK-NEXT:    uunpklo z4.s, z0.h
; CHECK-NEXT:    sel z1.h, p0, z1.h, z2.h
; CHECK-NEXT:    uunpkhi z2.s, z0.h
; CHECK-NEXT:    ptrue p0.s
; CHECK-NEXT:    uunpkhi z3.s, z1.h
; CHECK-NEXT:    udiv z2.s, p0/m, z2.s, z3.s
; CHECK-NEXT:    uunpklo z3.s, z1.h
; CHECK-NEXT:    udivr z3.s, p0/m, z3.s, z4.s
; CHECK-NEXT:    ptrue p0.h
; CHECK-NEXT:    uzp1 z2.h, z3.h, z2.h
; CHECK-NEXT:    mls z0.h, p0/m, z2.h, z1.h
; CHECK-NEXT:    ret
  %res = call <vscale x 8 x i16> @llvm.masked.urem(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i1> %m)
  ret <vscale x 8 x i16> %res
}

define <vscale x 2 x i64> @urem_nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i1> %m) {
; CHECK-LABEL: urem_nxv2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov z2.d, #1 // =0x1
; CHECK-NEXT:    sel z1.d, p0, z1.d, z2.d
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    movprfx z2, z0
; CHECK-NEXT:    udiv z2.d, p0/m, z2.d, z1.d
; CHECK-NEXT:    mls z0.d, p0/m, z2.d, z1.d
; CHECK-NEXT:    ret
  %res = call <vscale x 2 x i64> @llvm.masked.urem(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i1> %m)
  ret <vscale x 2 x i64> %res
}