llvm/test/CodeGen/AArch64/extend-bool-vector-load.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-LE
; RUN: llc -mtriple=aarch64_be-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-BE

define <16 x i8> @sext_v16i1_v16i8(ptr %p) {
; CHECK-LE-LABEL: sext_v16i1_v16i8:
; CHECK-LE:       // %bb.0:
; CHECK-LE-NEXT:    adrp x8, .LCPI0_0
; CHECK-LE-NEXT:    ldr h1, [x0]
; CHECK-LE-NEXT:    ldr q0, [x8, :lo12:.LCPI0_0]
; CHECK-LE-NEXT:    adrp x8, .LCPI0_1
; CHECK-LE-NEXT:    tbl v0.16b, { v1.16b }, v0.16b
; CHECK-LE-NEXT:    ldr q1, [x8, :lo12:.LCPI0_1]
; CHECK-LE-NEXT:    cmtst v0.16b, v0.16b, v1.16b
; CHECK-LE-NEXT:    ret
;
; CHECK-BE-LABEL: sext_v16i1_v16i8:
; CHECK-BE:       // %bb.0:
; CHECK-BE-NEXT:    ldr h0, [x0]
; CHECK-BE-NEXT:    adrp x8, .LCPI0_0
; CHECK-BE-NEXT:    add x8, x8, :lo12:.LCPI0_0
; CHECK-BE-NEXT:    ld1 { v1.16b }, [x8]
; CHECK-BE-NEXT:    adrp x8, .LCPI0_1
; CHECK-BE-NEXT:    add x8, x8, :lo12:.LCPI0_1
; CHECK-BE-NEXT:    rev16 v0.16b, v0.16b
; CHECK-BE-NEXT:    tbl v0.16b, { v0.16b }, v1.16b
; CHECK-BE-NEXT:    ld1 { v1.16b }, [x8]
; CHECK-BE-NEXT:    cmtst v0.16b, v0.16b, v1.16b
; CHECK-BE-NEXT:    rev64 v0.16b, v0.16b
; CHECK-BE-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
; CHECK-BE-NEXT:    ret
    %l = load <16 x i1>, ptr %p, align 4
    %e = sext <16 x i1> %l to <16 x i8>
    ret <16 x i8>  %e
}

define <16 x i8> @zext_v16i1_v16i8(ptr %p) {
; CHECK-LE-LABEL: zext_v16i1_v16i8:
; CHECK-LE:       // %bb.0:
; CHECK-LE-NEXT:    adrp x8, .LCPI1_0
; CHECK-LE-NEXT:    ldr h1, [x0]
; CHECK-LE-NEXT:    ldr q0, [x8, :lo12:.LCPI1_0]
; CHECK-LE-NEXT:    adrp x8, .LCPI1_1
; CHECK-LE-NEXT:    tbl v0.16b, { v1.16b }, v0.16b
; CHECK-LE-NEXT:    ldr q1, [x8, :lo12:.LCPI1_1]
; CHECK-LE-NEXT:    cmtst v0.16b, v0.16b, v1.16b
; CHECK-LE-NEXT:    ushr v0.16b, v0.16b, #7
; CHECK-LE-NEXT:    ret
;
; CHECK-BE-LABEL: zext_v16i1_v16i8:
; CHECK-BE:       // %bb.0:
; CHECK-BE-NEXT:    ldr h0, [x0]
; CHECK-BE-NEXT:    adrp x8, .LCPI1_0
; CHECK-BE-NEXT:    add x8, x8, :lo12:.LCPI1_0
; CHECK-BE-NEXT:    ld1 { v1.16b }, [x8]
; CHECK-BE-NEXT:    adrp x8, .LCPI1_1
; CHECK-BE-NEXT:    add x8, x8, :lo12:.LCPI1_1
; CHECK-BE-NEXT:    rev16 v0.16b, v0.16b
; CHECK-BE-NEXT:    tbl v0.16b, { v0.16b }, v1.16b
; CHECK-BE-NEXT:    ld1 { v1.16b }, [x8]
; CHECK-BE-NEXT:    cmtst v0.16b, v0.16b, v1.16b
; CHECK-BE-NEXT:    ushr v0.16b, v0.16b, #7
; CHECK-BE-NEXT:    rev64 v0.16b, v0.16b
; CHECK-BE-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
; CHECK-BE-NEXT:    ret
    %l = load <16 x i1>, ptr %p, align 4
    %e = zext <16 x i1> %l to <16 x i8>
    ret <16 x i8>  %e
}

define <32 x i8> @sext_v32i1_v32i8(ptr %p) {
; CHECK-LE-LABEL: sext_v32i1_v32i8:
; CHECK-LE:       // %bb.0:
; CHECK-LE-NEXT:    adrp x8, .LCPI2_0
; CHECK-LE-NEXT:    adrp x9, .LCPI2_2
; CHECK-LE-NEXT:    ldr s1, [x0]
; CHECK-LE-NEXT:    ldr q0, [x8, :lo12:.LCPI2_0]
; CHECK-LE-NEXT:    ldr q2, [x9, :lo12:.LCPI2_2]
; CHECK-LE-NEXT:    adrp x8, .LCPI2_1
; CHECK-LE-NEXT:    tbl v0.16b, { v1.16b }, v0.16b
; CHECK-LE-NEXT:    tbl v1.16b, { v1.16b }, v2.16b
; CHECK-LE-NEXT:    ldr q2, [x8, :lo12:.LCPI2_1]
; CHECK-LE-NEXT:    cmtst v0.16b, v0.16b, v2.16b
; CHECK-LE-NEXT:    cmtst v1.16b, v1.16b, v2.16b
; CHECK-LE-NEXT:    ret
;
; CHECK-BE-LABEL: sext_v32i1_v32i8:
; CHECK-BE:       // %bb.0:
; CHECK-BE-NEXT:    ldr s0, [x0]
; CHECK-BE-NEXT:    adrp x8, .LCPI2_0
; CHECK-BE-NEXT:    add x8, x8, :lo12:.LCPI2_0
; CHECK-BE-NEXT:    ld1 { v1.16b }, [x8]
; CHECK-BE-NEXT:    adrp x8, .LCPI2_2
; CHECK-BE-NEXT:    add x8, x8, :lo12:.LCPI2_2
; CHECK-BE-NEXT:    rev32 v0.16b, v0.16b
; CHECK-BE-NEXT:    ld1 { v2.16b }, [x8]
; CHECK-BE-NEXT:    adrp x8, .LCPI2_1
; CHECK-BE-NEXT:    add x8, x8, :lo12:.LCPI2_1
; CHECK-BE-NEXT:    tbl v1.16b, { v0.16b }, v1.16b
; CHECK-BE-NEXT:    tbl v0.16b, { v0.16b }, v2.16b
; CHECK-BE-NEXT:    ld1 { v2.16b }, [x8]
; CHECK-BE-NEXT:    cmtst v1.16b, v1.16b, v2.16b
; CHECK-BE-NEXT:    cmtst v0.16b, v0.16b, v2.16b
; CHECK-BE-NEXT:    rev64 v0.16b, v0.16b
; CHECK-BE-NEXT:    rev64 v1.16b, v1.16b
; CHECK-BE-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
; CHECK-BE-NEXT:    ext v1.16b, v1.16b, v1.16b, #8
; CHECK-BE-NEXT:    ret
    %l = load <32 x i1>, ptr %p, align 4
    %e = sext <32 x i1> %l to <32 x i8>
    ret <32 x i8> %e
}

define <4 x i32> @sext_v4i1_v4i32(ptr %p) {
; CHECK-LE-LABEL: sext_v4i1_v4i32:
; CHECK-LE:       // %bb.0:
; CHECK-LE-NEXT:    ldr b0, [x0]
; CHECK-LE-NEXT:    adrp x8, .LCPI3_0
; CHECK-LE-NEXT:    ldr q1, [x8, :lo12:.LCPI3_0]
; CHECK-LE-NEXT:    dup v0.4s, v0.s[0]
; CHECK-LE-NEXT:    cmtst v0.4s, v0.4s, v1.4s
; CHECK-LE-NEXT:    ret
;
; CHECK-BE-LABEL: sext_v4i1_v4i32:
; CHECK-BE:       // %bb.0:
; CHECK-BE-NEXT:    ldr b0, [x0]
; CHECK-BE-NEXT:    adrp x8, .LCPI3_0
; CHECK-BE-NEXT:    add x8, x8, :lo12:.LCPI3_0
; CHECK-BE-NEXT:    ld1 { v1.4s }, [x8]
; CHECK-BE-NEXT:    dup v0.4s, v0.s[0]
; CHECK-BE-NEXT:    cmtst v0.4s, v0.4s, v1.4s
; CHECK-BE-NEXT:    rev64 v0.4s, v0.4s
; CHECK-BE-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
; CHECK-BE-NEXT:    ret
    %l = load <4 x i1>, ptr %p, align 4
    %e = sext <4 x i1> %l to <4 x i32>
    ret <4 x i32>  %e
}

define <16 x i8> @sext_v16i1_volatile(ptr %p) {
; CHECK-LE-LABEL: sext_v16i1_volatile:
; CHECK-LE:       // %bb.0:
; CHECK-LE-NEXT:    ldrh w8, [x0]
; CHECK-LE-NEXT:    and w10, w8, #0x1
; CHECK-LE-NEXT:    ubfx w9, w8, #1, #1
; CHECK-LE-NEXT:    fmov s0, w10
; CHECK-LE-NEXT:    mov v0.b[1], w9
; CHECK-LE-NEXT:    ubfx w9, w8, #2, #1
; CHECK-LE-NEXT:    mov v0.b[2], w9
; CHECK-LE-NEXT:    ubfx w9, w8, #3, #1
; CHECK-LE-NEXT:    mov v0.b[3], w9
; CHECK-LE-NEXT:    ubfx w9, w8, #4, #1
; CHECK-LE-NEXT:    mov v0.b[4], w9
; CHECK-LE-NEXT:    ubfx w9, w8, #5, #1
; CHECK-LE-NEXT:    mov v0.b[5], w9
; CHECK-LE-NEXT:    ubfx w9, w8, #6, #1
; CHECK-LE-NEXT:    mov v0.b[6], w9
; CHECK-LE-NEXT:    ubfx w9, w8, #7, #1
; CHECK-LE-NEXT:    mov v0.b[7], w9
; CHECK-LE-NEXT:    ubfx w9, w8, #8, #1
; CHECK-LE-NEXT:    mov v0.b[8], w9
; CHECK-LE-NEXT:    ubfx w9, w8, #9, #1
; CHECK-LE-NEXT:    mov v0.b[9], w9
; CHECK-LE-NEXT:    ubfx w9, w8, #10, #1
; CHECK-LE-NEXT:    mov v0.b[10], w9
; CHECK-LE-NEXT:    ubfx w9, w8, #11, #1
; CHECK-LE-NEXT:    mov v0.b[11], w9
; CHECK-LE-NEXT:    ubfx w9, w8, #12, #1
; CHECK-LE-NEXT:    mov v0.b[12], w9
; CHECK-LE-NEXT:    ubfx w9, w8, #13, #1
; CHECK-LE-NEXT:    mov v0.b[13], w9
; CHECK-LE-NEXT:    ubfx w9, w8, #14, #1
; CHECK-LE-NEXT:    lsr w8, w8, #15
; CHECK-LE-NEXT:    mov v0.b[14], w9
; CHECK-LE-NEXT:    mov v0.b[15], w8
; CHECK-LE-NEXT:    shl v0.16b, v0.16b, #7
; CHECK-LE-NEXT:    cmlt v0.16b, v0.16b, #0
; CHECK-LE-NEXT:    ret
;
; CHECK-BE-LABEL: sext_v16i1_volatile:
; CHECK-BE:       // %bb.0:
; CHECK-BE-NEXT:    ldrh w8, [x0]
; CHECK-BE-NEXT:    lsr w9, w8, #15
; CHECK-BE-NEXT:    ubfx w10, w8, #14, #1
; CHECK-BE-NEXT:    fmov s0, w9
; CHECK-BE-NEXT:    ubfx w9, w8, #13, #1
; CHECK-BE-NEXT:    mov v0.b[1], w10
; CHECK-BE-NEXT:    mov v0.b[2], w9
; CHECK-BE-NEXT:    ubfx w9, w8, #12, #1
; CHECK-BE-NEXT:    mov v0.b[3], w9
; CHECK-BE-NEXT:    ubfx w9, w8, #11, #1
; CHECK-BE-NEXT:    mov v0.b[4], w9
; CHECK-BE-NEXT:    ubfx w9, w8, #10, #1
; CHECK-BE-NEXT:    mov v0.b[5], w9
; CHECK-BE-NEXT:    ubfx w9, w8, #9, #1
; CHECK-BE-NEXT:    mov v0.b[6], w9
; CHECK-BE-NEXT:    ubfx w9, w8, #8, #1
; CHECK-BE-NEXT:    mov v0.b[7], w9
; CHECK-BE-NEXT:    ubfx w9, w8, #7, #1
; CHECK-BE-NEXT:    mov v0.b[8], w9
; CHECK-BE-NEXT:    ubfx w9, w8, #6, #1
; CHECK-BE-NEXT:    mov v0.b[9], w9
; CHECK-BE-NEXT:    ubfx w9, w8, #5, #1
; CHECK-BE-NEXT:    mov v0.b[10], w9
; CHECK-BE-NEXT:    ubfx w9, w8, #4, #1
; CHECK-BE-NEXT:    mov v0.b[11], w9
; CHECK-BE-NEXT:    ubfx w9, w8, #3, #1
; CHECK-BE-NEXT:    mov v0.b[12], w9
; CHECK-BE-NEXT:    ubfx w9, w8, #2, #1
; CHECK-BE-NEXT:    mov v0.b[13], w9
; CHECK-BE-NEXT:    ubfx w9, w8, #1, #1
; CHECK-BE-NEXT:    and w8, w8, #0x1
; CHECK-BE-NEXT:    mov v0.b[14], w9
; CHECK-BE-NEXT:    mov v0.b[15], w8
; CHECK-BE-NEXT:    shl v0.16b, v0.16b, #7
; CHECK-BE-NEXT:    cmlt v0.16b, v0.16b, #0
; CHECK-BE-NEXT:    rev64 v0.16b, v0.16b
; CHECK-BE-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
; CHECK-BE-NEXT:    ret
    %l = load volatile <16 x i1>, ptr %p, align 4
    %e = sext <16 x i1> %l to <16 x i8>
    ret <16 x i8>  %e
}

define <12 x i8> @sext_v12i1_v12i8(ptr %p) {
; CHECK-LE-LABEL: sext_v12i1_v12i8:
; CHECK-LE:       // %bb.0:
; CHECK-LE-NEXT:    ldrh w8, [x0]
; CHECK-LE-NEXT:    and w10, w8, #0x1
; CHECK-LE-NEXT:    ubfx w9, w8, #1, #1
; CHECK-LE-NEXT:    fmov s0, w10
; CHECK-LE-NEXT:    mov v0.b[1], w9
; CHECK-LE-NEXT:    ubfx w9, w8, #2, #1
; CHECK-LE-NEXT:    mov v0.b[2], w9
; CHECK-LE-NEXT:    ubfx w9, w8, #3, #1
; CHECK-LE-NEXT:    mov v0.b[3], w9
; CHECK-LE-NEXT:    ubfx w9, w8, #4, #1
; CHECK-LE-NEXT:    mov v0.b[4], w9
; CHECK-LE-NEXT:    ubfx w9, w8, #5, #1
; CHECK-LE-NEXT:    mov v0.b[5], w9
; CHECK-LE-NEXT:    ubfx w9, w8, #6, #1
; CHECK-LE-NEXT:    mov v0.b[6], w9
; CHECK-LE-NEXT:    ubfx w9, w8, #7, #1
; CHECK-LE-NEXT:    mov v0.b[7], w9
; CHECK-LE-NEXT:    ubfx w9, w8, #8, #1
; CHECK-LE-NEXT:    mov v0.b[8], w9
; CHECK-LE-NEXT:    ubfx w9, w8, #9, #1
; CHECK-LE-NEXT:    mov v0.b[9], w9
; CHECK-LE-NEXT:    ubfx w9, w8, #10, #1
; CHECK-LE-NEXT:    lsr w8, w8, #11
; CHECK-LE-NEXT:    mov v0.b[10], w9
; CHECK-LE-NEXT:    mov v0.b[11], w8
; CHECK-LE-NEXT:    shl v0.16b, v0.16b, #7
; CHECK-LE-NEXT:    cmlt v0.16b, v0.16b, #0
; CHECK-LE-NEXT:    ret
;
; CHECK-BE-LABEL: sext_v12i1_v12i8:
; CHECK-BE:       // %bb.0:
; CHECK-BE-NEXT:    ldrh w8, [x0]
; CHECK-BE-NEXT:    lsr w9, w8, #11
; CHECK-BE-NEXT:    ubfx w10, w8, #10, #1
; CHECK-BE-NEXT:    fmov s0, w9
; CHECK-BE-NEXT:    ubfx w9, w8, #9, #1
; CHECK-BE-NEXT:    mov v0.b[1], w10
; CHECK-BE-NEXT:    mov v0.b[2], w9
; CHECK-BE-NEXT:    ubfx w9, w8, #8, #1
; CHECK-BE-NEXT:    mov v0.b[3], w9
; CHECK-BE-NEXT:    ubfx w9, w8, #7, #1
; CHECK-BE-NEXT:    mov v0.b[4], w9
; CHECK-BE-NEXT:    ubfx w9, w8, #6, #1
; CHECK-BE-NEXT:    mov v0.b[5], w9
; CHECK-BE-NEXT:    ubfx w9, w8, #5, #1
; CHECK-BE-NEXT:    mov v0.b[6], w9
; CHECK-BE-NEXT:    ubfx w9, w8, #4, #1
; CHECK-BE-NEXT:    mov v0.b[7], w9
; CHECK-BE-NEXT:    ubfx w9, w8, #3, #1
; CHECK-BE-NEXT:    mov v0.b[8], w9
; CHECK-BE-NEXT:    ubfx w9, w8, #2, #1
; CHECK-BE-NEXT:    mov v0.b[9], w9
; CHECK-BE-NEXT:    ubfx w9, w8, #1, #1
; CHECK-BE-NEXT:    and w8, w8, #0x1
; CHECK-BE-NEXT:    mov v0.b[10], w9
; CHECK-BE-NEXT:    mov v0.b[11], w8
; CHECK-BE-NEXT:    shl v0.16b, v0.16b, #7
; CHECK-BE-NEXT:    cmlt v0.16b, v0.16b, #0
; CHECK-BE-NEXT:    rev64 v0.16b, v0.16b
; CHECK-BE-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
; CHECK-BE-NEXT:    ret
    %l = load <12 x i1>, ptr %p, align 4
    %e = sext <12 x i1> %l to <12 x i8>
    ret <12 x i8>  %e
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK: {{.*}}