llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll - llvm-project - Git at Google

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK-NOFPRCVT
 ; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fprcvt,+fullfp16 | FileCheck %s --check-prefixes=CHECK
 ; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+sme,+neon,+fullfp16,+fprcvt -force-streaming | FileCheck %s --check-prefixes=CHECK-SME
 ; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+sve,+neon,+fullfp16,+fprcvt -force-streaming-compatible | FileCheck %s --check-prefixes=CHECK-SVE
 ; RUN: llc < %s -mtriple aarch64-unknown-unknown -global-isel -global-isel-abort=2 -mattr=+fprcvt,+fullfp16 2>&1  | FileCheck %s --check-prefixes=CHECK

 ;
 ; FPTOI
 ;

 define float @test_fptosi_f16_i32_simd(half %a)  {
 ; CHECK-NOFPRCVT-LABEL: test_fptosi_f16_i32_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzs w8, h0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: test_fptosi_f16_i32_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs s0, h0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: test_fptosi_f16_i32_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzs s0, h0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: test_fptosi_f16_i32_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzs s0, h0
 ; CHECK-SVE-NEXT:    ret
   %r = fptosi half %a to i32
   %bc = bitcast i32 %r to float
   ret float %bc
 }

 define double @test_fptosi_f16_i64_simd(half %a)  {
 ; CHECK-NOFPRCVT-LABEL: test_fptosi_f16_i64_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzs x8, h0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: test_fptosi_f16_i64_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs d0, h0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: test_fptosi_f16_i64_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzs d0, h0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: test_fptosi_f16_i64_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzs d0, h0
 ; CHECK-SVE-NEXT:    ret
   %r = fptosi half %a to i64
   %bc = bitcast i64 %r to double
   ret double %bc
 }

 define float @test_fptosi_f64_i32_simd(double %a)  {
 ; CHECK-NOFPRCVT-LABEL: test_fptosi_f64_i32_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzs w8, d0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: test_fptosi_f64_i32_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs s0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: test_fptosi_f64_i32_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzs s0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: test_fptosi_f64_i32_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzs s0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = fptosi double %a to i32
   %bc = bitcast i32 %r to float
   ret float %bc
 }

 define double @test_fptosi_f32_i64_simd(float %a)  {
 ; CHECK-NOFPRCVT-LABEL: test_fptosi_f32_i64_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzs x8, s0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: test_fptosi_f32_i64_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs d0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: test_fptosi_f32_i64_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzs d0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: test_fptosi_f32_i64_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzs d0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = fptosi float %a to i64
   %bc = bitcast i64 %r to double
   ret double %bc
 }

 define double @test_fptosi_f64_i64_simd(double %a)  {
 ; CHECK-NOFPRCVT-LABEL: test_fptosi_f64_i64_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzs d0, d0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: test_fptosi_f64_i64_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs d0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: test_fptosi_f64_i64_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzs d0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: test_fptosi_f64_i64_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzs d0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = fptosi double %a to i64
   %bc = bitcast i64 %r to double
   ret double %bc
 }


 define float @test_fptosi_f32_i32_simd(float %a)  {
 ; CHECK-NOFPRCVT-LABEL: test_fptosi_f32_i32_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzs s0, s0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: test_fptosi_f32_i32_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs s0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: test_fptosi_f32_i32_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzs s0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: test_fptosi_f32_i32_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzs s0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = fptosi float %a to i32
   %bc = bitcast i32 %r to float
   ret float %bc
 }

 define float @test_fptoui_f16_i32_simd(half %a)  {
 ; CHECK-NOFPRCVT-LABEL: test_fptoui_f16_i32_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzu w8, h0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: test_fptoui_f16_i32_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu s0, h0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: test_fptoui_f16_i32_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzu s0, h0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: test_fptoui_f16_i32_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzu s0, h0
 ; CHECK-SVE-NEXT:    ret
   %r = fptoui half %a to i32
   %bc = bitcast i32 %r to float
   ret float %bc
 }

 define double @test_fptoui_f16_i64_simd(half %a)  {
 ; CHECK-NOFPRCVT-LABEL: test_fptoui_f16_i64_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzu x8, h0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: test_fptoui_f16_i64_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu d0, h0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: test_fptoui_f16_i64_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzu d0, h0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: test_fptoui_f16_i64_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzu d0, h0
 ; CHECK-SVE-NEXT:    ret
   %r = fptoui half %a to i64
   %bc = bitcast i64 %r to double
   ret double %bc
 }

 define float @test_fptoui_f64_i32_simd(double %a)  {
 ; CHECK-NOFPRCVT-LABEL: test_fptoui_f64_i32_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzu w8, d0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: test_fptoui_f64_i32_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu s0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: test_fptoui_f64_i32_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzu s0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: test_fptoui_f64_i32_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzu s0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = fptoui double %a to i32
   %bc = bitcast i32 %r to float
   ret float %bc
 }

 define double @test_fptoui_f32_i64_simd(float %a)  {
 ; CHECK-NOFPRCVT-LABEL: test_fptoui_f32_i64_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzu x8, s0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: test_fptoui_f32_i64_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu d0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: test_fptoui_f32_i64_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzu d0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: test_fptoui_f32_i64_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzu d0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = fptoui float %a to i64
   %bc = bitcast i64 %r to double
   ret double %bc
 }

 define double @test_fptoui_f64_i64_simd(double %a)  {
 ; CHECK-NOFPRCVT-LABEL: test_fptoui_f64_i64_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzu d0, d0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: test_fptoui_f64_i64_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu d0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: test_fptoui_f64_i64_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzu d0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: test_fptoui_f64_i64_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzu d0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = fptoui double %a to i64
   %bc = bitcast i64 %r to double
   ret double %bc
 }


 define float @test_fptoui_f32_i32_simd(float %a)  {
 ; CHECK-NOFPRCVT-LABEL: test_fptoui_f32_i32_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzu s0, s0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: test_fptoui_f32_i32_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu s0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: test_fptoui_f32_i32_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzu s0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: test_fptoui_f32_i32_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzu s0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = fptoui float %a to i32
   %bc = bitcast i32 %r to float
   ret float %bc
 }

 ;
 ; FPTOI rounding
 ;


 define double @fcvtas_ds_round_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtas_ds_round_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtas x8, s0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtas_ds_round_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtas d0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtas_ds_round_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtas d0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtas_ds_round_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtas d0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.round.f32(float %a)
   %i = fptosi float %r to i64
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define float @fcvtas_sd_round_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtas_sd_round_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtas w8, d0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtas_sd_round_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtas s0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtas_sd_round_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtas s0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtas_sd_round_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtas s0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.round.f64(double %a)
   %i = fptosi double %r to i32
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define float @fcvtas_ss_round_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtas_ss_round_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtas s0, s0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtas_ss_round_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtas s0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtas_ss_round_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtas s0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtas_ss_round_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtas s0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.round.f32(float %a)
   %i = fptosi float %r to i32
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtas_dd_round_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtas_dd_round_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtas d0, d0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtas_dd_round_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtas d0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtas_dd_round_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtas d0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtas_dd_round_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtas d0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.round.f64(double %a)
   %i = fptosi double %r to i64
   %bc = bitcast i64 %i to double
   ret double %bc
 }


 define double @fcvtau_ds_round_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtau_ds_round_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtau x8, s0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtau_ds_round_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtau d0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtau_ds_round_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtau d0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtau_ds_round_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtau d0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.round.f32(float %a)
   %i = fptoui float %r to i64
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define float @fcvtau_sd_round_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtau_sd_round_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtau w8, d0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtau_sd_round_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtau s0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtau_sd_round_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtau s0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtau_sd_round_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtau s0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.round.f64(double %a)
   %i = fptoui double %r to i32
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define float @fcvtau_ss_round_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtau_ss_round_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtas s0, s0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtau_ss_round_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtas s0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtau_ss_round_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtas s0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtau_ss_round_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtas s0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.round.f32(float %a)
   %i = fptosi float %r to i32
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtau_dd_round_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtau_dd_round_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtas d0, d0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtau_dd_round_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtas d0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtau_dd_round_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtas d0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtau_dd_round_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtas d0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.round.f64(double %a)
   %i = fptosi double %r to i64
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define double @fcvtns_ds_roundeven_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtns_ds_roundeven_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtns x8, s0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtns_ds_roundeven_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtns d0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtns_ds_roundeven_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtns d0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtns_ds_roundeven_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtns d0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.roundeven.f32(float %a)
   %i = fptosi float %r to i64
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define float @fcvtns_sd_roundeven_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtns_sd_roundeven_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtns w8, d0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtns_sd_roundeven_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtns s0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtns_sd_roundeven_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtns s0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtns_sd_roundeven_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtns s0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.roundeven.f64(double %a)
   %i = fptosi double %r to i32
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define float @fcvtns_ss_roundeven_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtns_ss_roundeven_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtns s0, s0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtns_ss_roundeven_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtns s0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtns_ss_roundeven_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtns s0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtns_ss_roundeven_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtns s0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.roundeven.f32(float %a)
   %i = fptosi float %r to i32
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtns_dd_roundeven_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtns_dd_roundeven_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtns d0, d0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtns_dd_roundeven_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtns d0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtns_dd_roundeven_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtns d0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtns_dd_roundeven_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtns d0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.roundeven.f64(double %a)
   %i = fptosi double %r to i64
   %bc = bitcast i64 %i to double
   ret double %bc
 }


 define double @fcvtnu_ds_roundeven_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtnu_ds_roundeven_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtnu x8, s0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtnu_ds_roundeven_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtnu d0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtnu_ds_roundeven_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtnu d0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtnu_ds_roundeven_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtnu d0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.roundeven.f32(float %a)
   %i = fptoui float %r to i64
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define float @fcvtnu_sd_roundeven_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtnu_sd_roundeven_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtnu w8, d0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtnu_sd_roundeven_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtnu s0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtnu_sd_roundeven_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtnu s0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtnu_sd_roundeven_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtnu s0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.roundeven.f64(double %a)
   %i = fptoui double %r to i32
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define float @fcvtnu_ss_roundeven_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtnu_ss_roundeven_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtnu s0, s0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtnu_ss_roundeven_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtnu s0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtnu_ss_roundeven_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtnu s0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtnu_ss_roundeven_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtnu s0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.roundeven.f32(float %a)
   %i = fptoui float %r to i32
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtnu_dd_roundeven_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtnu_dd_roundeven_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtnu d0, d0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtnu_dd_roundeven_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtnu d0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtnu_dd_roundeven_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtnu d0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtnu_dd_roundeven_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtnu d0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.roundeven.f64(double %a)
   %i = fptoui double %r to i64
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define double @fcvtms_ds_round_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtms_ds_round_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtms x8, s0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtms_ds_round_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtms d0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtms_ds_round_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtms d0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtms_ds_round_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtms d0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.floor.f32(float %a)
   %i = fptosi float %r to i64
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define float @fcvtms_sd_round_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtms_sd_round_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtms w8, d0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtms_sd_round_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtms s0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtms_sd_round_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtms s0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtms_sd_round_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtms s0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.floor.f64(double %a)
   %i = fptosi double %r to i32
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define float @fcvtms_ss_round_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtms_ss_round_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtms s0, s0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtms_ss_round_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtms s0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtms_ss_round_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtms s0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtms_ss_round_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtms s0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.floor.f32(float %a)
   %i = fptosi float %r to i32
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtms_dd_round_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtms_dd_round_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtms d0, d0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtms_dd_round_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtms d0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtms_dd_round_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtms d0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtms_dd_round_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtms d0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.floor.f64(double %a)
   %i = fptosi double %r to i64
   %bc = bitcast i64 %i to double
   ret double %bc
 }


 define double @fcvtmu_ds_round_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtmu_ds_round_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtmu x8, s0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtmu_ds_round_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtmu d0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtmu_ds_round_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtmu d0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtmu_ds_round_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtmu d0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.floor.f32(float %a)
   %i = fptoui float %r to i64
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define float @fcvtmu_sd_round_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtmu_sd_round_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtmu w8, d0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtmu_sd_round_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtmu s0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtmu_sd_round_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtmu s0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtmu_sd_round_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtmu s0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.floor.f64(double %a)
   %i = fptoui double %r to i32
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define float @fcvtmu_ss_round_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtmu_ss_round_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtms s0, s0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtmu_ss_round_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtms s0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtmu_ss_round_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtms s0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtmu_ss_round_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtms s0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.floor.f32(float %a)
   %i = fptosi float %r to i32
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtmu_dd_round_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtmu_dd_round_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtms d0, d0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtmu_dd_round_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtms d0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtmu_dd_round_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtms d0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtmu_dd_round_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtms d0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.floor.f64(double %a)
   %i = fptosi double %r to i64
   %bc = bitcast i64 %i to double
   ret double %bc
 }


 define double @fcvtps_ds_round_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtps_ds_round_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtps x8, s0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtps_ds_round_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtps d0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtps_ds_round_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtps d0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtps_ds_round_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtps d0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.ceil.f32(float %a)
   %i = fptosi float %r to i64
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define float @fcvtps_sd_round_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtps_sd_round_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtps w8, d0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtps_sd_round_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtps s0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtps_sd_round_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtps s0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtps_sd_round_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtps s0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.ceil.f64(double %a)
   %i = fptosi double %r to i32
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define float @fcvtps_ss_round_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtps_ss_round_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtps s0, s0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtps_ss_round_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtps s0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtps_ss_round_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtps s0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtps_ss_round_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtps s0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.ceil.f32(float %a)
   %i = fptosi float %r to i32
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtps_dd_round_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtps_dd_round_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtps d0, d0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtps_dd_round_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtps d0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtps_dd_round_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtps d0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtps_dd_round_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtps d0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.ceil.f64(double %a)
   %i = fptosi double %r to i64
   %bc = bitcast i64 %i to double
   ret double %bc
 }


 define double @fcvtpu_ds_round_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtpu_ds_round_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtpu x8, s0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtpu_ds_round_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtpu d0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtpu_ds_round_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtpu d0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtpu_ds_round_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtpu d0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.ceil.f32(float %a)
   %i = fptoui float %r to i64
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define float @fcvtpu_sd_round_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtpu_sd_round_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtpu w8, d0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtpu_sd_round_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtpu s0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtpu_sd_round_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtpu s0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtpu_sd_round_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtpu s0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.ceil.f64(double %a)
   %i = fptoui double %r to i32
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define float @fcvtpu_ss_round_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtpu_ss_round_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtps s0, s0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtpu_ss_round_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtps s0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtpu_ss_round_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtps s0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtpu_ss_round_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtps s0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.ceil.f32(float %a)
   %i = fptosi float %r to i32
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtpu_dd_round_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtpu_dd_round_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtps d0, d0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtpu_dd_round_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtps d0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtpu_dd_round_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtps d0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtpu_dd_round_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtps d0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.ceil.f64(double %a)
   %i = fptosi double %r to i64
   %bc = bitcast i64 %i to double
   ret double %bc
 }


 define double @fcvtzs_ds_round_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtzs_ds_round_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzs x8, s0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtzs_ds_round_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs d0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtzs_ds_round_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzs d0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtzs_ds_round_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzs d0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.trunc.f32(float %a)
   %i = fptosi float %r to i64
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define float @fcvtzs_sd_round_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtzs_sd_round_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzs w8, d0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtzs_sd_round_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs s0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtzs_sd_round_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzs s0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtzs_sd_round_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzs s0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.trunc.f64(double %a)
   %i = fptosi double %r to i32
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define float @fcvtzs_ss_round_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtzs_ss_round_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzs s0, s0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtzs_ss_round_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs s0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtzs_ss_round_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzs s0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtzs_ss_round_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzs s0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.trunc.f32(float %a)
   %i = fptosi float %r to i32
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtzs_dd_round_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtzs_dd_round_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzs d0, d0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtzs_dd_round_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs d0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtzs_dd_round_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzs d0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtzs_dd_round_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzs d0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.trunc.f64(double %a)
   %i = fptosi double %r to i64
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define double @fcvtzu_ds_round_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtzu_ds_round_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzu x8, s0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtzu_ds_round_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu d0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtzu_ds_round_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzu d0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtzu_ds_round_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzu d0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.trunc.f32(float %a)
   %i = fptoui float %r to i64
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define float @fcvtzu_sd_round_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtzu_sd_round_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzu w8, d0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtzu_sd_round_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu s0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtzu_sd_round_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzu s0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtzu_sd_round_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzu s0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.trunc.f64(double %a)
   %i = fptoui double %r to i32
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define float @fcvtzu_ss_round_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtzu_ss_round_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzs s0, s0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtzu_ss_round_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs s0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtzu_ss_round_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzs s0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtzu_ss_round_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzs s0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.trunc.f32(float %a)
   %i = fptosi float %r to i32
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtzu_dd_round_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtzu_dd_round_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzs d0, d0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtzu_dd_round_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs d0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtzu_dd_round_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzs d0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtzu_dd_round_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzs d0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.trunc.f64(double %a)
   %i = fptosi double %r to i64
   %bc = bitcast i64 %i to double
   ret double %bc
 }


 ;
 ; FPTOI saturating
 ;

 define float @fcvtzs_sh_sat_simd(half %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtzs_sh_sat_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzs w8, h0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtzs_sh_sat_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs s0, h0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtzs_sh_sat_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzs s0, h0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtzs_sh_sat_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzs s0, h0
 ; CHECK-SVE-NEXT:    ret
   %i = call i32 @llvm.fptosi.sat.i32.f16(half %a)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtzs_dh_sat_simd(half %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtzs_dh_sat_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzs x8, h0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtzs_dh_sat_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs d0, h0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtzs_dh_sat_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzs d0, h0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtzs_dh_sat_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzs d0, h0
 ; CHECK-SVE-NEXT:    ret
   %i = call i64 @llvm.fptosi.sat.i64.f16(half %a)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define double @fcvtzs_ds_sat_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtzs_ds_sat_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzs x8, s0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtzs_ds_sat_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs d0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtzs_ds_sat_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzs d0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtzs_ds_sat_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzs d0, s0
 ; CHECK-SVE-NEXT:    ret
   %i = call i64 @llvm.fptosi.sat.i64.f32(float %a)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define float @fcvtzs_sd_sat_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtzs_sd_sat_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzs w8, d0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtzs_sd_sat_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs s0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtzs_sd_sat_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzs s0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtzs_sd_sat_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzs s0, d0
 ; CHECK-SVE-NEXT:    ret
   %i = call i32 @llvm.fptosi.sat.i32.f64(double %a)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define float @fcvtzs_ss_sat_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtzs_ss_sat_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzs s0, s0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtzs_ss_sat_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs s0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtzs_ss_sat_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzs s0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtzs_ss_sat_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzs s0, s0
 ; CHECK-SVE-NEXT:    ret
   %i = call i32 @llvm.fptosi.sat.i32.f32(float %a)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtzs_dd_sat_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtzs_dd_sat_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzs d0, d0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtzs_dd_sat_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs d0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtzs_dd_sat_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzs d0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtzs_dd_sat_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzs d0, d0
 ; CHECK-SVE-NEXT:    ret
   %i = call i64 @llvm.fptosi.sat.i64.f64(double %a)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define float @fcvtzu_sh_sat_simd(half %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtzu_sh_sat_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzu w8, h0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtzu_sh_sat_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu s0, h0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtzu_sh_sat_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzu s0, h0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtzu_sh_sat_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzu s0, h0
 ; CHECK-SVE-NEXT:    ret
   %i = call i32 @llvm.fptoui.sat.i32.f16(half %a)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtzu_dh_sat_simd(half %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtzu_dh_sat_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzu x8, h0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtzu_dh_sat_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu d0, h0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtzu_dh_sat_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzu d0, h0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtzu_dh_sat_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzu d0, h0
 ; CHECK-SVE-NEXT:    ret
   %i = call i64 @llvm.fptoui.sat.i64.f16(half %a)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define double @fcvtzu_ds_sat_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtzu_ds_sat_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzu x8, s0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtzu_ds_sat_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu d0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtzu_ds_sat_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzu d0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtzu_ds_sat_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzu d0, s0
 ; CHECK-SVE-NEXT:    ret
   %i = call i64 @llvm.fptoui.sat.i64.f32(float %a)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define float @fcvtzu_sd_sat_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtzu_sd_sat_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzu w8, d0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtzu_sd_sat_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu s0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtzu_sd_sat_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzu s0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtzu_sd_sat_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzu s0, d0
 ; CHECK-SVE-NEXT:    ret
   %i = call i32 @llvm.fptoui.sat.i32.f64(double %a)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define float @fcvtzu_ss_sat_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtzu_ss_sat_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzs s0, s0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtzu_ss_sat_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs s0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtzu_ss_sat_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzs s0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtzu_ss_sat_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzs s0, s0
 ; CHECK-SVE-NEXT:    ret
   %i = call i32 @llvm.fptosi.sat.i32.f32(float %a)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtzu_dd_sat_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtzu_dd_sat_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzs d0, d0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtzu_dd_sat_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs d0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtzu_dd_sat_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzs d0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtzu_dd_sat_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzs d0, d0
 ; CHECK-SVE-NEXT:    ret
   %i = call i64 @llvm.fptosi.sat.i64.f64(double %a)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 ;
 ; FPTOI saturating with rounding
 ;

 define float @fcvtas_sh_simd(half %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtas_sh_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtas w8, h0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtas_sh_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtas s0, h0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtas_sh_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtas s0, h0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtas_sh_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtas s0, h0
 ; CHECK-SVE-NEXT:    ret
   %r = call half @llvm.round.f16(half %a)
   %i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtas_dh_simd(half %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtas_dh_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtas x8, h0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtas_dh_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtas d0, h0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtas_dh_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtas d0, h0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtas_dh_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtas d0, h0
 ; CHECK-SVE-NEXT:    ret
   %r = call half @llvm.round.f16(half %a)
   %i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define double @fcvtas_ds_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtas_ds_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtas x8, s0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtas_ds_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtas d0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtas_ds_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtas d0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtas_ds_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtas d0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.round.f32(float %a)
   %i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define float @fcvtas_sd_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtas_sd_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtas w8, d0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtas_sd_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtas s0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtas_sd_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtas s0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtas_sd_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtas s0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.round.f64(double %a)
   %i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define float @fcvtas_ss_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtas_ss_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtas s0, s0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtas_ss_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtas s0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtas_ss_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtas s0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtas_ss_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtas s0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.round.f32(float %a)
   %i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtas_dd_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtas_dd_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtas d0, d0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtas_dd_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtas d0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtas_dd_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtas d0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtas_dd_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtas d0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.round.f64(double %a)
   %i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define float @fcvtau_sh_simd(half %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtau_sh_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtau w8, h0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtau_sh_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtau s0, h0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtau_sh_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtau s0, h0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtau_sh_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtau s0, h0
 ; CHECK-SVE-NEXT:    ret
   %r = call half @llvm.round.f16(half %a)
   %i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtau_dh_simd(half %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtau_dh_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtau x8, h0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtau_dh_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtau d0, h0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtau_dh_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtau d0, h0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtau_dh_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtau d0, h0
 ; CHECK-SVE-NEXT:    ret
   %r = call half @llvm.round.f16(half %a)
   %i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define double @fcvtau_ds_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtau_ds_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtau x8, s0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtau_ds_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtau d0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtau_ds_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtau d0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtau_ds_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtau d0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.round.f32(float %a)
   %i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define float @fcvtau_sd_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtau_sd_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtau w8, d0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtau_sd_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtau s0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtau_sd_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtau s0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtau_sd_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtau s0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.round.f64(double %a)
   %i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define float @fcvtau_ss_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtau_ss_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtas s0, s0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtau_ss_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtas s0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtau_ss_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtas s0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtau_ss_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtas s0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.round.f32(float %a)
   %i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtau_dd_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtau_dd_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtas d0, d0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtau_dd_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtas d0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtau_dd_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtas d0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtau_dd_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtas d0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.round.f64(double %a)
   %i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define float @fcvtns_sh_simd(half %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtns_sh_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtns w8, h0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtns_sh_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtns s0, h0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtns_sh_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtns s0, h0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtns_sh_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtns s0, h0
 ; CHECK-SVE-NEXT:    ret
   %r = call half @llvm.roundeven.f16(half %a)
   %i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtns_dh_simd(half %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtns_dh_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtns x8, h0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtns_dh_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtns d0, h0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtns_dh_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtns d0, h0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtns_dh_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtns d0, h0
 ; CHECK-SVE-NEXT:    ret
   %r = call half @llvm.roundeven.f16(half %a)
   %i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define double @fcvtns_ds_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtns_ds_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtns x8, s0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtns_ds_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtns d0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtns_ds_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtns d0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtns_ds_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtns d0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.roundeven.f32(float %a)
   %i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define float @fcvtns_sd_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtns_sd_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtns w8, d0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtns_sd_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtns s0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtns_sd_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtns s0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtns_sd_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtns s0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.roundeven.f64(double %a)
   %i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define float @fcvtns_ss_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtns_ss_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtns s0, s0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtns_ss_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtns s0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtns_ss_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtns s0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtns_ss_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtns s0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.roundeven.f32(float %a)
   %i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtns_dd_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtns_dd_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtns d0, d0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtns_dd_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtns d0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtns_dd_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtns d0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtns_dd_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtns d0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.roundeven.f64(double %a)
   %i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define float @fcvtnu_sh_simd(half %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtnu_sh_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtnu w8, h0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtnu_sh_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtnu s0, h0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtnu_sh_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtnu s0, h0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtnu_sh_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtnu s0, h0
 ; CHECK-SVE-NEXT:    ret
   %r = call half @llvm.roundeven.f16(half %a)
   %i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtnu_dh_simd(half %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtnu_dh_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtnu x8, h0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtnu_dh_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtnu d0, h0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtnu_dh_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtnu d0, h0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtnu_dh_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtnu d0, h0
 ; CHECK-SVE-NEXT:    ret
   %r = call half @llvm.roundeven.f16(half %a)
   %i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define double @fcvtnu_ds_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtnu_ds_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtnu x8, s0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtnu_ds_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtnu d0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtnu_ds_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtnu d0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtnu_ds_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtnu d0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.roundeven.f32(float %a)
   %i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define float @fcvtnu_sd_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtnu_sd_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtnu w8, d0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtnu_sd_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtnu s0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtnu_sd_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtnu s0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtnu_sd_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtnu s0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.roundeven.f64(double %a)
   %i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define float @fcvtnu_ss_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtnu_ss_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtnu s0, s0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtnu_ss_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtnu s0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtnu_ss_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtnu s0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtnu_ss_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtnu s0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.roundeven.f32(float %a)
   %i = call i32 @llvm.fptoui.sat.i32.f32(float %r)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtnu_dd_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtnu_dd_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtnu d0, d0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtnu_dd_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtnu d0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtnu_dd_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtnu d0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtnu_dd_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtnu d0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.roundeven.f64(double %a)
   %i = call i64 @llvm.fptoui.sat.i64.f64(double %r)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define float @fcvtms_sh_simd(half %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtms_sh_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtms w8, h0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtms_sh_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtms s0, h0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtms_sh_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtms s0, h0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtms_sh_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtms s0, h0
 ; CHECK-SVE-NEXT:    ret
   %r = call half @llvm.floor.f16(half %a)
   %i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtms_dh_simd(half %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtms_dh_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtms x8, h0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtms_dh_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtms d0, h0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtms_dh_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtms d0, h0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtms_dh_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtms d0, h0
 ; CHECK-SVE-NEXT:    ret
   %r = call half @llvm.floor.f16(half %a)
   %i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define double @fcvtms_ds_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtms_ds_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtms x8, s0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtms_ds_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtms d0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtms_ds_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtms d0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtms_ds_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtms d0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.floor.f32(float %a)
   %i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define float @fcvtms_sd_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtms_sd_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtms w8, d0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtms_sd_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtms s0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtms_sd_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtms s0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtms_sd_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtms s0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.floor.f64(double %a)
   %i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define float @fcvtms_ss_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtms_ss_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtms s0, s0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtms_ss_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtms s0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtms_ss_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtms s0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtms_ss_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtms s0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.floor.f32(float %a)
   %i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtms_dd_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtms_dd_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtms d0, d0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtms_dd_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtms d0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtms_dd_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtms d0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtms_dd_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtms d0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.floor.f64(double %a)
   %i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define float @fcvtmu_sh_simd(half %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtmu_sh_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtmu w8, h0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtmu_sh_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtmu s0, h0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtmu_sh_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtmu s0, h0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtmu_sh_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtmu s0, h0
 ; CHECK-SVE-NEXT:    ret
   %r = call half @llvm.floor.f16(half %a)
   %i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtmu_dh_simd(half %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtmu_dh_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtmu x8, h0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtmu_dh_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtmu d0, h0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtmu_dh_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtmu d0, h0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtmu_dh_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtmu d0, h0
 ; CHECK-SVE-NEXT:    ret
   %r = call half @llvm.floor.f16(half %a)
   %i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define double @fcvtmu_ds_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtmu_ds_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtmu x8, s0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtmu_ds_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtmu d0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtmu_ds_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtmu d0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtmu_ds_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtmu d0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.floor.f32(float %a)
   %i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define float @fcvtmu_sd_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtmu_sd_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtmu w8, d0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtmu_sd_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtmu s0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtmu_sd_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtmu s0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtmu_sd_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtmu s0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.floor.f64(double %a)
   %i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define float @fcvtmu_ss_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtmu_ss_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtms s0, s0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtmu_ss_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtms s0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtmu_ss_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtms s0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtmu_ss_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtms s0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.floor.f32(float %a)
   %i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtmu_dd_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtmu_dd_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtms d0, d0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtmu_dd_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtms d0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtmu_dd_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtms d0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtmu_dd_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtms d0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.floor.f64(double %a)
   %i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define float @fcvtps_sh_simd(half %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtps_sh_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtps w8, h0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtps_sh_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtps s0, h0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtps_sh_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtps s0, h0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtps_sh_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtps s0, h0
 ; CHECK-SVE-NEXT:    ret
   %r = call half @llvm.ceil.f16(half %a)
   %i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtps_dh_simd(half %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtps_dh_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtps x8, h0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtps_dh_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtps d0, h0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtps_dh_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtps d0, h0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtps_dh_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtps d0, h0
 ; CHECK-SVE-NEXT:    ret
   %r = call half @llvm.ceil.f16(half %a)
   %i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define double @fcvtps_ds_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtps_ds_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtps x8, s0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtps_ds_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtps d0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtps_ds_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtps d0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtps_ds_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtps d0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.ceil.f32(float %a)
   %i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define float @fcvtps_sd_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtps_sd_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtps w8, d0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtps_sd_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtps s0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtps_sd_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtps s0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtps_sd_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtps s0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.ceil.f64(double %a)
   %i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define float @fcvtps_ss_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtps_ss_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtps s0, s0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtps_ss_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtps s0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtps_ss_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtps s0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtps_ss_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtps s0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.ceil.f32(float %a)
   %i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtps_dd_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtps_dd_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtps d0, d0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtps_dd_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtps d0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtps_dd_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtps d0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtps_dd_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtps d0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.ceil.f64(double %a)
   %i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define float @fcvtpu_sh_simd(half %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtpu_sh_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtpu w8, h0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtpu_sh_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtpu s0, h0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtpu_sh_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtpu s0, h0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtpu_sh_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtpu s0, h0
 ; CHECK-SVE-NEXT:    ret
   %r = call half @llvm.ceil.f16(half %a)
   %i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtpu_dh_simd(half %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtpu_dh_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtpu x8, h0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtpu_dh_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtpu d0, h0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtpu_dh_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtpu d0, h0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtpu_dh_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtpu d0, h0
 ; CHECK-SVE-NEXT:    ret
   %r = call half @llvm.ceil.f16(half %a)
   %i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define double @fcvtpu_ds_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtpu_ds_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtpu x8, s0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtpu_ds_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtpu d0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtpu_ds_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtpu d0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtpu_ds_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtpu d0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.ceil.f32(float %a)
   %i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define float @fcvtpu_sd_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtpu_sd_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtpu w8, d0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtpu_sd_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtpu s0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtpu_sd_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtpu s0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtpu_sd_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtpu s0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.ceil.f64(double %a)
   %i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define float @fcvtpu_ss_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtpu_ss_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtps s0, s0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtpu_ss_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtps s0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtpu_ss_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtps s0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtpu_ss_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtps s0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.ceil.f32(float %a)
   %i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtpu_dd_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtpu_dd_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtps d0, d0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtpu_dd_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtps d0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtpu_dd_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtps d0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtpu_dd_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtps d0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.ceil.f64(double %a)
   %i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define float @fcvtzs_sh_simd(half %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtzs_sh_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzs w8, h0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtzs_sh_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs s0, h0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtzs_sh_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzs s0, h0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtzs_sh_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzs s0, h0
 ; CHECK-SVE-NEXT:    ret
   %r = call half @llvm.trunc.f16(half %a)
   %i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtzs_dh_simd(half %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtzs_dh_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzs x8, h0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtzs_dh_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs d0, h0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtzs_dh_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzs d0, h0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtzs_dh_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzs d0, h0
 ; CHECK-SVE-NEXT:    ret
   %r = call half @llvm.trunc.f16(half %a)
   %i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define double @fcvtzs_ds_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtzs_ds_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzs x8, s0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtzs_ds_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs d0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtzs_ds_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzs d0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtzs_ds_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzs d0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.trunc.f32(float %a)
   %i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define float @fcvtzs_sd_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtzs_sd_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzs w8, d0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtzs_sd_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs s0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtzs_sd_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzs s0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtzs_sd_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzs s0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.trunc.f64(double %a)
   %i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define float @fcvtzs_ss_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtzs_ss_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzs s0, s0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtzs_ss_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs s0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtzs_ss_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzs s0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtzs_ss_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzs s0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.trunc.f32(float %a)
   %i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtzs_dd_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtzs_dd_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzs d0, d0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtzs_dd_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs d0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtzs_dd_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzs d0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtzs_dd_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzs d0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.trunc.f64(double %a)
   %i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define float @fcvtzu_sh_simd(half %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtzu_sh_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzu w8, h0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtzu_sh_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu s0, h0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtzu_sh_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzu s0, h0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtzu_sh_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzu s0, h0
 ; CHECK-SVE-NEXT:    ret
   %r = call half @llvm.trunc.f16(half %a)
   %i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtzu_dh_simd(half %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtzu_dh_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzu x8, h0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtzu_dh_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu d0, h0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtzu_dh_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzu d0, h0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtzu_dh_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzu d0, h0
 ; CHECK-SVE-NEXT:    ret
   %r = call half @llvm.trunc.f16(half %a)
   %i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define double @fcvtzu_ds_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtzu_ds_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzu x8, s0
 ; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtzu_ds_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu d0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtzu_ds_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzu d0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtzu_ds_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzu d0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.trunc.f32(float %a)
   %i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
   %bc = bitcast i64 %i to double
   ret double %bc
 }

 define float @fcvtzu_sd_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtzu_sd_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzu w8, d0
 ; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtzu_sd_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu s0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtzu_sd_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzu s0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtzu_sd_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzu s0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.trunc.f64(double %a)
   %i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define float @fcvtzu_ss_simd(float %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtzu_ss_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzu s0, s0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtzu_ss_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu s0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtzu_ss_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzu s0, s0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtzu_ss_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzu s0, s0
 ; CHECK-SVE-NEXT:    ret
   %r = call float @llvm.trunc.f32(float %a)
   %i = call i32 @llvm.fptoui.sat.i32.f32(float %r)
   %bc = bitcast i32 %i to float
   ret float %bc
 }

 define double @fcvtzu_dd_simd(double %a) {
 ; CHECK-NOFPRCVT-LABEL: fcvtzu_dd_simd:
 ; CHECK-NOFPRCVT:       // %bb.0:
 ; CHECK-NOFPRCVT-NEXT:    fcvtzu d0, d0
 ; CHECK-NOFPRCVT-NEXT:    ret
 ;
 ; CHECK-LABEL: fcvtzu_dd_simd:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzu d0, d0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-SME-LABEL: fcvtzu_dd_simd:
 ; CHECK-SME:       // %bb.0:
 ; CHECK-SME-NEXT:    fcvtzu d0, d0
 ; CHECK-SME-NEXT:    ret
 ;
 ; CHECK-SVE-LABEL: fcvtzu_dd_simd:
 ; CHECK-SVE:       // %bb.0:
 ; CHECK-SVE-NEXT:    fcvtzu d0, d0
 ; CHECK-SVE-NEXT:    ret
   %r = call double @llvm.trunc.f64(double %a)
   %i = call i64 @llvm.fptoui.sat.i64.f64(double %r)
   %bc = bitcast i64 %i to double
   ret double %bc
 }