llvm/test/CodeGen/RISCV/ghccc-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f,+d < %s | FileCheck %s

; Check the GHC call convention works (rv32)

@base  = external global i32 ; assigned to register: s1
@sp    = external global i32 ; assigned to register: s2
@hp    = external global i32 ; assigned to register: s3
@r1    = external global i32 ; assigned to register: s4
@r2    = external global i32 ; assigned to register: s5
@r3    = external global i32 ; assigned to register: s6
@r4    = external global i32 ; assigned to register: s7
@r5    = external global i32 ; assigned to register: s8
@r6    = external global i32 ; assigned to register: s9
@r7    = external global i32 ; assigned to register: s10
@splim = external global i32 ; assigned to register: s11

@f1 = external global float  ; assigned to register: fs0
@f2 = external global float  ; assigned to register: fs1
@f3 = external global float  ; assigned to register: fs2
@f4 = external global float  ; assigned to register: fs3
@f5 = external global float  ; assigned to register: fs4
@f6 = external global float  ; assigned to register: fs5

@d1 = external global double ; assigned to register: fs6
@d2 = external global double ; assigned to register: fs7
@d3 = external global double ; assigned to register: fs8
@d4 = external global double ; assigned to register: fs9
@d5 = external global double ; assigned to register: fs10
@d6 = external global double ; assigned to register: fs11

define ghccc void @foo() nounwind {
; CHECK-LABEL: foo:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    lui a0, %hi(d6)
; CHECK-NEXT:    fld fs11, %lo(d6)(a0)
; CHECK-NEXT:    lui a0, %hi(d5)
; CHECK-NEXT:    fld fs10, %lo(d5)(a0)
; CHECK-NEXT:    lui a0, %hi(d4)
; CHECK-NEXT:    fld fs9, %lo(d4)(a0)
; CHECK-NEXT:    lui a0, %hi(d3)
; CHECK-NEXT:    fld fs8, %lo(d3)(a0)
; CHECK-NEXT:    lui a0, %hi(d2)
; CHECK-NEXT:    fld fs7, %lo(d2)(a0)
; CHECK-NEXT:    lui a0, %hi(d1)
; CHECK-NEXT:    fld fs6, %lo(d1)(a0)
; CHECK-NEXT:    lui a0, %hi(f6)
; CHECK-NEXT:    flw fs5, %lo(f6)(a0)
; CHECK-NEXT:    lui a0, %hi(f5)
; CHECK-NEXT:    flw fs4, %lo(f5)(a0)
; CHECK-NEXT:    lui a0, %hi(f4)
; CHECK-NEXT:    flw fs3, %lo(f4)(a0)
; CHECK-NEXT:    lui a0, %hi(f3)
; CHECK-NEXT:    flw fs2, %lo(f3)(a0)
; CHECK-NEXT:    lui a0, %hi(f2)
; CHECK-NEXT:    flw fs1, %lo(f2)(a0)
; CHECK-NEXT:    lui a0, %hi(f1)
; CHECK-NEXT:    flw fs0, %lo(f1)(a0)
; CHECK-NEXT:    lui a0, %hi(splim)
; CHECK-NEXT:    lw s11, %lo(splim)(a0)
; CHECK-NEXT:    lui a0, %hi(r7)
; CHECK-NEXT:    lw s10, %lo(r7)(a0)
; CHECK-NEXT:    lui a0, %hi(r6)
; CHECK-NEXT:    lw s9, %lo(r6)(a0)
; CHECK-NEXT:    lui a0, %hi(r5)
; CHECK-NEXT:    lw s8, %lo(r5)(a0)
; CHECK-NEXT:    lui a0, %hi(r4)
; CHECK-NEXT:    lw s7, %lo(r4)(a0)
; CHECK-NEXT:    lui a0, %hi(r3)
; CHECK-NEXT:    lw s6, %lo(r3)(a0)
; CHECK-NEXT:    lui a0, %hi(r2)
; CHECK-NEXT:    lw s5, %lo(r2)(a0)
; CHECK-NEXT:    lui a0, %hi(r1)
; CHECK-NEXT:    lw s4, %lo(r1)(a0)
; CHECK-NEXT:    lui a0, %hi(hp)
; CHECK-NEXT:    lw s3, %lo(hp)(a0)
; CHECK-NEXT:    lui a0, %hi(sp)
; CHECK-NEXT:    lw s2, %lo(sp)(a0)
; CHECK-NEXT:    lui a0, %hi(base)
; CHECK-NEXT:    lw s1, %lo(base)(a0)
; CHECK-NEXT:    tail bar@plt
entry:
  %0  = load double, ptr @d6
  %1  = load double, ptr @d5
  %2  = load double, ptr @d4
  %3  = load double, ptr @d3
  %4  = load double, ptr @d2
  %5  = load double, ptr @d1
  %6  = load float, ptr @f6
  %7  = load float, ptr @f5
  %8  = load float, ptr @f4
  %9  = load float, ptr @f3
  %10 = load float, ptr @f2
  %11 = load float, ptr @f1
  %12 = load i32, ptr @splim
  %13 = load i32, ptr @r7
  %14 = load i32, ptr @r6
  %15 = load i32, ptr @r5
  %16 = load i32, ptr @r4
  %17 = load i32, ptr @r3
  %18 = load i32, ptr @r2
  %19 = load i32, ptr @r1
  %20 = load i32, ptr @hp
  %21 = load i32, ptr @sp
  %22 = load i32, ptr @base
  tail call ghccc void @bar(i32 %22, i32 %21, i32 %20, i32 %19, i32 %18, i32 %17, i32 %16, i32 %15, i32 %14, i32 %13, i32 %12,
                            float %11, float %10, float %9, float %8, float %7, float %6,
                            double %5, double %4, double %3, double %2, double %1, double %0) nounwind
  ret void
}

declare ghccc void @bar(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32,
                        float, float, float, float, float, float,
                        double, double, double, double, double, double)