llvm/test/Transforms/SLPVectorizer/X86/ashr-main-opcode-copyables.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -passes=slp-vectorizer -slp-threshold=-99999 -S -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s

; AShr is the main opcode. add/or are copyable and vectorize as ashr with zero shift.
define void @test_main_opcode(ptr %dst, i32 %x, i32 %y) {
; CHECK-LABEL: define void @test_main_opcode(
; CHECK-SAME: ptr [[DST:%.*]], i32 [[X:%.*]], i32 [[Y:%.*]]) {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[X]], i64 0
; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[Y]], i64 1
; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
; CHECK-NEXT:    [[TMP3:%.*]] = ashr <4 x i32> [[TMP2]], <i32 1, i32 2, i32 0, i32 0>
; CHECK-NEXT:    store <4 x i32> [[TMP3]], ptr [[DST]], align 4
; CHECK-NEXT:    ret void
;
entry:
  %ashr0 = ashr i32 %x, 1
  %ashr1 = ashr i32 %y, 2
  %add = add i32 %x, 0
  %or = or i32 %y, 0
  store i32 %ashr0, ptr %dst, align 4
  %d1 = getelementptr i32, ptr %dst, i32 1
  store i32 %ashr1, ptr %d1, align 4
  %d2 = getelementptr i32, ptr %dst, i32 2
  store i32 %add, ptr %d2, align 4
  %d3 = getelementptr i32, ptr %dst, i32 3
  store i32 %or, ptr %d3, align 4
  ret void
}

; AShr main opcode with copyables and trunc users for minbitwidth analysis.
define void @test_minbitwidth_trunc(ptr %dst, ptr %src) {
; CHECK-LABEL: define void @test_minbitwidth_trunc(
; CHECK-SAME: ptr [[DST:%.*]], ptr [[SRC:%.*]]) {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr [[SRC]], align 4
; CHECK-NEXT:    [[TMP1:%.*]] = load i32, ptr [[SRC]], align 4
; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i64 0
; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[TMP1]], i64 1
; CHECK-NEXT:    [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
; CHECK-NEXT:    [[TMP5:%.*]] = ashr <4 x i32> [[TMP4]], <i32 8, i32 8, i32 0, i32 0>
; CHECK-NEXT:    [[TMP6:%.*]] = trunc <4 x i32> [[TMP5]] to <4 x i16>
; CHECK-NEXT:    store <4 x i16> [[TMP6]], ptr [[DST]], align 2
; CHECK-NEXT:    ret void
;
entry:
  %0 = load i32, ptr %src, align 4
  %1 = load i32, ptr %src, align 4
  %ashr0 = ashr i32 %0, 8
  %ashr1 = ashr i32 %1, 8
  %add = add i32 %0, 0
  %or = or i32 %1, 0
  %trunc0 = trunc i32 %ashr0 to i16
  %trunc1 = trunc i32 %ashr1 to i16
  %trunc2 = trunc i32 %add to i16
  %trunc3 = trunc i32 %or to i16
  store i16 %trunc0, ptr %dst, align 2
  %d1 = getelementptr i16, ptr %dst, i32 1
  store i16 %trunc1, ptr %d1, align 2
  %d2 = getelementptr i16, ptr %dst, i32 2
  store i16 %trunc2, ptr %d2, align 2
  %d3 = getelementptr i16, ptr %dst, i32 3
  store i16 %trunc3, ptr %d3, align 2
  ret void
}