[RISCV] Andes: model fast unaligned accesses for the 45-series (#221166) The 45-series cores support unaligned scalar accesses. Add FeatureUnalignedScalarMem to each 45-series processor (andes-n45, andes-nx45, andes-a45, andes-ax45 and andes-ax45mpv), so that it is selected by -mcpu rather than -mtune. Other processors declare it this way too. The feature is somewhat architectural: -mtune is only supposed to affect performance, but reaching it through tune features lets -mtune introduce unaligned accesses that crash on a CPU which does not support them. Cover this in memcpy.ll using -mcpu=andes-a45/-mcpu=andes-ax45. The new RUN lines pass -mtune=rocket so that the 45-series scheduling model does not reorder the output, letting them reuse the existing check lines. Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
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