llvm/test/Transforms/SLPVectorizer/AMDGPU/complex-mul-fma.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -S -mtriple=amdgpu9.42-amd-amdhsa -passes=slp-vectorizer < %s | FileCheck %s

; Print the IR instead of an SLP remark: the remark is emitted only when the tree is vectorized.
; The second fmul of each fsub/fadd does not fuse. Packing them needs a
; cross-half move the scalar form avoids, so the tree stays scalar.
define void @cmul_store(ptr addrspace(1) %out, float %xr, float %xi, float %wr, float %wi) {
; CHECK-LABEL: define void @cmul_store(
; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], float [[XR:%.*]], float [[XI:%.*]], float [[WR:%.*]], float [[WI:%.*]]) {
; CHECK-NEXT:    [[XR_WR:%.*]] = fmul contract float [[XR]], [[WR]]
; CHECK-NEXT:    [[XI_WI:%.*]] = fmul contract float [[XI]], [[WI]]
; CHECK-NEXT:    [[RE:%.*]] = fsub contract float [[XR_WR]], [[XI_WI]]
; CHECK-NEXT:    [[XI_WR:%.*]] = fmul contract float [[XI]], [[WR]]
; CHECK-NEXT:    [[XR_WI:%.*]] = fmul contract float [[XR]], [[WI]]
; CHECK-NEXT:    [[IM:%.*]] = fadd contract float [[XI_WR]], [[XR_WI]]
; CHECK-NEXT:    store float [[RE]], ptr addrspace(1) [[OUT]], align 8
; CHECK-NEXT:    [[OUT_IM:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[OUT]], i64 1
; CHECK-NEXT:    store float [[IM]], ptr addrspace(1) [[OUT_IM]], align 4
; CHECK-NEXT:    ret void
;
  %xr.wr = fmul contract float %xr, %wr
  %xi.wi = fmul contract float %xi, %wi
  %re = fsub contract float %xr.wr, %xi.wi
  %xi.wr = fmul contract float %xi, %wr
  %xr.wi = fmul contract float %xr, %wi
  %im = fadd contract float %xi.wr, %xr.wi
  store float %re, ptr addrspace(1) %out, align 8
  %out.im = getelementptr inbounds float, ptr addrspace(1) %out, i64 1
  store float %im, ptr addrspace(1) %out.im, align 4
  ret void
}