llvm/test/Transforms/SLPVectorizer/AArch64/select-zext-analysis.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -S --passes=slp-vectorizer -mtriple=aarch64-w64-windows-gnu < %s | FileCheck %s

define void @test(ptr %d, i32 %0, i1 %cmp) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: ptr [[D:%.*]], i32 [[TMP0:%.*]], i1 [[CMP:%.*]]) {
; CHECK-NEXT:  [[ENTRY:.*]]:
; CHECK-NEXT:    [[CONV:%.*]] = zext i1 [[CMP]] to i32
; CHECK-NEXT:    [[SUB:%.*]] = select i1 [[CMP]], i32 0, i32 2
; CHECK-NEXT:    br i1 [[CMP]], label %[[IF_ELSE:.*]], label %[[IF_END:.*]]
; CHECK:       [[IF_ELSE]]:
; CHECK-NEXT:    [[ADD3:%.*]] = add i32 [[TMP0]], [[CONV]]
; CHECK-NEXT:    [[SUB1:%.*]] = or i32 [[SUB]], 1
; CHECK-NEXT:    br label %[[IF_END]]
; CHECK:       [[IF_END]]:
; CHECK-NEXT:    [[A_0:%.*]] = phi i32 [ [[SUB]], %[[ENTRY]] ], [ [[SUB1]], %[[IF_ELSE]] ]
; CHECK-NEXT:    [[B_0:%.*]] = phi i32 [ [[CONV]], %[[ENTRY]] ], [ [[ADD3]], %[[IF_ELSE]] ]
; CHECK-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[D]], align 8
; CHECK-NEXT:    store i32 [[A_0]], ptr [[TMP1]], align 4
; CHECK-NEXT:    [[B4:%.*]] = getelementptr i8, ptr [[TMP1]], i64 4
; CHECK-NEXT:    store i32 [[B_0]], ptr [[B4]], align 4
; CHECK-NEXT:    ret void
;
entry:
  %conv = zext i1 %cmp to i32
  %sub = select i1 %cmp, i32 0, i32 2
  br i1 %cmp, label %if.else, label %if.end

if.else:
  %add3 = add i32 %0, %conv
  %sub1 = or i32 %sub, 1
  br label %if.end

if.end:
  %a.0 = phi i32 [ %sub, %entry ], [ %sub1, %if.else ]
  %b.0 = phi i32 [ %conv, %entry ], [ %add3, %if.else ]
  %1 = load ptr, ptr %d, align 8
  store i32 %a.0, ptr %1, align 4
  %b4 = getelementptr i8, ptr %1, i64 4
  store i32 %b.0, ptr %b4, align 4
  ret void
}