llvm/test/Transforms/SLPVectorizer/AArch64/icmp-wrong-bitwidth.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -passes=slp-vectorizer -S -mtriple=aarch64 < %s | FileCheck %s

define void @test(ptr %dst) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: ptr [[DST:%.*]]) {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[P0:%.*]] = getelementptr i8, ptr [[DST]], i64 0
; CHECK-NEXT:    store <4 x i8> splat (i8 1), ptr [[P0]], align 1
; CHECK-NEXT:    ret void
;
entry:
  %s0 = sext i16 126 to i32
  %s1 = sext i16 126 to i32
  %s2 = sext i16 126 to i32
  %s3 = sext i16 126 to i32
  %c0 = icmp sgt i32 214, %s0
  %c1 = icmp sgt i32 214, %s1
  %c2 = icmp sgt i32 214, %s2
  %c3 = icmp sgt i32 214, %s3
  %z0 = zext i1 %c0 to i8
  %z1 = zext i1 %c1 to i8
  %z2 = zext i1 %c2 to i8
  %z3 = zext i1 %c3 to i8
  %p0 = getelementptr i8, ptr %dst, i64 0
  %p1 = getelementptr i8, ptr %dst, i64 1
  %p2 = getelementptr i8, ptr %dst, i64 2
  %p3 = getelementptr i8, ptr %dst, i64 3
  store i8 %z0, ptr %p0
  store i8 %z1, ptr %p1
  store i8 %z2, ptr %p2
  store i8 %z3, ptr %p3
  ret void
}