llvm/test/Transforms/PhaseOrdering/constraint-elimination-materialize-flags.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
; RUN: opt -passes='default<O3>' -S %s | FileCheck %s

define void @index_mask_removed(ptr %A, i16 %start, i16 %v, i16 %n) {
; CHECK-LABEL: define void @index_mask_removed(
; CHECK-SAME: ptr nofree writeonly captures(none) [[A:%.*]], i16 [[START:%.*]], i16 [[V:%.*]], i16 [[N:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[PRE:%.*]] = icmp slt i16 [[START]], [[V]]
; CHECK-NEXT:    [[EC_NOT1:%.*]] = icmp eq i16 [[START]], [[N]]
; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[PRE]], i1 true, i1 [[EC_NOT1]]
; CHECK-NEXT:    br i1 [[OR_COND]], label %[[EXIT:.*]], label %[[LOOP_BODY_PREHEADER:.*]]
; CHECK:       [[LOOP_BODY_PREHEADER]]:
; CHECK-NEXT:    [[TMP0:%.*]] = xor i16 [[START]], -1
; CHECK-NEXT:    [[TMP1:%.*]] = add i16 [[N]], [[TMP0]]
; CHECK-NEXT:    [[TMP2:%.*]] = zext i16 [[TMP1]] to i32
; CHECK-NEXT:    [[TMP3:%.*]] = add nuw nsw i32 [[TMP2]], 1
; CHECK-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i16 [[TMP1]], 11
; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[LOOP_BODY_PREHEADER3:.*]], label %[[VECTOR_SCEVCHECK:.*]]
; CHECK:       [[VECTOR_SCEVCHECK]]:
; CHECK-NEXT:    [[TMP4:%.*]] = xor i16 [[START]], -1
; CHECK-NEXT:    [[TMP5:%.*]] = add i16 [[N]], [[TMP4]]
; CHECK-NEXT:    [[TMP6:%.*]] = sext i16 [[V]] to i32
; CHECK-NEXT:    [[TMP7:%.*]] = zext i16 [[TMP5]] to i32
; CHECK-NEXT:    [[TMP8:%.*]] = xor i16 [[START]], -1
; CHECK-NEXT:    [[TMP9:%.*]] = sext i16 [[TMP8]] to i32
; CHECK-NEXT:    [[TMP10:%.*]] = add nsw i32 [[TMP9]], [[TMP6]]
; CHECK-NEXT:    [[TMP11:%.*]] = icmp ult i32 [[TMP10]], [[TMP7]]
; CHECK-NEXT:    br i1 [[TMP11]], label %[[LOOP_BODY_PREHEADER3]], label %[[VECTOR_PH:.*]]
; CHECK:       [[VECTOR_PH]]:
; CHECK-NEXT:    [[N_VEC:%.*]] = and i32 [[TMP3]], 131068
; CHECK-NEXT:    [[TMP12:%.*]] = trunc i32 [[N_VEC]] to i16
; CHECK-NEXT:    [[TMP13:%.*]] = add i16 [[START]], [[TMP12]]
; CHECK-NEXT:    [[INVARIANT_OP:%.*]] = sub i16 [[START]], [[V]]
; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]
; CHECK:       [[VECTOR_BODY]]:
; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT:    [[TMP14:%.*]] = trunc i32 [[INDEX]] to i16
; CHECK-NEXT:    [[DOTREASS:%.*]] = add i16 [[TMP14]], [[INVARIANT_OP]]
; CHECK-NEXT:    [[TMP15:%.*]] = sext i16 [[DOTREASS]] to i64
; CHECK-NEXT:    [[TMP16:%.*]] = and i64 [[TMP15]], 4294967295
; CHECK-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw i8, ptr [[A]], i64 [[TMP16]]
; CHECK-NEXT:    store <4 x i8> splat (i8 1), ptr [[TMP17]], align 1
; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
; CHECK-NEXT:    [[TMP18:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-NEXT:    br i1 [[TMP18]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK:       [[MIDDLE_BLOCK]]:
; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i32 [[TMP3]], [[N_VEC]]
; CHECK-NEXT:    br i1 [[CMP_N]], label %[[EXIT]], label %[[LOOP_BODY_PREHEADER3]]
; CHECK:       [[LOOP_BODY_PREHEADER3]]:
; CHECK-NEXT:    [[IV2_PH:%.*]] = phi i16 [ [[START]], %[[VECTOR_SCEVCHECK]] ], [ [[START]], %[[LOOP_BODY_PREHEADER]] ], [ [[TMP13]], %[[MIDDLE_BLOCK]] ]
; CHECK-NEXT:    br label %[[LOOP_BODY:.*]]
; CHECK:       [[LOOP_BODY]]:
; CHECK-NEXT:    [[IV2:%.*]] = phi i16 [ [[IV_NEXT:%.*]], %[[LOOP_BODY]] ], [ [[IV2_PH]], %[[LOOP_BODY_PREHEADER3]] ]
; CHECK-NEXT:    [[OFF:%.*]] = sub nsw i16 [[IV2]], [[V]]
; CHECK-NEXT:    [[EXT:%.*]] = sext i16 [[OFF]] to i64
; CHECK-NEXT:    [[MASK:%.*]] = and i64 [[EXT]], 4294967295
; CHECK-NEXT:    [[GEP:%.*]] = getelementptr inbounds nuw i8, ptr [[A]], i64 [[MASK]]
; CHECK-NEXT:    store i8 1, ptr [[GEP]], align 1
; CHECK-NEXT:    [[IV_NEXT]] = add nsw i16 [[IV2]], 1
; CHECK-NEXT:    [[EC_NOT:%.*]] = icmp eq i16 [[IV_NEXT]], [[N]]
; CHECK-NEXT:    br i1 [[EC_NOT]], label %[[EXIT]], label %[[LOOP_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK:       [[EXIT]]:
; CHECK-NEXT:    ret void
;
entry:
  %pre = icmp slt i16 %start, %v
  br i1 %pre, label %exit, label %loop.header

loop.header:
  %iv = phi i16 [ %start, %entry ], [ %iv.next, %loop.latch ]
  %ec = icmp ne i16 %iv, %n
  br i1 %ec, label %loop.body, label %exit

loop.body:
  %off = sub nsw i16 %iv, %v
  %ext = sext i16 %off to i64
  %mask = and i64 %ext, 4294967295
  %gep = getelementptr inbounds i8, ptr %A, i64 %mask
  store i8 1, ptr %gep, align 1
  br label %loop.latch

loop.latch:
  %iv.next = add nsw i16 %iv, 1
  br label %loop.header

exit:
  ret void
}

define void @index_not_widened(ptr %A, i32 %start, i32 %v, i32 %n) {
; CHECK-LABEL: define void @index_not_widened(
; CHECK-SAME: ptr nofree writeonly captures(none) [[A:%.*]], i32 [[START:%.*]], i32 [[V:%.*]], i32 [[N:%.*]]) local_unnamed_addr #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*]]:
; CHECK-NEXT:    [[PRE:%.*]] = icmp slt i32 [[START]], [[V]]
; CHECK-NEXT:    [[EC_NOT1:%.*]] = icmp eq i32 [[START]], [[N]]
; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[PRE]], i1 true, i1 [[EC_NOT1]]
; CHECK-NEXT:    br i1 [[OR_COND]], label %[[EXIT:.*]], label %[[LOOP_BODY:.*]]
; CHECK:       [[LOOP_BODY]]:
; CHECK-NEXT:    [[IV2:%.*]] = phi i32 [ [[IV_NEXT:%.*]], %[[LOOP_BODY]] ], [ [[START]], %[[ENTRY]] ]
; CHECK-NEXT:    [[OFF:%.*]] = sub nsw i32 [[IV2]], [[V]]
; CHECK-NEXT:    [[EXT:%.*]] = sext i32 [[OFF]] to i64
; CHECK-NEXT:    [[GEP:%.*]] = getelementptr inbounds [4 x i8], ptr [[A]], i64 [[EXT]]
; CHECK-NEXT:    store i32 [[IV2]], ptr [[GEP]], align 4
; CHECK-NEXT:    [[IV_NEXT]] = add nsw i32 [[IV2]], 1
; CHECK-NEXT:    [[EC_NOT:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
; CHECK-NEXT:    br i1 [[EC_NOT]], label %[[EXIT]], label %[[LOOP_BODY]]
; CHECK:       [[EXIT]]:
; CHECK-NEXT:    ret void
;
entry:
  %pre = icmp slt i32 %start, %v
  br i1 %pre, label %exit, label %loop.header

loop.header:
  %iv = phi i32 [ %start, %entry ], [ %iv.next, %loop.latch ]
  %ec = icmp ne i32 %iv, %n
  br i1 %ec, label %loop.body, label %exit

loop.body:
  %off = sub nsw i32 %iv, %v
  %ext = sext i32 %off to i64
  %gep = getelementptr inbounds [4 x i8], ptr %A, i64 %ext
  store i32 %iv, ptr %gep, align 4
  br label %loop.latch

loop.latch:
  %iv.next = add nsw i32 %iv, 1
  br label %loop.header

exit:
  ret void
}

define void @iterator_distance_index(ptr %out, ptr %arr, i1 %skip) {
; CHECK-LABEL: define void @iterator_distance_index(
; CHECK-SAME: ptr nofree writeonly captures(none) [[OUT:%.*]], ptr [[ARR:%.*]], i1 [[SKIP:%.*]]) local_unnamed_addr #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*]]:
; CHECK-NEXT:    br i1 [[SKIP]], label %[[EARLY_EXIT:.*]], label %[[INNER_PREHEADER:.*]]
; CHECK:       [[INNER_PREHEADER]]:
; CHECK-NEXT:    [[I2:%.*]] = phi i32 [ [[I_NEXT:%.*]], %[[OUTER_LATCH:.*]] ], [ 0, %[[ENTRY]] ]
; CHECK-NEXT:    br label %[[INNER_BODY_PREHEADER:.*]]
; CHECK:       [[INNER_BODY_PREHEADER]]:
; CHECK-NEXT:    [[J1:%.*]] = phi i32 [ 0, %[[INNER_PREHEADER]] ], [ [[J_NEXT:%.*]], %[[INNER_EXIT:.*]] ]
; CHECK-NEXT:    [[K_LT_J_PEEL_NOT:%.*]] = icmp eq i32 [[J1]], 0
; CHECK-NEXT:    br i1 [[K_LT_J_PEEL_NOT]], label %[[INNER_EXIT]], label %[[INNER_BODY_PEEL_NEXT:.*]]
; CHECK:       [[INNER_BODY_PEEL_NEXT]]:
; CHECK-NEXT:    [[K_LT_J_NOT:%.*]] = icmp eq i32 [[J1]], 1
; CHECK-NEXT:    br label %[[INNER_BODY:.*]]
; CHECK:       [[INNER_BODY]]:
; CHECK-NEXT:    br i1 [[K_LT_J_NOT]], label %[[INNER_EXIT]], label %[[INNER_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
; CHECK:       [[INNER_EXIT]]:
; CHECK-NEXT:    [[SUB:%.*]] = sub nuw nsw i32 [[I2]], [[J1]]
; CHECK-NEXT:    [[IDX:%.*]] = zext nneg i32 [[SUB]] to i64
; CHECK-NEXT:    [[GEP:%.*]] = getelementptr [4 x i8], ptr [[ARR]], i64 [[IDX]]
; CHECK-NEXT:    store ptr [[GEP]], ptr [[OUT]], align 8
; CHECK-NEXT:    store i32 0, ptr [[OUT]], align 8
; CHECK-NEXT:    [[J_NEXT]] = add nuw nsw i32 [[J1]], 1
; CHECK-NEXT:    [[J_GT_I_NOT:%.*]] = icmp samesign ult i32 [[J1]], [[I2]]
; CHECK-NEXT:    br i1 [[J_GT_I_NOT]], label %[[INNER_BODY_PREHEADER]], label %[[OUTER_LATCH]]
; CHECK:       [[OUTER_LATCH]]:
; CHECK-NEXT:    [[I_NEXT]] = add nuw nsw i32 [[I2]], 1
; CHECK-NEXT:    br label %[[INNER_PREHEADER]]
; CHECK:       [[EARLY_EXIT]]:
; CHECK-NEXT:    ret void
;
entry:
  br label %outer

outer:
  %i = phi i32 [ 0, %entry ], [ %i.next, %outer.latch ]
  br i1 %skip, label %early.exit, label %inner

inner:
  %j = phi i32 [ %j.next, %inner.exit ], [ 0, %outer ]
  %j.gt.i = icmp ugt i32 %j, %i
  br i1 %j.gt.i, label %outer.latch, label %inner.body

inner.body:
  %k = phi i32 [ 0, %inner ], [ 1, %inner.body ]
  %k.lt.j = icmp ult i32 %k, %j
  br i1 %k.lt.j, label %inner.body, label %inner.exit

inner.exit:
  %sub = sub i32 %i, %j
  %idx = zext i32 %sub to i64
  %gep = getelementptr [4 x i8], ptr %arr, i64 %idx
  store ptr %gep, ptr %out, align 8
  store i32 0, ptr %out, align 4
  %j.next = add i32 %j, 1
  br label %inner

outer.latch:
  %i.next = add i32 %i, 1
  br label %outer

early.exit:
  ret void
}