llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-tail-folding-interleave-only.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
; RUN: opt -S -passes=loop-vectorize -force-tail-folding-style=data-and-control -tail-folding-policy=must-fold-tail \
; RUN:   -force-vector-width=1 -force-vector-interleave=4 %s | FileCheck %s

define void @scalar_vf_single_iteration(ptr noalias %dst, ptr noalias %src) {
; CHECK-LABEL: define void @scalar_vf_single_iteration(
; CHECK-SAME: ptr noalias [[DST:%.*]], ptr noalias [[SRC:%.*]]) {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    br label %[[VECTOR_PH:.*]]
; CHECK:       [[VECTOR_PH]]:
; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]
; CHECK:       [[VECTOR_BODY]]:
; CHECK-NEXT:    br label %[[PRED_STORE_CONTINUE:.*]]
; CHECK:       [[PRED_STORE_CONTINUE]]:
; CHECK-NEXT:    [[TMP6:%.*]] = load i64, ptr [[SRC]], align 8
; CHECK-NEXT:    [[TMP8:%.*]] = mul i64 [[TMP6]], 3
; CHECK-NEXT:    store i64 [[TMP8]], ptr [[DST]], align 8
; CHECK-NEXT:    br label %[[PRED_STORE_CONTINUE5:.*]]
; CHECK:       [[PRED_STORE_CONTINUE5]]:
; CHECK-NEXT:    br label %[[PRED_STORE_IF6:.*]]
; CHECK:       [[PRED_STORE_IF6]]:
; CHECK-NEXT:    [[TMP10:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 1
; CHECK-NEXT:    [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8
; CHECK-NEXT:    [[TMP12:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 1
; CHECK-NEXT:    [[TMP13:%.*]] = mul i64 [[TMP11]], 3
; CHECK-NEXT:    store i64 [[TMP13]], ptr [[TMP12]], align 8
; CHECK-NEXT:    br label %[[PRED_STORE_CONTINUE7:.*]]
; CHECK:       [[PRED_STORE_CONTINUE7]]:
; CHECK-NEXT:    br label %[[PRED_STORE_IF8:.*]]
; CHECK:       [[PRED_STORE_IF8]]:
; CHECK-NEXT:    [[TMP15:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 2
; CHECK-NEXT:    [[TMP16:%.*]] = load i64, ptr [[TMP15]], align 8
; CHECK-NEXT:    [[TMP17:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 2
; CHECK-NEXT:    [[TMP18:%.*]] = mul i64 [[TMP16]], 3
; CHECK-NEXT:    store i64 [[TMP18]], ptr [[TMP17]], align 8
; CHECK-NEXT:    br label %[[PRED_STORE_CONTINUE9:.*]]
; CHECK:       [[PRED_STORE_CONTINUE9]]:
; CHECK-NEXT:    br label %[[EXIT:.*]]
; CHECK:       [[EXIT]]:
; CHECK-NEXT:    br label %[[MIDDLE_BLOCK:.*]]
; CHECK:       [[MIDDLE_BLOCK]]:
; CHECK-NEXT:    br label %[[EXIT1:.*]]
; CHECK:       [[EXIT1]]:
; CHECK-NEXT:    ret void
;
entry:
  br label %loop

loop:
  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
  %p = getelementptr inbounds i64, ptr %src, i64 %iv
  %l = load i64, ptr %p, align 8
  %m = mul i64 %l, 3
  %q = getelementptr inbounds i64, ptr %dst, i64 %iv
  store i64 %m, ptr %q, align 8
  %iv.next = add nuw nsw i64 %iv, 1
  %ec = icmp eq i64 %iv.next, 3
  br i1 %ec, label %exit, label %loop

exit:
  ret void
}