llvm/test/Transforms/LoopVectorize/outer-loop-scev-predicates.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --filter-out-after "^vector.body:" --version 6
; RUN: opt -passes=loop-vectorize -enable-vplan-native-path -S %s | FileCheck %s

define void @outer_loop_needs_scev_predicate(ptr %dst, i32 %n) {
; CHECK-LABEL: define void @outer_loop_needs_scev_predicate(
; CHECK-SAME: ptr [[DST:%.*]], i32 [[N:%.*]]) {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[TMP0:%.*]] = call i32 @llvm.umax.i32(i32 [[N]], i32 1)
; CHECK-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP0]], 4
; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK]], [[SCALAR_PH:label %.*]], label %[[VECTOR_SCEVCHECK:.*]]
; CHECK:       [[VECTOR_SCEVCHECK]]:
; CHECK-NEXT:    [[TMP3:%.*]] = call i32 @llvm.usub.sat.i32(i32 [[N]], i32 1)
; CHECK-NEXT:    [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
; CHECK-NEXT:    [[TMP5:%.*]] = add i16 1, [[TMP4]]
; CHECK-NEXT:    [[TMP6:%.*]] = icmp ult i16 [[TMP5]], 1
; CHECK-NEXT:    [[TMP7:%.*]] = icmp ugt i32 [[TMP3]], 65535
; CHECK-NEXT:    [[TMP8:%.*]] = or i1 [[TMP6]], [[TMP7]]
; CHECK-NEXT:    br i1 [[TMP8]], [[SCALAR_PH]], label %[[VECTOR_PH:.*]]
; CHECK:       [[VECTOR_PH]]:
; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[TMP0]], 3
; CHECK-NEXT:    [[N_VEC:%.*]] = sub i32 [[TMP0]], [[TMP1]]
; CHECK-NEXT:    [[TMP2:%.*]] = trunc i32 [[N_VEC]] to i16
; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]
; CHECK:       [[VECTOR_BODY]]:
;
entry:
  br label %outer.header

outer.header:
  %outer.iv = phi i16 [ 0, %entry ], [ %outer.iv.next, %outer.latch ]
  %outer.iv.ext = zext i16 %outer.iv to i64
  %gep = getelementptr inbounds i32, ptr %dst, i64 %outer.iv.ext
  br label %inner

inner:
  %iv = phi i64 [ 0, %outer.header ], [ %iv.next, %inner ]
  store i32 0, ptr %gep, align 4
  %iv.next = add nuw nsw i64 %iv, 1
  %inner.ec = icmp eq i64 %iv.next, 8
  br i1 %inner.ec, label %outer.latch, label %inner

outer.latch:
  %outer.iv.next = add i16 %outer.iv, 1
  %outer.iv.next.ext = zext i16 %outer.iv.next to i32
  %outer.ec = icmp ult i32 %outer.iv.next.ext, %n
  br i1 %outer.ec, label %outer.header, label %exit, !llvm.loop !0

exit:
  ret void
}

define void @outer_loop_scev_predicate_known_false(ptr %dst) {
; CHECK-LABEL: define void @outer_loop_scev_predicate_known_false(
; CHECK-SAME: ptr [[DST:%.*]]) {
; CHECK-NEXT:  [[ENTRY:.*]]:
; CHECK-NEXT:    br label %[[OUTER_HEADER:.*]]
; CHECK:       [[OUTER_HEADER]]:
; CHECK-NEXT:    [[OUTER_IV:%.*]] = phi i16 [ 0, %[[ENTRY]] ], [ [[OUTER_IV_NEXT:%.*]], %[[OUTER_LATCH:.*]] ]
; CHECK-NEXT:    [[OUTER_IV_EXT:%.*]] = zext i16 [[OUTER_IV]] to i64
; CHECK-NEXT:    [[GEP:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[OUTER_IV_EXT]]
; CHECK-NEXT:    br label %[[INNER:.*]]
; CHECK:       [[INNER]]:
; CHECK-NEXT:    [[IV:%.*]] = phi i64 [ 0, %[[OUTER_HEADER]] ], [ [[IV_NEXT:%.*]], %[[INNER]] ]
; CHECK-NEXT:    store i32 0, ptr [[GEP]], align 4
; CHECK-NEXT:    [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT:    [[INNER_EC:%.*]] = icmp eq i64 [[IV_NEXT]], 8
; CHECK-NEXT:    br i1 [[INNER_EC]], label %[[OUTER_LATCH]], label %[[INNER]]
; CHECK:       [[OUTER_LATCH]]:
; CHECK-NEXT:    [[OUTER_IV_NEXT]] = add i16 [[OUTER_IV]], 1
; CHECK-NEXT:    [[OUTER_IV_NEXT_EXT:%.*]] = zext i16 [[OUTER_IV_NEXT]] to i32
; CHECK-NEXT:    [[OUTER_EC:%.*]] = icmp ult i32 [[OUTER_IV_NEXT_EXT]], 70000
; CHECK-NEXT:    br i1 [[OUTER_EC]], label %[[OUTER_HEADER]], label %[[EXIT:.*]], !llvm.loop [[LOOP4:![0-9]+]]
; CHECK:       [[EXIT]]:
; CHECK-NEXT:    ret void
;
entry:
  br label %outer.header

outer.header:
  %outer.iv = phi i16 [ 0, %entry ], [ %outer.iv.next, %outer.latch ]
  %outer.iv.ext = zext i16 %outer.iv to i64
  %gep = getelementptr inbounds i32, ptr %dst, i64 %outer.iv.ext
  br label %inner

inner:
  %iv = phi i64 [ 0, %outer.header ], [ %iv.next, %inner ]
  store i32 0, ptr %gep, align 4
  %iv.next = add nuw nsw i64 %iv, 1
  %inner.ec = icmp eq i64 %iv.next, 8
  br i1 %inner.ec, label %outer.latch, label %inner

outer.latch:
  %outer.iv.next = add i16 %outer.iv, 1
  %outer.iv.next.ext = zext i16 %outer.iv.next to i32
  %outer.ec = icmp ult i32 %outer.iv.next.ext, 70000
  br i1 %outer.ec, label %outer.header, label %exit, !llvm.loop !0

exit:
  ret void
}

!0 = distinct !{!0, !1, !2}
!1 = !{!"llvm.loop.vectorize.enable"}
!2 = !{!"llvm.loop.vectorize.width", i32 4}