llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll

; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --filter-out-after "Successor" --version 6
; RUN: opt -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 \
; RUN:   -force-target-supports-scalable-vectors \
; RUN:   -disable-output -vplan-print-after="printFinalVPlan$" %s 2>&1 | FileCheck %s

define void @scev_add_expanded(ptr %dst, i64 %n) {
; CHECK-LABEL: VPlan for loop in 'scev_add_expanded'
; CHECK:  VPlan 'Final VPlan for VF={4},UF={1}' {
; CHECK-EMPTY:
; CHECK-NEXT:  ir-bb<loop.preheader>:
; CHECK-NEXT:    EMIT vp<[[VP2:%[0-9]+]]> = add ir<%n>, ir<2>
; CHECK-NEXT:    EMIT vp<%min.iters.check> = icmp ult vp<[[VP2]]>, ir<4>
; CHECK-NEXT:    EMIT branch-on-cond vp<%min.iters.check>
; CHECK-NEXT:  Successor(s): ir-bb<scalar.ph>, vector.ph
;
entry:
  %cmp = icmp ne i64 %n, 0
  br i1 %cmp, label %loop, label %exit

loop:
  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
  %gep = getelementptr i8, ptr %dst, i64 %iv
  store i8 0, ptr %gep
  %iv.next = add nuw i64 %iv, 1
  %cmp.loop = icmp ule i64 %iv, %n
  br i1 %cmp.loop, label %loop, label %exit

exit:
  ret void
}

define void @scev_add_lshr_expanded(ptr %dst, i64 %n) {
; CHECK-LABEL: VPlan for loop in 'scev_add_lshr_expanded'
; CHECK:  VPlan 'Final VPlan for VF={4},UF={1}' {
; CHECK-NEXT:  Live-in ir<%2> = original trip-count
; CHECK-EMPTY:
; CHECK-NEXT:  ir-bb<loop.preheader>:
; CHECK-NEXT:    IR   %0 = add i64 %n, -1
; CHECK-NEXT:    IR   %1 = lshr i64 %0, 1
; CHECK-NEXT:    IR   %2 = add nuw i64 %1, 1
; CHECK-NEXT:    EMIT vp<%min.iters.check> = icmp ult ir<%2>, ir<4>
; CHECK-NEXT:    EMIT branch-on-cond vp<%min.iters.check>
; CHECK-NEXT:  Successor(s): ir-bb<scalar.ph>, vector.ph
;
entry:
  %cmp = icmp ugt i64 %n, 2
  br i1 %cmp, label %loop, label %exit

loop:
  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
  %gep = getelementptr i8, ptr %dst, i64 %iv
  store i8 0, ptr %gep
  %iv.next = add nuw i64 %iv, 2
  %cmp.loop = icmp ult i64 %iv.next, %n
  br i1 %cmp.loop, label %loop, label %exit

exit:
  ret void
}

define void @scev_add_udiv3_expanded(ptr %dst, i64 %n) {
; CHECK-LABEL: VPlan for loop in 'scev_add_udiv3_expanded'
; CHECK:  VPlan 'Final VPlan for VF={4},UF={1}' {
; CHECK-NEXT:  Live-in ir<%2> = original trip-count
; CHECK-EMPTY:
; CHECK-NEXT:  ir-bb<loop.preheader>:
; CHECK-NEXT:    IR   %0 = add i64 %n, -1
; CHECK-NEXT:    IR   %1 = udiv i64 %0, 3
; CHECK-NEXT:    IR   %2 = add nuw nsw i64 %1, 1
; CHECK-NEXT:    EMIT vp<%min.iters.check> = icmp ult ir<%2>, ir<4>
; CHECK-NEXT:    EMIT branch-on-cond vp<%min.iters.check>
; CHECK-NEXT:  Successor(s): ir-bb<scalar.ph>, vector.ph
;
entry:
  %cmp = icmp ugt i64 %n, 3
  br i1 %cmp, label %loop, label %exit

loop:
  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
  %gep = getelementptr i8, ptr %dst, i64 %iv
  store i8 0, ptr %gep
  %iv.next = add nuw i64 %iv, 3
  %cmp.loop = icmp ult i64 %iv.next, %n
  br i1 %cmp.loop, label %loop, label %exit

exit:
  ret void
}

define void @scev_expand_vscale_mul(ptr %dst, i64 %n) {
; CHECK-LABEL: VPlan for loop in 'scev_expand_vscale_mul'
; CHECK:  VPlan 'Final VPlan for VF={vscale x 4},UF={1}' {
; CHECK-NEXT:  Live-in ir<%n> = original trip-count
; CHECK-EMPTY:
; CHECK-NEXT:  ir-bb<loop.preheader>:
; CHECK-NEXT:    EMIT-SCALAR vp<[[VP2:%[0-9]+]]> = vscale i64
; CHECK-NEXT:    EMIT vp<[[VP3:%[0-9]+]]> = shl nuw vp<[[VP2]]>, ir<2>
; CHECK-NEXT:    EMIT vp<%min.iters.check> = icmp ult ir<%n>, vp<[[VP3]]>
; CHECK-NEXT:    EMIT branch-on-cond vp<%min.iters.check>
; CHECK-NEXT:  Successor(s): ir-bb<scalar.ph>, vector.ph
;
entry:
  %cmp = icmp ne i64 %n, 0
  br i1 %cmp, label %loop, label %exit

loop:
  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
  %gep = getelementptr i8, ptr %dst, i64 %iv
  store i8 0, ptr %gep
  %iv.next = add nuw i64 %iv, 1
  %cmp.loop = icmp ult i64 %iv.next, %n
  br i1 %cmp.loop, label %loop, label %exit, !llvm.loop !0

exit:
  ret void
}

define void @scev_expand_udiv(ptr %dst, i64 %n) {
; CHECK-LABEL: VPlan for loop in 'scev_expand_udiv'
; CHECK:  VPlan 'Final VPlan for VF={4},UF={1}' {
; CHECK-EMPTY:
; CHECK-NEXT:  ir-bb<loop.preheader>:
; CHECK-NEXT:    EMIT vp<%min.iters.check> = icmp ult ir<%div>, ir<4>
; CHECK-NEXT:    EMIT branch-on-cond vp<%min.iters.check>
; CHECK-NEXT:  Successor(s): ir-bb<scalar.ph>, vector.ph
;
entry:
  %div = udiv i64 %n, 3
  %cmp = icmp ne i64 %div, 0
  br i1 %cmp, label %loop.preheader, label %exit

loop.preheader:
  br label %loop

loop:
  %iv = phi i64 [ 0, %loop.preheader ], [ %iv.next, %loop ]
  %gep = getelementptr i8, ptr %dst, i64 %iv
  store i8 0, ptr %gep
  %iv.next = add nuw i64 %iv, 1
  %cmp.loop = icmp ult i64 %iv.next, %div
  br i1 %cmp.loop, label %loop, label %exit

exit:
  ret void
}

!0 = distinct !{!0, !1, !2}
!1 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
!2 = !{!"llvm.loop.vectorize.width", i32 4}