llvm/test/Transforms/LoopVectorize/RISCV/versioning-dead-load.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
; RUN: opt -S -passes=loop-vectorize -mtriple=riscv64 -mattr=+v < %s | FileCheck %s

; Test an interleave group with a dead load member (%b), under stride versioning.
define void @f(ptr noalias %p, ptr noalias %q, ptr noalias %dst, i64 %stride) vscale_range(2, 1024) {
; CHECK-LABEL: define void @f(
; CHECK-SAME: ptr noalias [[P:%.*]], ptr noalias [[Q:%.*]], ptr noalias [[DST:%.*]], i64 [[STRIDE:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    br label %[[VECTOR_SCEVCHECK:.*]]
; CHECK:       [[VECTOR_SCEVCHECK]]:
; CHECK-NEXT:    [[IDENT_CHECK:%.*]] = icmp ne i64 [[STRIDE]], 1
; CHECK-NEXT:    br i1 [[IDENT_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK:       [[VECTOR_PH]]:
; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]
; CHECK:       [[VECTOR_BODY]]:
; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT:    [[AVL:%.*]] = phi i64 [ 1024, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT:    [[TMP0:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 2, i1 true)
; CHECK-NEXT:    [[TMP1:%.*]] = mul nuw nsw i64 [[INDEX]], 24
; CHECK-NEXT:    [[TMP2:%.*]] = getelementptr inbounds nuw i8, ptr [[P]], i64 [[TMP1]]
; CHECK-NEXT:    [[INTERLEAVE_EVL:%.*]] = mul nuw nsw i32 [[TMP0]], 3
; CHECK-NEXT:    [[WIDE_VP_LOAD:%.*]] = call <vscale x 6 x i64> @llvm.vp.load.nxv6i64.p0(ptr align 8 [[TMP2]], <vscale x 6 x i1> splat (i1 true), i32 [[INTERLEAVE_EVL]])
; CHECK-NEXT:    [[STRIDED_VEC:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.vector.deinterleave3.nxv6i64(<vscale x 6 x i64> [[WIDE_VP_LOAD]])
; CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[STRIDED_VEC]], 0
; CHECK-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[STRIDED_VEC]], 1
; CHECK-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[STRIDED_VEC]], 2
; CHECK-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [8 x i8], ptr [[Q]], i64 [[INDEX]]
; CHECK-NEXT:    call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> [[TMP3]], ptr align 8 [[TMP6]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP0]])
; CHECK-NEXT:    [[TMP7:%.*]] = add <vscale x 2 x i64> [[TMP3]], [[TMP5]]
; CHECK-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [8 x i8], ptr [[DST]], i64 [[INDEX]]
; CHECK-NEXT:    call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> [[TMP7]], ptr align 8 [[TMP8]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP0]])
; CHECK-NEXT:    [[TMP9:%.*]] = zext i32 [[TMP0]] to i64
; CHECK-NEXT:    [[CURRENT_ITERATION_NEXT]] = add nuw i64 [[TMP9]], [[INDEX]]
; CHECK-NEXT:    [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP9]]
; CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
; CHECK-NEXT:    br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK:       [[MIDDLE_BLOCK]]:
; CHECK-NEXT:    br label %[[EXIT:.*]]
; CHECK:       [[SCALAR_PH]]:
; CHECK-NEXT:    br label %[[LOOP_HEADER:.*]]
; CHECK:       [[LOOP_HEADER]]:
; CHECK-NEXT:    [[IV:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
; CHECK-NEXT:    [[ARRAYIDX_IDX:%.*]] = mul nuw nsw i64 [[IV]], 24
; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds nuw i8, ptr [[P]], i64 [[ARRAYIDX_IDX]]
; CHECK-NEXT:    [[A:%.*]] = load i64, ptr [[ARRAYIDX]], align 8
; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw i8, ptr [[ARRAYIDX]], i64 8
; CHECK-NEXT:    [[B:%.*]] = load i64, ptr [[ARRAYIDX2]], align 8
; CHECK-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds nuw i8, ptr [[ARRAYIDX]], i64 16
; CHECK-NEXT:    [[C:%.*]] = load i64, ptr [[ARRAYIDX3]], align 8
; CHECK-NEXT:    [[MUL3:%.*]] = mul nsw i64 [[IV]], [[STRIDE]]
; CHECK-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds [8 x i8], ptr [[Q]], i64 [[MUL3]]
; CHECK-NEXT:    store i64 [[A]], ptr [[ARRAYIDX4]], align 8
; CHECK-NEXT:    [[CMP5:%.*]] = icmp sgt i64 [[A]], 0
; CHECK-NEXT:    br i1 [[CMP5]], label %[[IF_THEN:.*]], label %[[LOOP_LATCH]]
; CHECK:       [[IF_THEN]]:
; CHECK-NEXT:    [[REM:%.*]] = srem i64 3, [[STRIDE]]
; CHECK-NEXT:    [[TMP11:%.*]] = mul i64 [[B]], [[REM]]
; CHECK-NEXT:    br label %[[LOOP_LATCH]]
; CHECK:       [[LOOP_LATCH]]:
; CHECK-NEXT:    [[T_0:%.*]] = phi i64 [ [[TMP11]], %[[IF_THEN]] ], [ 0, %[[LOOP_HEADER]] ]
; CHECK-NEXT:    [[TMP12:%.*]] = add i64 [[T_0]], [[A]]
; CHECK-NEXT:    [[TMP13:%.*]] = add i64 [[TMP12]], [[C]]
; CHECK-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds nuw [8 x i8], ptr [[DST]], i64 [[IV]]
; CHECK-NEXT:    store i64 [[TMP13]], ptr [[ARRAYIDX10]], align 8
; CHECK-NEXT:    [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
; CHECK-NEXT:    br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK:       [[EXIT]]:
; CHECK-NEXT:    ret void
;
entry:
  br label %loop.header

loop.header:
  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]
  %arrayidx.idx = mul nuw nsw i64 %iv, 24
  %arrayidx = getelementptr inbounds nuw i8, ptr %p, i64 %arrayidx.idx
  %a = load i64, ptr %arrayidx, align 8
  %arrayidx2 = getelementptr inbounds nuw i8, ptr %arrayidx, i64 8
  %b = load i64, ptr %arrayidx2, align 8
  %arrayidx3 = getelementptr inbounds nuw i8, ptr %arrayidx, i64 16
  %c = load i64, ptr %arrayidx3, align 8
  %mul3 = mul nsw i64 %iv, %stride
  %arrayidx4 = getelementptr inbounds [8 x i8], ptr %q, i64 %mul3
  store i64 %a, ptr %arrayidx4, align 8
  %cmp5 = icmp sgt i64 %a, 0
  br i1 %cmp5, label %if.then, label %loop.latch

if.then:
  %rem = srem i64 3, %stride
  %0 = mul i64 %b, %rem
  br label %loop.latch

loop.latch:
  %t.0 = phi i64 [ %0, %if.then ], [ 0, %loop.header ]
  %1 = add i64 %t.0, %a
  %2 = add i64 %1, %c
  %arrayidx10 = getelementptr inbounds nuw [8 x i8], ptr %dst, i64 %iv
  store i64 %2, ptr %arrayidx10, align 8
  %iv.next = add nuw nsw i64 %iv, 1
  %exitcond.not = icmp eq i64 %iv.next, 1024
  br i1 %exitcond.not, label %exit, label %loop.header

exit:
  ret void
}