llvm/test/Transforms/LoopUnroll/AArch64/partial-reductions.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -p loop-unroll -S %s | FileCheck %s
target triple = "aarch64-unknown-linux-gnu"

define i32 @unroll_partial_rdx(ptr nofree noundef readonly captures(none) %a, ptr nofree noundef readonly captures(none) %b) {
; CHECK-LABEL: define i32 @unroll_partial_rdx(
; CHECK-SAME: ptr nofree noundef readonly captures(none) [[A:%.*]], ptr nofree noundef readonly captures(none) [[B:%.*]]) {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    br label %[[LOOP:.*]]
; CHECK:       [[LOOP]]:
; CHECK-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw i8, ptr [[A]], i64 16
; CHECK-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw i8, ptr [[A]], i64 32
; CHECK-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw i8, ptr [[A]], i64 48
; CHECK-NEXT:    [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[A]], align 4
; CHECK-NEXT:    [[WIDE_LOAD20:%.*]] = load <4 x i32>, ptr [[TMP12]], align 4
; CHECK-NEXT:    [[WIDE_LOAD21:%.*]] = load <4 x i32>, ptr [[TMP14]], align 4
; CHECK-NEXT:    [[WIDE_LOAD22:%.*]] = load <4 x i32>, ptr [[TMP15]], align 4
; CHECK-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw i8, ptr [[B]], i64 16
; CHECK-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw i8, ptr [[B]], i64 32
; CHECK-NEXT:    [[TMP18:%.*]] = getelementptr inbounds nuw i8, ptr [[B]], i64 48
; CHECK-NEXT:    [[WIDE_LOAD23:%.*]] = load <4 x i32>, ptr [[B]], align 4
; CHECK-NEXT:    [[WIDE_LOAD24:%.*]] = load <4 x i32>, ptr [[TMP16]], align 4
; CHECK-NEXT:    [[WIDE_LOAD25:%.*]] = load <4 x i32>, ptr [[TMP17]], align 4
; CHECK-NEXT:    [[WIDE_LOAD26:%.*]] = load <4 x i32>, ptr [[TMP18]], align 4
; CHECK-NEXT:    [[TMP19:%.*]] = mul <4 x i32> [[WIDE_LOAD23]], [[WIDE_LOAD1]]
; CHECK-NEXT:    [[TMP20:%.*]] = mul <4 x i32> [[WIDE_LOAD24]], [[WIDE_LOAD20]]
; CHECK-NEXT:    [[TMP21:%.*]] = mul <4 x i32> [[WIDE_LOAD25]], [[WIDE_LOAD21]]
; CHECK-NEXT:    [[TMP94:%.*]] = mul <4 x i32> [[WIDE_LOAD26]], [[WIDE_LOAD22]]
; CHECK-NEXT:    [[VEC_PHI:%.*]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> zeroinitializer, <4 x i32> [[TMP19]])
; CHECK-NEXT:    [[VEC_PHI10:%.*]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> zeroinitializer, <4 x i32> [[TMP20]])
; CHECK-NEXT:    [[VEC_PHI11:%.*]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> zeroinitializer, <4 x i32> [[TMP21]])
; CHECK-NEXT:    [[VEC_PHI12:%.*]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> zeroinitializer, <4 x i32> [[TMP94]])
; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[A]], i64 16
; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 16
; CHECK-NEXT:    [[TMP2:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 32
; CHECK-NEXT:    [[TMP3:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 48
; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4
; CHECK-NEXT:    [[WIDE_LOAD13:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4
; CHECK-NEXT:    [[WIDE_LOAD14:%.*]] = load <4 x i32>, ptr [[TMP2]], align 4
; CHECK-NEXT:    [[WIDE_LOAD15:%.*]] = load <4 x i32>, ptr [[TMP3]], align 4
; CHECK-NEXT:    [[TMP4:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[B]], i64 16
; CHECK-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP4]], i64 16
; CHECK-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP4]], i64 32
; CHECK-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP4]], i64 48
; CHECK-NEXT:    [[WIDE_LOAD16:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4
; CHECK-NEXT:    [[WIDE_LOAD17:%.*]] = load <4 x i32>, ptr [[TMP5]], align 4
; CHECK-NEXT:    [[WIDE_LOAD18:%.*]] = load <4 x i32>, ptr [[TMP6]], align 4
; CHECK-NEXT:    [[WIDE_LOAD19:%.*]] = load <4 x i32>, ptr [[TMP7]], align 4
; CHECK-NEXT:    [[TMP8:%.*]] = mul <4 x i32> [[WIDE_LOAD16]], [[WIDE_LOAD]]
; CHECK-NEXT:    [[TMP9:%.*]] = mul <4 x i32> [[WIDE_LOAD17]], [[WIDE_LOAD13]]
; CHECK-NEXT:    [[TMP10:%.*]] = mul <4 x i32> [[WIDE_LOAD18]], [[WIDE_LOAD14]]
; CHECK-NEXT:    [[TMP11:%.*]] = mul <4 x i32> [[WIDE_LOAD19]], [[WIDE_LOAD15]]
; CHECK-NEXT:    [[PARTIAL_REDUCE:%.*]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> [[VEC_PHI]], <4 x i32> [[TMP8]])
; CHECK-NEXT:    [[PARTIAL_REDUCE20:%.*]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> [[VEC_PHI10]], <4 x i32> [[TMP9]])
; CHECK-NEXT:    [[PARTIAL_REDUCE21:%.*]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> [[VEC_PHI11]], <4 x i32> [[TMP10]])
; CHECK-NEXT:    [[PARTIAL_REDUCE22:%.*]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> [[VEC_PHI12]], <4 x i32> [[TMP11]])
; CHECK-NEXT:    [[TMP22:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[A]], i64 32
; CHECK-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP22]], i64 16
; CHECK-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP22]], i64 32
; CHECK-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP22]], i64 48
; CHECK-NEXT:    [[WIDE_LOAD_2:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4
; CHECK-NEXT:    [[WIDE_LOAD13_2:%.*]] = load <4 x i32>, ptr [[TMP23]], align 4
; CHECK-NEXT:    [[WIDE_LOAD14_2:%.*]] = load <4 x i32>, ptr [[TMP24]], align 4
; CHECK-NEXT:    [[WIDE_LOAD15_2:%.*]] = load <4 x i32>, ptr [[TMP25]], align 4
; CHECK-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[B]], i64 32
; CHECK-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP26]], i64 16
; CHECK-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP26]], i64 32
; CHECK-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP26]], i64 48
; CHECK-NEXT:    [[WIDE_LOAD16_2:%.*]] = load <4 x i32>, ptr [[TMP26]], align 4
; CHECK-NEXT:    [[WIDE_LOAD17_2:%.*]] = load <4 x i32>, ptr [[TMP27]], align 4
; CHECK-NEXT:    [[WIDE_LOAD18_2:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4
; CHECK-NEXT:    [[WIDE_LOAD19_2:%.*]] = load <4 x i32>, ptr [[TMP29]], align 4
; CHECK-NEXT:    [[TMP30:%.*]] = mul <4 x i32> [[WIDE_LOAD16_2]], [[WIDE_LOAD_2]]
; CHECK-NEXT:    [[TMP31:%.*]] = mul <4 x i32> [[WIDE_LOAD17_2]], [[WIDE_LOAD13_2]]
; CHECK-NEXT:    [[TMP32:%.*]] = mul <4 x i32> [[WIDE_LOAD18_2]], [[WIDE_LOAD14_2]]
; CHECK-NEXT:    [[TMP33:%.*]] = mul <4 x i32> [[WIDE_LOAD19_2]], [[WIDE_LOAD15_2]]
; CHECK-NEXT:    [[PARTIAL_REDUCE_2:%.*]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> [[PARTIAL_REDUCE]], <4 x i32> [[TMP30]])
; CHECK-NEXT:    [[PARTIAL_REDUCE20_2:%.*]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> [[PARTIAL_REDUCE20]], <4 x i32> [[TMP31]])
; CHECK-NEXT:    [[PARTIAL_REDUCE21_2:%.*]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> [[PARTIAL_REDUCE21]], <4 x i32> [[TMP32]])
; CHECK-NEXT:    [[PARTIAL_REDUCE22_2:%.*]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> [[PARTIAL_REDUCE22]], <4 x i32> [[TMP33]])
; CHECK-NEXT:    [[TMP34:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[A]], i64 48
; CHECK-NEXT:    [[TMP35:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP34]], i64 16
; CHECK-NEXT:    [[TMP36:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP34]], i64 32
; CHECK-NEXT:    [[TMP37:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP34]], i64 48
; CHECK-NEXT:    [[WIDE_LOAD_3:%.*]] = load <4 x i32>, ptr [[TMP34]], align 4
; CHECK-NEXT:    [[WIDE_LOAD13_3:%.*]] = load <4 x i32>, ptr [[TMP35]], align 4
; CHECK-NEXT:    [[WIDE_LOAD14_3:%.*]] = load <4 x i32>, ptr [[TMP36]], align 4
; CHECK-NEXT:    [[WIDE_LOAD15_3:%.*]] = load <4 x i32>, ptr [[TMP37]], align 4
; CHECK-NEXT:    [[TMP38:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[B]], i64 48
; CHECK-NEXT:    [[TMP39:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP38]], i64 16
; CHECK-NEXT:    [[TMP40:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP38]], i64 32
; CHECK-NEXT:    [[TMP41:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP38]], i64 48
; CHECK-NEXT:    [[WIDE_LOAD16_3:%.*]] = load <4 x i32>, ptr [[TMP38]], align 4
; CHECK-NEXT:    [[WIDE_LOAD17_3:%.*]] = load <4 x i32>, ptr [[TMP39]], align 4
; CHECK-NEXT:    [[WIDE_LOAD18_3:%.*]] = load <4 x i32>, ptr [[TMP40]], align 4
; CHECK-NEXT:    [[WIDE_LOAD19_3:%.*]] = load <4 x i32>, ptr [[TMP41]], align 4
; CHECK-NEXT:    [[TMP42:%.*]] = mul <4 x i32> [[WIDE_LOAD16_3]], [[WIDE_LOAD_3]]
; CHECK-NEXT:    [[TMP43:%.*]] = mul <4 x i32> [[WIDE_LOAD17_3]], [[WIDE_LOAD13_3]]
; CHECK-NEXT:    [[TMP44:%.*]] = mul <4 x i32> [[WIDE_LOAD18_3]], [[WIDE_LOAD14_3]]
; CHECK-NEXT:    [[TMP45:%.*]] = mul <4 x i32> [[WIDE_LOAD19_3]], [[WIDE_LOAD15_3]]
; CHECK-NEXT:    [[PARTIAL_REDUCE_3:%.*]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> [[PARTIAL_REDUCE_2]], <4 x i32> [[TMP42]])
; CHECK-NEXT:    [[PARTIAL_REDUCE20_3:%.*]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> [[PARTIAL_REDUCE20_2]], <4 x i32> [[TMP43]])
; CHECK-NEXT:    [[PARTIAL_REDUCE21_3:%.*]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> [[PARTIAL_REDUCE21_2]], <4 x i32> [[TMP44]])
; CHECK-NEXT:    [[PARTIAL_REDUCE22_3:%.*]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> [[PARTIAL_REDUCE22_2]], <4 x i32> [[TMP45]])
; CHECK-NEXT:    [[TMP46:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[A]], i64 64
; CHECK-NEXT:    [[TMP47:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP46]], i64 16
; CHECK-NEXT:    [[TMP48:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP46]], i64 32
; CHECK-NEXT:    [[TMP49:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP46]], i64 48
; CHECK-NEXT:    [[WIDE_LOAD_4:%.*]] = load <4 x i32>, ptr [[TMP46]], align 4
; CHECK-NEXT:    [[WIDE_LOAD13_4:%.*]] = load <4 x i32>, ptr [[TMP47]], align 4
; CHECK-NEXT:    [[WIDE_LOAD14_4:%.*]] = load <4 x i32>, ptr [[TMP48]], align 4
; CHECK-NEXT:    [[WIDE_LOAD15_4:%.*]] = load <4 x i32>, ptr [[TMP49]], align 4
; CHECK-NEXT:    [[TMP50:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[B]], i64 64
; CHECK-NEXT:    [[TMP51:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP50]], i64 16
; CHECK-NEXT:    [[TMP52:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP50]], i64 32
; CHECK-NEXT:    [[TMP53:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP50]], i64 48
; CHECK-NEXT:    [[WIDE_LOAD16_4:%.*]] = load <4 x i32>, ptr [[TMP50]], align 4
; CHECK-NEXT:    [[WIDE_LOAD17_4:%.*]] = load <4 x i32>, ptr [[TMP51]], align 4
; CHECK-NEXT:    [[WIDE_LOAD18_4:%.*]] = load <4 x i32>, ptr [[TMP52]], align 4
; CHECK-NEXT:    [[WIDE_LOAD19_4:%.*]] = load <4 x i32>, ptr [[TMP53]], align 4
; CHECK-NEXT:    [[TMP54:%.*]] = mul <4 x i32> [[WIDE_LOAD16_4]], [[WIDE_LOAD_4]]
; CHECK-NEXT:    [[TMP55:%.*]] = mul <4 x i32> [[WIDE_LOAD17_4]], [[WIDE_LOAD13_4]]
; CHECK-NEXT:    [[TMP56:%.*]] = mul <4 x i32> [[WIDE_LOAD18_4]], [[WIDE_LOAD14_4]]
; CHECK-NEXT:    [[TMP57:%.*]] = mul <4 x i32> [[WIDE_LOAD19_4]], [[WIDE_LOAD15_4]]
; CHECK-NEXT:    [[PARTIAL_REDUCE_4:%.*]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> [[PARTIAL_REDUCE_3]], <4 x i32> [[TMP54]])
; CHECK-NEXT:    [[PARTIAL_REDUCE20_4:%.*]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> [[PARTIAL_REDUCE20_3]], <4 x i32> [[TMP55]])
; CHECK-NEXT:    [[PARTIAL_REDUCE21_4:%.*]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> [[PARTIAL_REDUCE21_3]], <4 x i32> [[TMP56]])
; CHECK-NEXT:    [[PARTIAL_REDUCE22_4:%.*]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> [[PARTIAL_REDUCE22_3]], <4 x i32> [[TMP57]])
; CHECK-NEXT:    [[TMP58:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[A]], i64 80
; CHECK-NEXT:    [[TMP59:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP58]], i64 16
; CHECK-NEXT:    [[TMP60:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP58]], i64 32
; CHECK-NEXT:    [[TMP61:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP58]], i64 48
; CHECK-NEXT:    [[WIDE_LOAD_5:%.*]] = load <4 x i32>, ptr [[TMP58]], align 4
; CHECK-NEXT:    [[WIDE_LOAD13_5:%.*]] = load <4 x i32>, ptr [[TMP59]], align 4
; CHECK-NEXT:    [[WIDE_LOAD14_5:%.*]] = load <4 x i32>, ptr [[TMP60]], align 4
; CHECK-NEXT:    [[WIDE_LOAD15_5:%.*]] = load <4 x i32>, ptr [[TMP61]], align 4
; CHECK-NEXT:    [[TMP62:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[B]], i64 80
; CHECK-NEXT:    [[TMP63:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP62]], i64 16
; CHECK-NEXT:    [[TMP64:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP62]], i64 32
; CHECK-NEXT:    [[TMP65:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP62]], i64 48
; CHECK-NEXT:    [[WIDE_LOAD16_5:%.*]] = load <4 x i32>, ptr [[TMP62]], align 4
; CHECK-NEXT:    [[WIDE_LOAD17_5:%.*]] = load <4 x i32>, ptr [[TMP63]], align 4
; CHECK-NEXT:    [[WIDE_LOAD18_5:%.*]] = load <4 x i32>, ptr [[TMP64]], align 4
; CHECK-NEXT:    [[WIDE_LOAD19_5:%.*]] = load <4 x i32>, ptr [[TMP65]], align 4
; CHECK-NEXT:    [[TMP66:%.*]] = mul <4 x i32> [[WIDE_LOAD16_5]], [[WIDE_LOAD_5]]
; CHECK-NEXT:    [[TMP67:%.*]] = mul <4 x i32> [[WIDE_LOAD17_5]], [[WIDE_LOAD13_5]]
; CHECK-NEXT:    [[TMP68:%.*]] = mul <4 x i32> [[WIDE_LOAD18_5]], [[WIDE_LOAD14_5]]
; CHECK-NEXT:    [[TMP69:%.*]] = mul <4 x i32> [[WIDE_LOAD19_5]], [[WIDE_LOAD15_5]]
; CHECK-NEXT:    [[PARTIAL_REDUCE_5:%.*]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> [[PARTIAL_REDUCE_4]], <4 x i32> [[TMP66]])
; CHECK-NEXT:    [[PARTIAL_REDUCE20_5:%.*]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> [[PARTIAL_REDUCE20_4]], <4 x i32> [[TMP67]])
; CHECK-NEXT:    [[PARTIAL_REDUCE21_5:%.*]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> [[PARTIAL_REDUCE21_4]], <4 x i32> [[TMP68]])
; CHECK-NEXT:    [[PARTIAL_REDUCE22_5:%.*]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> [[PARTIAL_REDUCE22_4]], <4 x i32> [[TMP69]])
; CHECK-NEXT:    [[TMP70:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[A]], i64 96
; CHECK-NEXT:    [[TMP71:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP70]], i64 16
; CHECK-NEXT:    [[TMP72:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP70]], i64 32
; CHECK-NEXT:    [[TMP73:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP70]], i64 48
; CHECK-NEXT:    [[WIDE_LOAD_6:%.*]] = load <4 x i32>, ptr [[TMP70]], align 4
; CHECK-NEXT:    [[WIDE_LOAD13_6:%.*]] = load <4 x i32>, ptr [[TMP71]], align 4
; CHECK-NEXT:    [[WIDE_LOAD14_6:%.*]] = load <4 x i32>, ptr [[TMP72]], align 4
; CHECK-NEXT:    [[WIDE_LOAD15_6:%.*]] = load <4 x i32>, ptr [[TMP73]], align 4
; CHECK-NEXT:    [[TMP74:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[B]], i64 96
; CHECK-NEXT:    [[TMP75:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP74]], i64 16
; CHECK-NEXT:    [[TMP76:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP74]], i64 32
; CHECK-NEXT:    [[TMP77:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP74]], i64 48
; CHECK-NEXT:    [[WIDE_LOAD16_6:%.*]] = load <4 x i32>, ptr [[TMP74]], align 4
; CHECK-NEXT:    [[WIDE_LOAD17_6:%.*]] = load <4 x i32>, ptr [[TMP75]], align 4
; CHECK-NEXT:    [[WIDE_LOAD18_6:%.*]] = load <4 x i32>, ptr [[TMP76]], align 4
; CHECK-NEXT:    [[WIDE_LOAD19_6:%.*]] = load <4 x i32>, ptr [[TMP77]], align 4
; CHECK-NEXT:    [[TMP78:%.*]] = mul <4 x i32> [[WIDE_LOAD16_6]], [[WIDE_LOAD_6]]
; CHECK-NEXT:    [[TMP79:%.*]] = mul <4 x i32> [[WIDE_LOAD17_6]], [[WIDE_LOAD13_6]]
; CHECK-NEXT:    [[TMP80:%.*]] = mul <4 x i32> [[WIDE_LOAD18_6]], [[WIDE_LOAD14_6]]
; CHECK-NEXT:    [[TMP81:%.*]] = mul <4 x i32> [[WIDE_LOAD19_6]], [[WIDE_LOAD15_6]]
; CHECK-NEXT:    [[PARTIAL_REDUCE_6:%.*]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> [[PARTIAL_REDUCE_5]], <4 x i32> [[TMP78]])
; CHECK-NEXT:    [[PARTIAL_REDUCE20_6:%.*]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> [[PARTIAL_REDUCE20_5]], <4 x i32> [[TMP79]])
; CHECK-NEXT:    [[PARTIAL_REDUCE21_6:%.*]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> [[PARTIAL_REDUCE21_5]], <4 x i32> [[TMP80]])
; CHECK-NEXT:    [[PARTIAL_REDUCE22_6:%.*]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> [[PARTIAL_REDUCE22_5]], <4 x i32> [[TMP81]])
; CHECK-NEXT:    [[TMP82:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[A]], i64 112
; CHECK-NEXT:    [[TMP83:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP82]], i64 16
; CHECK-NEXT:    [[TMP84:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP82]], i64 32
; CHECK-NEXT:    [[TMP85:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP82]], i64 48
; CHECK-NEXT:    [[WIDE_LOAD_7:%.*]] = load <4 x i32>, ptr [[TMP82]], align 4
; CHECK-NEXT:    [[WIDE_LOAD13_7:%.*]] = load <4 x i32>, ptr [[TMP83]], align 4
; CHECK-NEXT:    [[WIDE_LOAD14_7:%.*]] = load <4 x i32>, ptr [[TMP84]], align 4
; CHECK-NEXT:    [[WIDE_LOAD15_7:%.*]] = load <4 x i32>, ptr [[TMP85]], align 4
; CHECK-NEXT:    [[TMP86:%.*]] = getelementptr inbounds nuw [4 x i8], ptr [[B]], i64 112
; CHECK-NEXT:    [[TMP87:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP86]], i64 16
; CHECK-NEXT:    [[TMP88:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP86]], i64 32
; CHECK-NEXT:    [[TMP89:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP86]], i64 48
; CHECK-NEXT:    [[WIDE_LOAD16_7:%.*]] = load <4 x i32>, ptr [[TMP86]], align 4
; CHECK-NEXT:    [[WIDE_LOAD17_7:%.*]] = load <4 x i32>, ptr [[TMP87]], align 4
; CHECK-NEXT:    [[WIDE_LOAD18_7:%.*]] = load <4 x i32>, ptr [[TMP88]], align 4
; CHECK-NEXT:    [[WIDE_LOAD19_7:%.*]] = load <4 x i32>, ptr [[TMP89]], align 4
; CHECK-NEXT:    [[TMP90:%.*]] = mul <4 x i32> [[WIDE_LOAD16_7]], [[WIDE_LOAD_7]]
; CHECK-NEXT:    [[TMP91:%.*]] = mul <4 x i32> [[WIDE_LOAD17_7]], [[WIDE_LOAD13_7]]
; CHECK-NEXT:    [[TMP92:%.*]] = mul <4 x i32> [[WIDE_LOAD18_7]], [[WIDE_LOAD14_7]]
; CHECK-NEXT:    [[TMP93:%.*]] = mul <4 x i32> [[WIDE_LOAD19_7]], [[WIDE_LOAD15_7]]
; CHECK-NEXT:    [[PARTIAL_REDUCE_LCSSA:%.*]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> [[PARTIAL_REDUCE_6]], <4 x i32> [[TMP90]])
; CHECK-NEXT:    [[PARTIAL_REDUCE20_LCSSA:%.*]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> [[PARTIAL_REDUCE20_6]], <4 x i32> [[TMP91]])
; CHECK-NEXT:    [[PARTIAL_REDUCE21_LCSSA:%.*]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> [[PARTIAL_REDUCE21_6]], <4 x i32> [[TMP92]])
; CHECK-NEXT:    [[PARTIAL_REDUCE22_LCSSA:%.*]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> [[PARTIAL_REDUCE22_6]], <4 x i32> [[TMP93]])
; CHECK-NEXT:    [[BIN_RDX:%.*]] = add <4 x i32> [[PARTIAL_REDUCE20_LCSSA]], [[PARTIAL_REDUCE_LCSSA]]
; CHECK-NEXT:    [[BIN_RDX23:%.*]] = add <4 x i32> [[PARTIAL_REDUCE21_LCSSA]], [[BIN_RDX]]
; CHECK-NEXT:    [[BIN_RDX24:%.*]] = add <4 x i32> [[PARTIAL_REDUCE22_LCSSA]], [[BIN_RDX23]]
; CHECK-NEXT:    [[TMP13:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX24]])
; CHECK-NEXT:    ret i32 [[TMP13]]
;
entry:
  br label %loop

loop:
  %index = phi i64 [ 0, %entry ], [ %index.next, %loop ]
  %vec.phi = phi <4 x i32> [ zeroinitializer, %entry ], [ %partial.reduce, %loop ]
  %vec.phi10 = phi <4 x i32> [ zeroinitializer, %entry ], [ %partial.reduce20, %loop ]
  %vec.phi11 = phi <4 x i32> [ zeroinitializer, %entry ], [ %partial.reduce21, %loop ]
  %vec.phi12 = phi <4 x i32> [ zeroinitializer, %entry ], [ %partial.reduce22, %loop ]
  %0 = getelementptr inbounds nuw [4 x i8], ptr %a, i64 %index
  %1 = getelementptr inbounds nuw i8, ptr %0, i64 16
  %2 = getelementptr inbounds nuw i8, ptr %0, i64 32
  %3 = getelementptr inbounds nuw i8, ptr %0, i64 48
  %wide.load = load <4 x i32>, ptr %0, align 4
  %wide.load13 = load <4 x i32>, ptr %1, align 4
  %wide.load14 = load <4 x i32>, ptr %2, align 4
  %wide.load15 = load <4 x i32>, ptr %3, align 4
  %4 = getelementptr inbounds nuw [4 x i8], ptr %b, i64 %index
  %5 = getelementptr inbounds nuw i8, ptr %4, i64 16
  %6 = getelementptr inbounds nuw i8, ptr %4, i64 32
  %7 = getelementptr inbounds nuw i8, ptr %4, i64 48
  %wide.load16 = load <4 x i32>, ptr %4, align 4
  %wide.load17 = load <4 x i32>, ptr %5, align 4
  %wide.load18 = load <4 x i32>, ptr %6, align 4
  %wide.load19 = load <4 x i32>, ptr %7, align 4
  %8 = mul <4 x i32> %wide.load16, %wide.load
  %9 = mul <4 x i32> %wide.load17, %wide.load13
  %10 = mul <4 x i32> %wide.load18, %wide.load14
  %11 = mul <4 x i32> %wide.load19, %wide.load15
  %partial.reduce = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> %vec.phi, <4 x i32> %8)
  %partial.reduce20 = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> %vec.phi10, <4 x i32> %9)
  %partial.reduce21 = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> %vec.phi11, <4 x i32> %10)
  %partial.reduce22 = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32(<4 x i32> %vec.phi12, <4 x i32> %11)
  %index.next = add nuw i64 %index, 16
  %12 = icmp eq i64 %index.next, 128
  br i1 %12, label %exit, label %loop

exit:
  %bin.rdx = add <4 x i32> %partial.reduce20, %partial.reduce
  %bin.rdx23 = add <4 x i32> %partial.reduce21, %bin.rdx
  %bin.rdx24 = add <4 x i32> %partial.reduce22, %bin.rdx23
  %13 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %bin.rdx24)
  ret i32 %13
}