llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-icmpzero-mixed-ptr-width.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -passes=loop-reduce -S %s | FileCheck %s
;
; Verify that LSR produces well-typed icmp operands when ICmpZero uses a
; pointer-typed operand from a narrow address space (addrspace(5), 32-bit)
; but the chosen IV is wider (i64, from flat-pointer address uses).

target triple = "amdgpu9.42-amd-amdhsa"

define amdgpu_kernel void @icmpzero_mixed_ptr_width(ptr addrspace(5) %scratch) {
; CHECK-LABEL: define amdgpu_kernel void @icmpzero_mixed_ptr_width(
; CHECK-SAME: ptr addrspace(5) [[SCRATCH:%.*]]) {
; CHECK-NEXT:  [[ENTRY:.*]]:
; CHECK-NEXT:    br label %[[LOOP:.*]]
; CHECK:       [[LOOP]]:
; CHECK-NEXT:    [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], %[[LOOP]] ], [ 0, %[[ENTRY]] ]
; CHECK-NEXT:    [[DST:%.*]] = phi ptr addrspace(5) [ [[SCRATCH]], %[[ENTRY]] ], [ [[DST_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT:    [[SCEVGEP4:%.*]] = getelementptr i8, ptr null, i64 [[LSR_IV]]
; CHECK-NEXT:    [[D0:%.*]] = load double, ptr addrspace(5) [[DST]], align 8
; CHECK-NEXT:    [[S0:%.*]] = load double, ptr [[SCEVGEP4]], align 8
; CHECK-NEXT:    [[DST_1:%.*]] = getelementptr i8, ptr addrspace(5) [[DST]], i32 8
; CHECK-NEXT:    [[D1:%.*]] = load double, ptr addrspace(5) [[DST_1]], align 8
; CHECK-NEXT:    [[SCEVGEP2:%.*]] = getelementptr i8, ptr null, i64 [[LSR_IV]]
; CHECK-NEXT:    [[SCEVGEP3:%.*]] = getelementptr i8, ptr [[SCEVGEP2]], i64 8
; CHECK-NEXT:    [[S1:%.*]] = load double, ptr [[SCEVGEP3]], align 8
; CHECK-NEXT:    [[DST_2:%.*]] = getelementptr i8, ptr addrspace(5) [[DST]], i32 16
; CHECK-NEXT:    [[D2:%.*]] = load double, ptr addrspace(5) [[DST_2]], align 8
; CHECK-NEXT:    [[SCEVGEP:%.*]] = getelementptr i8, ptr null, i64 [[LSR_IV]]
; CHECK-NEXT:    [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 16
; CHECK-NEXT:    [[S2:%.*]] = load double, ptr [[SCEVGEP1]], align 8
; CHECK-NEXT:    [[DST_NEXT]] = getelementptr i8, ptr addrspace(5) [[DST]], i32 96
; CHECK-NEXT:    [[LSR_IV_NEXT]] = add nuw nsw i64 [[LSR_IV]], 96
; CHECK-NEXT:    [[DONE:%.*]] = icmp eq i64 [[LSR_IV_NEXT]], 96
; CHECK-NEXT:    br i1 [[DONE]], label %[[EXIT:.*]], label %[[LOOP]]
; CHECK:       [[EXIT]]:
; CHECK-NEXT:    ret void
;
entry:
  br label %loop

loop:
  %src = phi ptr [ null, %entry ], [ %src.next, %loop ]
  %dst = phi ptr addrspace(5) [ %scratch, %entry ], [ %dst.next, %loop ]
  %d0 = load double, ptr addrspace(5) %dst, align 8
  %s0 = load double, ptr %src, align 8
  %dst.1 = getelementptr i8, ptr addrspace(5) %dst, i32 8
  %d1 = load double, ptr addrspace(5) %dst.1, align 8
  %src.1 = getelementptr i8, ptr %src, i64 8
  %s1 = load double, ptr %src.1, align 8
  %dst.2 = getelementptr i8, ptr addrspace(5) %dst, i32 16
  %d2 = load double, ptr addrspace(5) %dst.2, align 8
  %src.2 = getelementptr i8, ptr %src, i64 16
  %s2 = load double, ptr %src.2, align 8
  %dst.next = getelementptr i8, ptr addrspace(5) %dst, i32 96
  %src.next = getelementptr i8, ptr %src, i64 96
  %done = icmp eq ptr addrspace(5) %dst, %scratch
  br i1 %done, label %exit, label %loop

exit:
  ret void
}