llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-simplify-image-array-zero-slice.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -S -passes=instcombine -mtriple=amdgpu12.01 %s | FileCheck %s

define amdgpu_ps void @store_1darray_zero_slice(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s) {
; CHECK-LABEL: define amdgpu_ps void @store_1darray_zero_slice(
; CHECK-SAME: <8 x i32> inreg [[RSRC:%.*]], <4 x float> [[VDATA:%.*]], i32 [[S:%.*]]) {
; CHECK-NEXT:    call void @llvm.amdgcn.image.store.1d.v4f32.i32.v8i32(<4 x float> [[VDATA]], i32 15, i32 [[S]], <8 x i32> [[RSRC]], i32 0, i32 0)
; CHECK-NEXT:    ret void
;
  call void @llvm.amdgcn.image.store.1darray.v4f32.i32.v8i32(<4 x float> %vdata, i32 15, i32 %s, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
  ret void
}

define amdgpu_ps void @store_2darray_zero_slice(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t) {
; CHECK-LABEL: define amdgpu_ps void @store_2darray_zero_slice(
; CHECK-SAME: <8 x i32> inreg [[RSRC:%.*]], <4 x float> [[VDATA:%.*]], i32 [[S:%.*]], i32 [[T:%.*]]) {
; CHECK-NEXT:    call void @llvm.amdgcn.image.store.2d.v4f32.i32.v8i32(<4 x float> [[VDATA]], i32 15, i32 [[S]], i32 [[T]], <8 x i32> [[RSRC]], i32 0, i32 0)
; CHECK-NEXT:    ret void
;
  call void @llvm.amdgcn.image.store.2darray.v4f32.i32.v8i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
  ret void
}

define amdgpu_ps void @store_2darray_zero_slice_f16(<8 x i32> inreg %rsrc, <4 x half> %vdata, i32 %s, i32 %t) {
; CHECK-LABEL: define amdgpu_ps void @store_2darray_zero_slice_f16(
; CHECK-SAME: <8 x i32> inreg [[RSRC:%.*]], <4 x half> [[VDATA:%.*]], i32 [[S:%.*]], i32 [[T:%.*]]) {
; CHECK-NEXT:    call void @llvm.amdgcn.image.store.2d.v4f16.i32.v8i32(<4 x half> [[VDATA]], i32 15, i32 [[S]], i32 [[T]], <8 x i32> [[RSRC]], i32 0, i32 0)
; CHECK-NEXT:    ret void
;
  call void @llvm.amdgcn.image.store.2darray.v4f16.i32.v8i32(<4 x half> %vdata, i32 15, i32 %s, i32 %t, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
  ret void
}

define amdgpu_ps void @store_2darraymsaa_zero_slice(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t, i32 %fragid) {
; CHECK-LABEL: define amdgpu_ps void @store_2darraymsaa_zero_slice(
; CHECK-SAME: <8 x i32> inreg [[RSRC:%.*]], <4 x float> [[VDATA:%.*]], i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]]) {
; CHECK-NEXT:    call void @llvm.amdgcn.image.store.2dmsaa.v4f32.i32.v8i32(<4 x float> [[VDATA]], i32 15, i32 [[S]], i32 [[T]], i32 [[FRAGID]], <8 x i32> [[RSRC]], i32 0, i32 0)
; CHECK-NEXT:    ret void
;
  call void @llvm.amdgcn.image.store.2darraymsaa.v4f32.i32.v8i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 0, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
  ret void
}

define amdgpu_ps void @store_mip_2darray_zero_slice_nonzero_mip(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t) {
; CHECK-LABEL: define amdgpu_ps void @store_mip_2darray_zero_slice_nonzero_mip(
; CHECK-SAME: <8 x i32> inreg [[RSRC:%.*]], <4 x float> [[VDATA:%.*]], i32 [[S:%.*]], i32 [[T:%.*]]) {
; CHECK-NEXT:    call void @llvm.amdgcn.image.store.mip.2d.v4f32.i32.v8i32(<4 x float> [[VDATA]], i32 15, i32 [[S]], i32 [[T]], i32 2, <8 x i32> [[RSRC]], i32 0, i32 0)
; CHECK-NEXT:    ret void
;
  call void @llvm.amdgcn.image.store.mip.2darray.v4f32.i32.v8i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 0, i32 2, <8 x i32> %rsrc, i32 0, i32 0)
  ret void
}

define amdgpu_ps void @store_2darray_zero_slice_a16(<8 x i32> inreg %rsrc, <4 x float> %vdata, i16 %s, i16 %t) {
; CHECK-LABEL: define amdgpu_ps void @store_2darray_zero_slice_a16(
; CHECK-SAME: <8 x i32> inreg [[RSRC:%.*]], <4 x float> [[VDATA:%.*]], i16 [[S:%.*]], i16 [[T:%.*]]) {
; CHECK-NEXT:    call void @llvm.amdgcn.image.store.2d.v4f32.i16.v8i32(<4 x float> [[VDATA]], i32 15, i16 [[S]], i16 [[T]], <8 x i32> [[RSRC]], i32 0, i32 0)
; CHECK-NEXT:    ret void
;
  call void @llvm.amdgcn.image.store.2darray.v4f32.i16.v8i32(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 0, <8 x i32> %rsrc, i32 0, i32 0)
  ret void
}

define amdgpu_ps <4 x float> @load_1darray_zero_slice(<8 x i32> inreg %rsrc, i32 %s) {
; CHECK-LABEL: define amdgpu_ps <4 x float> @load_1darray_zero_slice(
; CHECK-SAME: <8 x i32> inreg [[RSRC:%.*]], i32 [[S:%.*]]) {
; CHECK-NEXT:    [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32.v8i32(i32 15, i32 [[S]], <8 x i32> [[RSRC]], i32 0, i32 0)
; CHECK-NEXT:    ret <4 x float> [[V]]
;
  %v = call <4 x float> @llvm.amdgcn.image.load.1darray.v4f32.i32.v8i32(i32 15, i32 %s, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
  ret <4 x float> %v
}

define amdgpu_ps <4 x float> @load_2darray_zero_slice(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
; CHECK-LABEL: define amdgpu_ps <4 x float> @load_2darray_zero_slice(
; CHECK-SAME: <8 x i32> inreg [[RSRC:%.*]], i32 [[S:%.*]], i32 [[T:%.*]]) {
; CHECK-NEXT:    [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32.v8i32(i32 15, i32 [[S]], i32 [[T]], <8 x i32> [[RSRC]], i32 0, i32 0)
; CHECK-NEXT:    ret <4 x float> [[V]]
;
  %v = call <4 x float> @llvm.amdgcn.image.load.2darray.v4f32.i32.v8i32(i32 15, i32 %s, i32 %t, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
  ret <4 x float> %v
}

define amdgpu_ps <4 x half> @load_2darray_zero_slice_f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
; CHECK-LABEL: define amdgpu_ps <4 x half> @load_2darray_zero_slice_f16(
; CHECK-SAME: <8 x i32> inreg [[RSRC:%.*]], i32 [[S:%.*]], i32 [[T:%.*]]) {
; CHECK-NEXT:    [[V:%.*]] = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i32.v8i32(i32 15, i32 [[S]], i32 [[T]], <8 x i32> [[RSRC]], i32 0, i32 0)
; CHECK-NEXT:    ret <4 x half> [[V]]
;
  %v = call <4 x half> @llvm.amdgcn.image.load.2darray.v4f16.i32.v8i32(i32 15, i32 %s, i32 %t, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
  ret <4 x half> %v
}

define amdgpu_ps <4 x float> @load_2darraymsaa_zero_slice(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %fragid) {
; CHECK-LABEL: define amdgpu_ps <4 x float> @load_2darraymsaa_zero_slice(
; CHECK-SAME: <8 x i32> inreg [[RSRC:%.*]], i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]]) {
; CHECK-NEXT:    [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.load.2dmsaa.v4f32.i32.v8i32(i32 15, i32 [[S]], i32 [[T]], i32 [[FRAGID]], <8 x i32> [[RSRC]], i32 0, i32 0)
; CHECK-NEXT:    ret <4 x float> [[V]]
;
  %v = call <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i32.v8i32(i32 15, i32 %s, i32 %t, i32 0, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
  ret <4 x float> %v
}

define amdgpu_ps <4 x float> @msaa_load_x_2darraymsaa_zero_slice(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %fragid) {
; CHECK-LABEL: define amdgpu_ps <4 x float> @msaa_load_x_2darraymsaa_zero_slice(
; CHECK-SAME: <8 x i32> inreg [[RSRC:%.*]], i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]]) {
; CHECK-NEXT:    [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v4f32.i32.v8i32(i32 15, i32 [[S]], i32 [[T]], i32 [[FRAGID]], <8 x i32> [[RSRC]], i32 0, i32 0)
; CHECK-NEXT:    ret <4 x float> [[V]]
;
  %v = call <4 x float> @llvm.amdgcn.image.msaa.load.x.2darraymsaa.v4f32.i32.v8i32(i32 15, i32 %s, i32 %t, i32 0, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
  ret <4 x float> %v
}

define amdgpu_ps void @store_2darray_nonzero_slice(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t) {
; CHECK-LABEL: define amdgpu_ps void @store_2darray_nonzero_slice(
; CHECK-SAME: <8 x i32> inreg [[RSRC:%.*]], <4 x float> [[VDATA:%.*]], i32 [[S:%.*]], i32 [[T:%.*]]) {
; CHECK-NEXT:    call void @llvm.amdgcn.image.store.2darray.v4f32.i32.v8i32(<4 x float> [[VDATA]], i32 15, i32 [[S]], i32 [[T]], i32 1, <8 x i32> [[RSRC]], i32 0, i32 0)
; CHECK-NEXT:    ret void
;
  call void @llvm.amdgcn.image.store.2darray.v4f32.i32.v8i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 1, <8 x i32> %rsrc, i32 0, i32 0)
  ret void
}

define amdgpu_ps void @store_2darray_variable_slice(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t, i32 %slice) {
; CHECK-LABEL: define amdgpu_ps void @store_2darray_variable_slice(
; CHECK-SAME: <8 x i32> inreg [[RSRC:%.*]], <4 x float> [[VDATA:%.*]], i32 [[S:%.*]], i32 [[T:%.*]], i32 [[SLICE:%.*]]) {
; CHECK-NEXT:    call void @llvm.amdgcn.image.store.2darray.v4f32.i32.v8i32(<4 x float> [[VDATA]], i32 15, i32 [[S]], i32 [[T]], i32 [[SLICE]], <8 x i32> [[RSRC]], i32 0, i32 0)
; CHECK-NEXT:    ret void
;
  call void @llvm.amdgcn.image.store.2darray.v4f32.i32.v8i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0)
  ret void
}

define amdgpu_ps void @store_cube_zero_face(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t) {
; CHECK-LABEL: define amdgpu_ps void @store_cube_zero_face(
; CHECK-SAME: <8 x i32> inreg [[RSRC:%.*]], <4 x float> [[VDATA:%.*]], i32 [[S:%.*]], i32 [[T:%.*]]) {
; CHECK-NEXT:    call void @llvm.amdgcn.image.store.cube.v4f32.i32.v8i32(<4 x float> [[VDATA]], i32 15, i32 [[S]], i32 [[T]], i32 0, <8 x i32> [[RSRC]], i32 0, i32 0)
; CHECK-NEXT:    ret void
;
  call void @llvm.amdgcn.image.store.cube.v4f32.i32.v8i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
  ret void
}

define amdgpu_ps void @store_3d_zero_r(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t) {
; CHECK-LABEL: define amdgpu_ps void @store_3d_zero_r(
; CHECK-SAME: <8 x i32> inreg [[RSRC:%.*]], <4 x float> [[VDATA:%.*]], i32 [[S:%.*]], i32 [[T:%.*]]) {
; CHECK-NEXT:    call void @llvm.amdgcn.image.store.3d.v4f32.i32.v8i32(<4 x float> [[VDATA]], i32 15, i32 [[S]], i32 [[T]], i32 0, <8 x i32> [[RSRC]], i32 0, i32 0)
; CHECK-NEXT:    ret void
;
  call void @llvm.amdgcn.image.store.3d.v4f32.i32.v8i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
  ret void
}

define amdgpu_ps <4 x float> @getresinfo_2darray_zero_mip(<8 x i32> inreg %rsrc) {
; CHECK-LABEL: define amdgpu_ps <4 x float> @getresinfo_2darray_zero_mip(
; CHECK-SAME: <8 x i32> inreg [[RSRC:%.*]]) {
; CHECK-NEXT:    [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.getresinfo.2darray.v4f32.i16.v8i32(i32 15, i16 0, <8 x i32> [[RSRC]], i32 0, i32 0)
; CHECK-NEXT:    ret <4 x float> [[V]]
;
  %v = call <4 x float> @llvm.amdgcn.image.getresinfo.2darray.v4f32.i32.v8i32(i32 15, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
  ret <4 x float> %v
}

define amdgpu_ps <4 x float> @sample_cl_2darray_zero_slice_zero_clamp(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) {
; CHECK-LABEL: define amdgpu_ps <4 x float> @sample_cl_2darray_zero_slice_zero_clamp(
; CHECK-SAME: <8 x i32> inreg [[RSRC:%.*]], <4 x i32> inreg [[SAMP:%.*]], float [[S:%.*]], float [[T:%.*]]) {
; CHECK-NEXT:    [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.cl.2darray.v4f32.f32.v8i32.v4i32(i32 15, float [[S]], float [[T]], float 0.000000e+00, float 0.000000e+00, <8 x i32> [[RSRC]], <4 x i32> [[SAMP]], i1 false, i32 0, i32 0)
; CHECK-NEXT:    ret <4 x float> [[V]]
;
  %v = call <4 x float> @llvm.amdgcn.image.sample.cl.2darray.v4f32.f32.v8i32.v4i32(i32 15, float %s, float %t, float 0.0, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
  ret <4 x float> %v
}

define amdgpu_ps i32 @atomic_add_2darray_zero_slice(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %t) {
; CHECK-LABEL: define amdgpu_ps i32 @atomic_add_2darray_zero_slice(
; CHECK-SAME: <8 x i32> inreg [[RSRC:%.*]], i32 [[DATA:%.*]], i32 [[S:%.*]], i32 [[T:%.*]]) {
; CHECK-NEXT:    [[V:%.*]] = call i32 @llvm.amdgcn.image.atomic.add.2darray.i32.i32.v8i32(i32 [[DATA]], i32 [[S]], i32 [[T]], i32 0, <8 x i32> [[RSRC]], i32 0, i32 0)
; CHECK-NEXT:    ret i32 [[V]]
;
  %v = call i32 @llvm.amdgcn.image.atomic.add.2darray.i32.i32.v8i32(i32 %data, i32 %s, i32 %t, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
  ret i32 %v
}

define amdgpu_ps <2 x half> @atomic_pk_add_f16_2darray_zero_slice(<8 x i32> inreg %rsrc, <2 x half> %data, i32 %s, i32 %t) {
; CHECK-LABEL: define amdgpu_ps <2 x half> @atomic_pk_add_f16_2darray_zero_slice(
; CHECK-SAME: <8 x i32> inreg [[RSRC:%.*]], <2 x half> [[DATA:%.*]], i32 [[S:%.*]], i32 [[T:%.*]]) {
; CHECK-NEXT:    [[V:%.*]] = call <2 x half> @llvm.amdgcn.image.atomic.pk.add.f16.2darray.v2f16.i32.v8i32(<2 x half> [[DATA]], i32 [[S]], i32 [[T]], i32 0, <8 x i32> [[RSRC]], i32 0, i32 0)
; CHECK-NEXT:    ret <2 x half> [[V]]
;
  %v = call <2 x half> @llvm.amdgcn.image.atomic.pk.add.f16.2darray.v2f16.i32.v8i32(<2 x half> %data, i32 %s, i32 %t, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
  ret <2 x half> %v
}