llvm/test/Transforms/CodeGenPrepare/RISCV/xqcilo.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' \
; RUN:   -mtriple=riscv32 -mattr=+xqcilo < %s | FileCheck %s --check-prefix=XQCILO

; Two loads in separate blocks share a base pointer with large (26-bit) byte
; offsets. CodeGenPrepare's splitLargeGEPOffsets queries
; RISCVTargetLowering::isLegalAddressingMode to decide whether the offsets can
; be folded into the addressing mode. With Xqcilo, isLegalAddressingMode now
; accepts 26-bit offsets, so the GEPs are left intact and each access keeps its
; full offset instead of being split out into a separate base address.
define i32 @split_large_geps(ptr %p, i1 %c) {
; XQCILO-LABEL: define i32 @split_large_geps(
; XQCILO-SAME: ptr [[P:%.*]], i1 [[C:%.*]]) #[[ATTR0:[0-9]+]] {
; XQCILO-NEXT:  [[ENTRY:.*:]]
; XQCILO-NEXT:    br i1 [[C]], label %[[A:.*]], label %[[B:.*]]
; XQCILO:       [[A]]:
; XQCILO-NEXT:    [[SPLITGEP:%.*]] = getelementptr i8, ptr [[P]], i32 20000
; XQCILO-NEXT:    [[V0:%.*]] = load i32, ptr [[SPLITGEP]], align 4
; XQCILO-NEXT:    br label %[[MERGE:.*]]
; XQCILO:       [[B]]:
; XQCILO-NEXT:    [[TMP0:%.*]] = getelementptr i8, ptr [[P]], i32 20004
; XQCILO-NEXT:    [[V1:%.*]] = load i32, ptr [[TMP0]], align 4
; XQCILO-NEXT:    br label %[[MERGE]]
; XQCILO:       [[MERGE]]:
; XQCILO-NEXT:    [[R:%.*]] = phi i32 [ [[V0]], %[[A]] ], [ [[V1]], %[[B]] ]
; XQCILO-NEXT:    ret i32 [[R]]
;
entry:
  br i1 %c, label %a, label %b

a:
  %g0 = getelementptr i8, ptr %p, i32 20000
  %v0 = load i32, ptr %g0
  br label %merge

b:
  %g1 = getelementptr i8, ptr %p, i32 20004
  %v1 = load i32, ptr %g1
  br label %merge

merge:
  %r = phi i32 [ %v0, %a ], [ %v1, %b ]
  ret i32 %r
}