llvm/test/CodeGen/X86/vector-idiv-strictfp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=CHECK

define <16 x i8> @test_divv_16i8_strictfp(<16 x i8> %a, <16 x i8> %b) nounwind strictfp {
; CHECK-LABEL: test_divv_16i8_strictfp:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vpmovzxbd {{.*#+}} zmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero,xmm1[8],zero,zero,zero,xmm1[9],zero,zero,zero,xmm1[10],zero,zero,zero,xmm1[11],zero,zero,zero,xmm1[12],zero,zero,zero,xmm1[13],zero,zero,zero,xmm1[14],zero,zero,zero,xmm1[15],zero,zero,zero
; CHECK-NEXT:    vcvtdq2ps %zmm1, %zmm1
; CHECK-NEXT:    vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; CHECK-NEXT:    vcvtdq2ps %zmm0, %zmm0
; CHECK-NEXT:    vdivps {rn-sae}, %zmm1, %zmm0, %zmm0
; CHECK-NEXT:    vcvttps2udq {sae}, %zmm0, %zmm0
; CHECK-NEXT:    vpmovdb %zmm0, %xmm0
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %res = udiv <16 x i8> %a, %b
  ret <16 x i8> %res
}

define <4 x i32> @test_sdivv_4i32_strictfp(<4 x i32> %a, <4 x i32> %b) nounwind strictfp {
; CHECK-LABEL: test_sdivv_4i32_strictfp:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vcvtdq2pd %xmm1, %ymm1
; CHECK-NEXT:    vcvtdq2pd %xmm0, %ymm0
; CHECK-NEXT:    vdivpd {rn-sae}, %zmm1, %zmm0, %zmm0
; CHECK-NEXT:    vcvttpd2dq {sae}, %zmm0, %ymm0
; CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 killed $ymm0
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %res = sdiv <4 x i32> %a, %b
  ret <4 x i32> %res
}

define <8 x i16> @test_sdivv_8i16_strictfp(<8 x i16> %a, <8 x i16> %b) nounwind strictfp {
; CHECK-LABEL: test_sdivv_8i16_strictfp:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vpmovsxwd %xmm1, %ymm1
; CHECK-NEXT:    vcvtdq2ps %ymm1, %ymm1
; CHECK-NEXT:    vpmovsxwd %xmm0, %ymm0
; CHECK-NEXT:    vcvtdq2ps %ymm0, %ymm0
; CHECK-NEXT:    vdivps {rn-sae}, %zmm1, %zmm0, %zmm0
; CHECK-NEXT:    vcvttps2dq {sae}, %zmm0, %zmm0
; CHECK-NEXT:    vpmovdw %zmm0, %ymm0
; CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 killed $ymm0
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %res = sdiv <8 x i16> %a, %b
  ret <8 x i16> %res
}

define <8 x i32> @test_remv_8i32_strictfp(<8 x i32> %a, <8 x i32> %b) nounwind strictfp {
; CHECK-LABEL: test_remv_8i32_strictfp:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vcvtudq2pd %ymm1, %zmm2
; CHECK-NEXT:    vcvtudq2pd %ymm0, %zmm3
; CHECK-NEXT:    vdivpd {rn-sae}, %zmm2, %zmm3, %zmm2
; CHECK-NEXT:    vcvttpd2udq {sae}, %zmm2, %ymm2
; CHECK-NEXT:    vpmulld %ymm1, %ymm2, %ymm1
; CHECK-NEXT:    vpsubd %ymm1, %ymm0, %ymm0
; CHECK-NEXT:    retq
  %res = urem <8 x i32> %a, %b
  ret <8 x i32> %res
}

define <8 x i32> @test_masked_divv_8i32_strictfp(<8 x i32> %a, <8 x i32> %b, <8 x i1> %m) nounwind strictfp {
; CHECK-LABEL: test_masked_divv_8i32_strictfp:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vcvtudq2pd %ymm1, %zmm1
; CHECK-NEXT:    vcvtudq2pd %ymm0, %zmm0
; CHECK-NEXT:    vdivpd {rn-sae}, %zmm1, %zmm0, %zmm0
; CHECK-NEXT:    vcvttpd2udq {sae}, %zmm0, %ymm0
; CHECK-NEXT:    retq
  %res = call <8 x i32> @llvm.masked.udiv(<8 x i32> %a, <8 x i32> %b, <8 x i1> %m)
  ret <8 x i32> %res
}

define <16 x i32> @test_masked_divv_16i32_strictfp(<16 x i32> %a, <16 x i32> %b, <16 x i1> %m) nounwind strictfp {
; CHECK-LABEL: test_masked_divv_16i32_strictfp:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vcvtudq2pd %ymm1, %zmm2
; CHECK-NEXT:    vcvtudq2pd %ymm0, %zmm3
; CHECK-NEXT:    vdivpd {rn-sae}, %zmm2, %zmm3, %zmm2
; CHECK-NEXT:    vcvttpd2udq {sae}, %zmm2, %ymm2
; CHECK-NEXT:    vextractf64x4 $1, %zmm1, %ymm1
; CHECK-NEXT:    vcvtudq2pd %ymm1, %zmm1
; CHECK-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
; CHECK-NEXT:    vcvtudq2pd %ymm0, %zmm0
; CHECK-NEXT:    vdivpd {rn-sae}, %zmm1, %zmm0, %zmm0
; CHECK-NEXT:    vcvttpd2udq {sae}, %zmm0, %ymm0
; CHECK-NEXT:    vinsertf64x4 $1, %ymm0, %zmm2, %zmm0
; CHECK-NEXT:    retq
  %res = call <16 x i32> @llvm.masked.udiv(<16 x i32> %a, <16 x i32> %b, <16 x i1> %m)
  ret <16 x i32> %res
}

define <16 x i32> @test_divv_16i32_strictfp(<16 x i32> %a, <16 x i32> %b) nounwind strictfp {
; CHECK-LABEL: test_divv_16i32_strictfp:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vcvtudq2pd %ymm1, %zmm2
; CHECK-NEXT:    vcvtudq2pd %ymm0, %zmm3
; CHECK-NEXT:    vdivpd {rn-sae}, %zmm2, %zmm3, %zmm2
; CHECK-NEXT:    vcvttpd2udq {sae}, %zmm2, %ymm2
; CHECK-NEXT:    vextractf64x4 $1, %zmm1, %ymm1
; CHECK-NEXT:    vcvtudq2pd %ymm1, %zmm1
; CHECK-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
; CHECK-NEXT:    vcvtudq2pd %ymm0, %zmm0
; CHECK-NEXT:    vdivpd {rn-sae}, %zmm1, %zmm0, %zmm0
; CHECK-NEXT:    vcvttpd2udq {sae}, %zmm0, %ymm0
; CHECK-NEXT:    vinsertf64x4 $1, %ymm0, %zmm2, %zmm0
; CHECK-NEXT:    retq
  %res = udiv <16 x i32> %a, %b
  ret <16 x i32> %res
}

define void @test_divv_9i32_strictfp(<9 x i32> %a, <9 x i32> %b, ptr %p) nounwind strictfp {
; CHECK-LABEL: test_divv_9i32_strictfp:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vcvtdq2pd %ymm1, %zmm2
; CHECK-NEXT:    vcvtdq2pd %ymm0, %zmm3
; CHECK-NEXT:    vdivpd {rn-sae}, %zmm2, %zmm3, %zmm2
; CHECK-NEXT:    vcvttpd2dq {sae}, %zmm2, %ymm2
; CHECK-NEXT:    vextracti32x4 $2, %zmm0, %xmm0
; CHECK-NEXT:    vmovd %xmm0, %eax
; CHECK-NEXT:    vextracti32x4 $2, %zmm1, %xmm0
; CHECK-NEXT:    vmovd %xmm0, %ecx
; CHECK-NEXT:    cltd
; CHECK-NEXT:    idivl %ecx
; CHECK-NEXT:    movl %eax, 32(%rdi)
; CHECK-NEXT:    vmovaps %ymm2, (%rdi)
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %res = sdiv <9 x i32> %a, %b
  store <9 x i32> %res, ptr %p
  ret void
}

define void @test_divv_12i32_strictfp(<12 x i32> %a, <12 x i32> %b, ptr %p) nounwind strictfp {
; CHECK-LABEL: test_divv_12i32_strictfp:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vextractf32x4 $2, %zmm1, %xmm2
; CHECK-NEXT:    vcvtdq2pd %xmm2, %ymm2
; CHECK-NEXT:    vextractf32x4 $2, %zmm0, %xmm3
; CHECK-NEXT:    vcvtdq2pd %xmm3, %ymm3
; CHECK-NEXT:    vdivpd {rn-sae}, %zmm2, %zmm3, %zmm2
; CHECK-NEXT:    vcvttpd2dq {sae}, %zmm2, %ymm2
; CHECK-NEXT:    vcvtdq2pd %ymm1, %zmm1
; CHECK-NEXT:    vcvtdq2pd %ymm0, %zmm0
; CHECK-NEXT:    vdivpd {rn-sae}, %zmm1, %zmm0, %zmm0
; CHECK-NEXT:    vcvttpd2dq {sae}, %zmm0, %ymm0
; CHECK-NEXT:    vmovaps %ymm0, (%rdi)
; CHECK-NEXT:    vmovaps %xmm2, 32(%rdi)
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %res = sdiv <12 x i32> %a, %b
  store <12 x i32> %res, ptr %p
  ret void
}

define <6 x i32> @test_masked_divv_6i32_strictfp(<6 x i32> %a, <6 x i32> %b, <6 x i1> %m) nounwind strictfp {
; CHECK-LABEL: test_masked_divv_6i32_strictfp:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vcvtdq2pd %ymm1, %zmm1
; CHECK-NEXT:    vcvtdq2pd %ymm0, %zmm0
; CHECK-NEXT:    vdivpd {rn-sae}, %zmm1, %zmm0, %zmm0
; CHECK-NEXT:    vcvttpd2dq {sae}, %zmm0, %ymm0
; CHECK-NEXT:    retq
  %res = call <6 x i32> @llvm.masked.sdiv(<6 x i32> %a, <6 x i32> %b, <6 x i1> %m)
  ret <6 x i32> %res
}

define void @test_divv_32i32_strictfp(<32 x i32> %a, <32 x i32> %b, ptr %p) nounwind strictfp {
; CHECK-LABEL: test_divv_32i32_strictfp:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vcvtdq2pd %ymm2, %zmm4
; CHECK-NEXT:    vcvtdq2pd %ymm0, %zmm5
; CHECK-NEXT:    vdivpd {rn-sae}, %zmm4, %zmm5, %zmm4
; CHECK-NEXT:    vcvttpd2dq {sae}, %zmm4, %ymm4
; CHECK-NEXT:    vextractf64x4 $1, %zmm2, %ymm2
; CHECK-NEXT:    vcvtdq2pd %ymm2, %zmm2
; CHECK-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
; CHECK-NEXT:    vcvtdq2pd %ymm0, %zmm0
; CHECK-NEXT:    vdivpd {rn-sae}, %zmm2, %zmm0, %zmm0
; CHECK-NEXT:    vcvttpd2dq {sae}, %zmm0, %ymm0
; CHECK-NEXT:    vinsertf64x4 $1, %ymm0, %zmm4, %zmm0
; CHECK-NEXT:    vcvtdq2pd %ymm3, %zmm2
; CHECK-NEXT:    vcvtdq2pd %ymm1, %zmm4
; CHECK-NEXT:    vdivpd {rn-sae}, %zmm2, %zmm4, %zmm2
; CHECK-NEXT:    vcvttpd2dq {sae}, %zmm2, %ymm2
; CHECK-NEXT:    vextractf64x4 $1, %zmm3, %ymm3
; CHECK-NEXT:    vcvtdq2pd %ymm3, %zmm3
; CHECK-NEXT:    vextractf64x4 $1, %zmm1, %ymm1
; CHECK-NEXT:    vcvtdq2pd %ymm1, %zmm1
; CHECK-NEXT:    vdivpd {rn-sae}, %zmm3, %zmm1, %zmm1
; CHECK-NEXT:    vcvttpd2dq {sae}, %zmm1, %ymm1
; CHECK-NEXT:    vinsertf64x4 $1, %ymm1, %zmm2, %zmm1
; CHECK-NEXT:    vmovaps %zmm1, 64(%rdi)
; CHECK-NEXT:    vmovaps %zmm0, (%rdi)
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %res = sdiv <32 x i32> %a, %b
  store <32 x i32> %res, ptr %p
  ret void
}