llvm/test/CodeGen/X86/known-fpclass.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s

define i1 @sqrt_neginf_f32(float %a0) {
; CHECK-LABEL: sqrt_neginf_f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsqrtss %xmm0, %xmm0, %xmm0
; CHECK-NEXT:    vmovd %xmm0, %eax
; CHECK-NEXT:    cmpl $-8388608, %eax # imm = 0xFF800000
; CHECK-NEXT:    sete %al
; CHECK-NEXT:    retq
  %sqr = call float @llvm.sqrt.f32(float %a0)
  %res = tail call i1 @llvm.is.fpclass.f32(float %sqr, i32 4)  ; 0x4 = "neginf"
  ret i1 %res
}

define i1 @sqrt_neginf_v4f32(<4 x float> %a0, ptr %p1) {
; CHECK-LABEL: sqrt_neginf_v4f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsqrtps %xmm0, %xmm0
; CHECK-NEXT:    vmovaps %xmm0, (%rdi)
; CHECK-NEXT:    vextractps $0, %xmm0, %eax
; CHECK-NEXT:    cmpl $-8388608, %eax # imm = 0xFF800000
; CHECK-NEXT:    sete %al
; CHECK-NEXT:    retq
  %sqr = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %a0)
  store <4 x float> %sqr, ptr %p1
  %elt = extractelement <4 x float> %sqr, i32 0
  %res = tail call i1 @llvm.is.fpclass.f32(float %elt, i32 4)  ; 0x4 = "neginf"
  ret i1 %res
}