llvm/test/CodeGen/X86/extractsubvector-load.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown   -mattr=+sse2 | FileCheck %s --check-prefixes=X86-SSE
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3 | FileCheck %s --check-prefixes=X64-SSE
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx  | FileCheck %s --check-prefixes=X64-AVX,X64-AVX1
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=X64-AVX,X64-AVX2
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=X64-AVX,X64-AVX512

define <4 x i32> @load_v8i32_v4i32_ofs4(ptr %val) nounwind {
; X86-SSE-LABEL: load_v8i32_v4i32_ofs4:
; X86-SSE:       # %bb.0:
; X86-SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT:    movaps 16(%eax), %xmm0
; X86-SSE-NEXT:    retl
;
; X64-SSE-LABEL: load_v8i32_v4i32_ofs4:
; X64-SSE:       # %bb.0:
; X64-SSE-NEXT:    movaps 16(%rdi), %xmm0
; X64-SSE-NEXT:    retq
;
; X64-AVX-LABEL: load_v8i32_v4i32_ofs4:
; X64-AVX:       # %bb.0:
; X64-AVX-NEXT:    vmovaps 16(%rdi), %xmm0
; X64-AVX-NEXT:    retq
  %ld = load <8 x i32>, ptr %val
  %sub = shufflevector <8 x i32> %ld, <8 x i32> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
  ret <4 x i32> %sub
}

define <4 x float> @load_v16f32_v4f32_ofs0(ptr %val) nounwind {
; X86-SSE-LABEL: load_v16f32_v4f32_ofs0:
; X86-SSE:       # %bb.0:
; X86-SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT:    movaps (%eax), %xmm0
; X86-SSE-NEXT:    retl
;
; X64-SSE-LABEL: load_v16f32_v4f32_ofs0:
; X64-SSE:       # %bb.0:
; X64-SSE-NEXT:    movaps (%rdi), %xmm0
; X64-SSE-NEXT:    retq
;
; X64-AVX-LABEL: load_v16f32_v4f32_ofs0:
; X64-AVX:       # %bb.0:
; X64-AVX-NEXT:    vmovaps (%rdi), %xmm0
; X64-AVX-NEXT:    retq
  %ld = load <16 x float>, ptr %val
  %sub = shufflevector <16 x float> %ld, <16 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  ret <4 x float> %sub
}

define <4 x float> @load_v16f32_v4f32_ofs7(ptr %val) nounwind {
; X86-SSE-LABEL: load_v16f32_v4f32_ofs7:
; X86-SSE:       # %bb.0:
; X86-SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT:    movaps 32(%eax), %xmm1
; X86-SSE-NEXT:    movaps %xmm1, %xmm0
; X86-SSE-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,0],mem[3,0]
; X86-SSE-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[1,2]
; X86-SSE-NEXT:    retl
;
; X64-SSE-LABEL: load_v16f32_v4f32_ofs7:
; X64-SSE:       # %bb.0:
; X64-SSE-NEXT:    movaps 32(%rdi), %xmm1
; X64-SSE-NEXT:    movaps %xmm1, %xmm0
; X64-SSE-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,0],mem[3,0]
; X64-SSE-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[1,2]
; X64-SSE-NEXT:    retq
;
; X64-AVX1-LABEL: load_v16f32_v4f32_ofs7:
; X64-AVX1:       # %bb.0:
; X64-AVX1-NEXT:    vmovaps 32(%rdi), %xmm0
; X64-AVX1-NEXT:    vblendps {{.*#+}} xmm0 = xmm0[0,1,2],mem[3]
; X64-AVX1-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[3,0,1,2]
; X64-AVX1-NEXT:    retq
;
; X64-AVX2-LABEL: load_v16f32_v4f32_ofs7:
; X64-AVX2:       # %bb.0:
; X64-AVX2-NEXT:    vmovaps {{.*#+}} xmm0 = [7,0,1,2]
; X64-AVX2-NEXT:    vmovaps 32(%rdi), %ymm1
; X64-AVX2-NEXT:    vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3],mem[4,5,6,7]
; X64-AVX2-NEXT:    vpermps %ymm1, %ymm0, %ymm0
; X64-AVX2-NEXT:    # kill: def $xmm0 killed $xmm0 killed $ymm0
; X64-AVX2-NEXT:    vzeroupper
; X64-AVX2-NEXT:    retq
;
; X64-AVX512-LABEL: load_v16f32_v4f32_ofs7:
; X64-AVX512:       # %bb.0:
; X64-AVX512-NEXT:    vpmovsxbd {{.*#+}} xmm1 = [23,0,1,2]
; X64-AVX512-NEXT:    vmovaps (%rdi), %ymm2
; X64-AVX512-NEXT:    vmovaps 32(%rdi), %ymm0
; X64-AVX512-NEXT:    vpermt2ps %zmm2, %zmm1, %zmm0
; X64-AVX512-NEXT:    # kill: def $xmm0 killed $xmm0 killed $zmm0
; X64-AVX512-NEXT:    vzeroupper
; X64-AVX512-NEXT:    retq
  %ld = load <16 x float>, ptr %val
  %sub = shufflevector <16 x float> %ld, <16 x float> poison, <4 x i32> <i32 7, i32 8, i32 9, i32 10>
  ret <4 x float> %sub
}

define <8 x float> @load_v16f32_v8f32_ofs4(ptr %val) nounwind {
; X86-SSE-LABEL: load_v16f32_v8f32_ofs4:
; X86-SSE:       # %bb.0:
; X86-SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT:    movaps 16(%eax), %xmm0
; X86-SSE-NEXT:    movaps 32(%eax), %xmm1
; X86-SSE-NEXT:    retl
;
; X64-SSE-LABEL: load_v16f32_v8f32_ofs4:
; X64-SSE:       # %bb.0:
; X64-SSE-NEXT:    movaps 16(%rdi), %xmm0
; X64-SSE-NEXT:    movaps 32(%rdi), %xmm1
; X64-SSE-NEXT:    retq
;
; X64-AVX-LABEL: load_v16f32_v8f32_ofs4:
; X64-AVX:       # %bb.0:
; X64-AVX-NEXT:    vmovaps (%rdi), %ymm0
; X64-AVX-NEXT:    vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],mem[0,1]
; X64-AVX-NEXT:    retq
  %ld = load <16 x float>, ptr %val
  %sub = shufflevector <16 x float> %ld, <16 x float> poison, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>
  ret <8 x float> %sub
}

define <2 x float> @load_v4f32_v2f32_ofs0(ptr %val) nounwind {
; X86-SSE-LABEL: load_v4f32_v2f32_ofs0:
; X86-SSE:       # %bb.0:
; X86-SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT:    movaps (%eax), %xmm0
; X86-SSE-NEXT:    retl
;
; X64-SSE-LABEL: load_v4f32_v2f32_ofs0:
; X64-SSE:       # %bb.0:
; X64-SSE-NEXT:    movaps (%rdi), %xmm0
; X64-SSE-NEXT:    retq
;
; X64-AVX-LABEL: load_v4f32_v2f32_ofs0:
; X64-AVX:       # %bb.0:
; X64-AVX-NEXT:    vmovaps (%rdi), %xmm0
; X64-AVX-NEXT:    retq
  %ld = load <4 x float>, ptr %val
  %sub = shufflevector <4 x float> %ld, <4 x float> poison, <2 x i32> <i32 0, i32 1>
  ret <2 x float> %sub
}

define <2 x float> @load_v4f32_v2f32_ofs1(ptr %val) nounwind {
; X86-SSE-LABEL: load_v4f32_v2f32_ofs1:
; X86-SSE:       # %bb.0:
; X86-SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT:    movaps (%eax), %xmm0
; X86-SSE-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,2,2,3]
; X86-SSE-NEXT:    retl
;
; X64-SSE-LABEL: load_v4f32_v2f32_ofs1:
; X64-SSE:       # %bb.0:
; X64-SSE-NEXT:    movaps (%rdi), %xmm0
; X64-SSE-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,2,2,3]
; X64-SSE-NEXT:    retq
;
; X64-AVX-LABEL: load_v4f32_v2f32_ofs1:
; X64-AVX:       # %bb.0:
; X64-AVX-NEXT:    vpermilps {{.*#+}} xmm0 = mem[1,2,2,3]
; X64-AVX-NEXT:    retq
  %ld = load <4 x float>, ptr %val
  %sub = shufflevector <4 x float> %ld, <4 x float> poison, <2 x i32> <i32 1, i32 2>
  ret <2 x float> %sub
}

define <4 x i32> @load_v8i32_v4i32_ofs4_freeze(ptr %val) nounwind {
; X86-SSE-LABEL: load_v8i32_v4i32_ofs4_freeze:
; X86-SSE:       # %bb.0:
; X86-SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT:    movaps 16(%eax), %xmm0
; X86-SSE-NEXT:    retl
;
; X64-SSE-LABEL: load_v8i32_v4i32_ofs4_freeze:
; X64-SSE:       # %bb.0:
; X64-SSE-NEXT:    movaps 16(%rdi), %xmm0
; X64-SSE-NEXT:    retq
;
; X64-AVX-LABEL: load_v8i32_v4i32_ofs4_freeze:
; X64-AVX:       # %bb.0:
; X64-AVX-NEXT:    vmovaps 16(%rdi), %xmm0
; X64-AVX-NEXT:    retq
  %ld = load <8 x i32>, ptr %val
  %fr = freeze <8 x i32> %ld
  %sub = shufflevector <8 x i32> %fr, <8 x i32> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
  ret <4 x i32> %sub
}

define <4 x double> @load_v8f64_v4f64_ofs0_freeze(ptr %val) nounwind {
; X86-SSE-LABEL: load_v8f64_v4f64_ofs0_freeze:
; X86-SSE:       # %bb.0:
; X86-SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT:    movaps (%eax), %xmm0
; X86-SSE-NEXT:    movaps 16(%eax), %xmm1
; X86-SSE-NEXT:    retl
;
; X64-SSE-LABEL: load_v8f64_v4f64_ofs0_freeze:
; X64-SSE:       # %bb.0:
; X64-SSE-NEXT:    movaps (%rdi), %xmm0
; X64-SSE-NEXT:    movaps 16(%rdi), %xmm1
; X64-SSE-NEXT:    retq
;
; X64-AVX-LABEL: load_v8f64_v4f64_ofs0_freeze:
; X64-AVX:       # %bb.0:
; X64-AVX-NEXT:    vmovaps (%rdi), %ymm0
; X64-AVX-NEXT:    retq
  %ld = load <8 x double>, ptr %val
  %fr = freeze <8 x double> %ld
  %sub = shufflevector <8 x double> %fr, <8 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  ret <4 x double> %sub
}

define <16 x i8> @load_v32i8_v16i8_ofs0_freeze_multiuse(ptr %val) nounwind {
; X86-SSE-LABEL: load_v32i8_v16i8_ofs0_freeze_multiuse:
; X86-SSE:       # %bb.0:
; X86-SSE-NEXT:    subl $16, %esp
; X86-SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT:    movaps (%eax), %xmm0
; X86-SSE-NEXT:    movups %xmm0, (%esp) # 16-byte Spill
; X86-SSE-NEXT:    movaps 16(%eax), %xmm1
; X86-SSE-NEXT:    calll use_v32i8@PLT
; X86-SSE-NEXT:    movups (%esp), %xmm0 # 16-byte Reload
; X86-SSE-NEXT:    addl $16, %esp
; X86-SSE-NEXT:    retl
;
; X64-SSE-LABEL: load_v32i8_v16i8_ofs0_freeze_multiuse:
; X64-SSE:       # %bb.0:
; X64-SSE-NEXT:    subq $24, %rsp
; X64-SSE-NEXT:    movaps (%rdi), %xmm0
; X64-SSE-NEXT:    movaps %xmm0, (%rsp) # 16-byte Spill
; X64-SSE-NEXT:    movaps 16(%rdi), %xmm1
; X64-SSE-NEXT:    callq use_v32i8@PLT
; X64-SSE-NEXT:    movaps (%rsp), %xmm0 # 16-byte Reload
; X64-SSE-NEXT:    addq $24, %rsp
; X64-SSE-NEXT:    retq
;
; X64-AVX-LABEL: load_v32i8_v16i8_ofs0_freeze_multiuse:
; X64-AVX:       # %bb.0:
; X64-AVX-NEXT:    subq $40, %rsp
; X64-AVX-NEXT:    vmovaps (%rdi), %ymm0
; X64-AVX-NEXT:    vmovups %ymm0, (%rsp) # 32-byte Spill
; X64-AVX-NEXT:    callq use_v32i8@PLT
; X64-AVX-NEXT:    vmovups (%rsp), %ymm0 # 32-byte Reload
; X64-AVX-NEXT:    # kill: def $xmm0 killed $xmm0 killed $ymm0
; X64-AVX-NEXT:    addq $40, %rsp
; X64-AVX-NEXT:    vzeroupper
; X64-AVX-NEXT:    retq
  %ld = load <32 x i8>, ptr %val
  %fr = freeze <32 x i8> %ld
  %sub = shufflevector <32 x i8> %fr, <32 x i8> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
  call void @use_v32i8(<32 x i8> %fr)
  ret <16 x i8> %sub
}
declare void @use_v32i8(<32 x i8>)