llvm/test/CodeGen/SystemZ/vec-move-25.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
;
; Test that zero extension is not made after a vector element extraction.

define i16 @fun0(<16 x i8> %Arg) {
; CHECK-LABEL: fun0:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vlgvb %r2, %v24, 0
; CHECK-NEXT:    # kill: def $r2l killed $r2l killed $r2d
; CHECK-NEXT:    br %r14
  %Elt = extractelement <16 x i8> %Arg, i32 0
  %Ext = zext i8 %Elt to i16
  ret i16 %Ext
}

define i32 @fun1(<16 x i8> %Arg) {
; CHECK-LABEL: fun1:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vlgvb %r2, %v24, 0
; CHECK-NEXT:    # kill: def $r2l killed $r2l killed $r2d
; CHECK-NEXT:    br %r14
  %Elt = extractelement <16 x i8> %Arg, i32 0
  %Ext = zext i8 %Elt to i32
  ret i32 %Ext
}

define i64 @fun2(<16 x i8> %Arg) {
; CHECK-LABEL: fun2:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vlgvb %r2, %v24, 0
; CHECK-NEXT:    br %r14
  %Elt = extractelement <16 x i8> %Arg, i32 0
  %Ext = zext i8 %Elt to i64
  ret i64 %Ext
}

define i128 @fun3(<16 x i8> %Arg) {
; CHECK-LABEL: fun3:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vlgvb %r0, %v24, 0
; CHECK-NEXT:    vgbm %v0, 0
; CHECK-NEXT:    vlvgb %v0, %r0, 15
; CHECK-NEXT:    vst %v0, 0(%r2), 3
; CHECK-NEXT:    br %r14
  %Elt = extractelement <16 x i8> %Arg, i32 0
  %Ext = zext i8 %Elt to i128
  ret i128 %Ext
}

define i32 @fun4(<8 x i16> %Arg) {
; CHECK-LABEL: fun4:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vlgvh %r2, %v24, 0
; CHECK-NEXT:    # kill: def $r2l killed $r2l killed $r2d
; CHECK-NEXT:    br %r14
  %Elt = extractelement <8 x i16> %Arg, i32 0
  %Ext = zext i16 %Elt to i32
  ret i32 %Ext
}

define i64 @fun5(<8 x i16> %Arg) {
; CHECK-LABEL: fun5:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vlgvh %r2, %v24, 0
; CHECK-NEXT:    br %r14
  %Elt = extractelement <8 x i16> %Arg, i32 0
  %Ext = zext i16 %Elt to i64
  ret i64 %Ext
}

define i128 @fun6(<8 x i16> %Arg) {
; CHECK-LABEL: fun6:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vlgvh %r0, %v24, 0
; CHECK-NEXT:    vgbm %v0, 0
; CHECK-NEXT:    vlvgh %v0, %r0, 7
; CHECK-NEXT:    vst %v0, 0(%r2), 3
; CHECK-NEXT:    br %r14
  %Elt = extractelement <8 x i16> %Arg, i32 0
  %Ext = zext i16 %Elt to i128
  ret i128 %Ext
}

define i64 @fun7(<4 x i32> %Arg) {
; CHECK-LABEL: fun7:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vlgvf %r2, %v24, 0
; CHECK-NEXT:    br %r14
  %Elt = extractelement <4 x i32> %Arg, i32 0
  %Ext = zext i32 %Elt to i64
  ret i64 %Ext
}

define i128 @fun8(<4 x i32> %Arg) {
; CHECK-LABEL: fun8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vuplhf %v0, %v24
; CHECK-NEXT:    vuplhg %v0, %v0
; CHECK-NEXT:    vst %v0, 0(%r2), 3
; CHECK-NEXT:    br %r14
  %Elt = extractelement <4 x i32> %Arg, i32 0
  %Ext = zext i32 %Elt to i128
  ret i128 %Ext
}

define i16 @fun9(<16 x i8> %Arg, i32 %index) {
; CHECK-LABEL: fun9:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vlgvb %r2, %v24, 0
; CHECK-NEXT:    # kill: def $r2l killed $r2l killed $r2d
; CHECK-NEXT:    br %r14
  %Elt = extractelement <16 x i8> %Arg, i32 0
  %Ext = zext i8 %Elt to i16
  ret i16 %Ext
}

define i32 @fun10(<16 x i8> %Arg, i32 %index) {
; CHECK-LABEL: fun10:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vlgvb %r2, %v24, 0
; CHECK-NEXT:    # kill: def $r2l killed $r2l killed $r2d
; CHECK-NEXT:    br %r14
  %Elt = extractelement <16 x i8> %Arg, i32 0
  %Ext = zext i8 %Elt to i32
  ret i32 %Ext
}

define i64 @fun11(<16 x i8> %Arg, i32 %index) {
; CHECK-LABEL: fun11:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vlgvb %r2, %v24, 0
; CHECK-NEXT:    br %r14
  %Elt = extractelement <16 x i8> %Arg, i32 0
  %Ext = zext i8 %Elt to i64
  ret i64 %Ext
}

define i128 @fun12(<16 x i8> %Arg, i32 %index) {
; CHECK-LABEL: fun12:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vlgvb %r0, %v24, 0
; CHECK-NEXT:    vgbm %v0, 0
; CHECK-NEXT:    vlvgb %v0, %r0, 15
; CHECK-NEXT:    vst %v0, 0(%r2), 3
; CHECK-NEXT:    br %r14
  %Elt = extractelement <16 x i8> %Arg, i32 0
  %Ext = zext i8 %Elt to i128
  ret i128 %Ext
}

define i32 @fun13(<8 x i16> %Arg, i32 %index) {
; CHECK-LABEL: fun13:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vlgvh %r2, %v24, 0
; CHECK-NEXT:    # kill: def $r2l killed $r2l killed $r2d
; CHECK-NEXT:    br %r14
  %Elt = extractelement <8 x i16> %Arg, i32 0
  %Ext = zext i16 %Elt to i32
  ret i32 %Ext
}

define i64 @fun14(<8 x i16> %Arg, i32 %index) {
; CHECK-LABEL: fun14:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vlgvh %r2, %v24, 0
; CHECK-NEXT:    br %r14
  %Elt = extractelement <8 x i16> %Arg, i32 0
  %Ext = zext i16 %Elt to i64
  ret i64 %Ext
}

define i128 @fun15(<8 x i16> %Arg, i32 %index) {
; CHECK-LABEL: fun15:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vlgvh %r0, %v24, 0
; CHECK-NEXT:    vgbm %v0, 0
; CHECK-NEXT:    vlvgh %v0, %r0, 7
; CHECK-NEXT:    vst %v0, 0(%r2), 3
; CHECK-NEXT:    br %r14
  %Elt = extractelement <8 x i16> %Arg, i32 0
  %Ext = zext i16 %Elt to i128
  ret i128 %Ext
}

define i64 @fun16(<4 x i32> %Arg, i32 %index) {
; CHECK-LABEL: fun16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vlgvf %r2, %v24, 0
; CHECK-NEXT:    br %r14
  %Elt = extractelement <4 x i32> %Arg, i32 0
  %Ext = zext i32 %Elt to i64
  ret i64 %Ext
}

define i128 @fun17(<4 x i32> %Arg, i32 %index) {
; CHECK-LABEL: fun17:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vuplhf %v0, %v24
; CHECK-NEXT:    vuplhg %v0, %v0
; CHECK-NEXT:    vst %v0, 0(%r2), 3
; CHECK-NEXT:    br %r14
  %Elt = extractelement <4 x i32> %Arg, i32 0
  %Ext = zext i32 %Elt to i128
  ret i128 %Ext
}