llvm/test/CodeGen/SystemZ/vec-abi-04.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
;
; Test handling of fp16 IR vector arguments for z10 (without vector support).

define <1 x half> @pass_half_1(<1 x half> %Dummy, <1 x half> %Arg) {
; CHECK-LABEL: pass_half_1:
; CHECK:       # %bb.0:
; CHECK-NEXT:    ler %f0, %f2
; CHECK-NEXT:    br %r14
  ret <1 x half> %Arg
}

define <4 x half> @pass_half_4(<1 x half> %Dummy, <4 x half> %Arg) {
; CHECK-LABEL: pass_half_4:
; CHECK:       # %bb.0:
; CHECK-NEXT:    lgh %r0, 166(%r15)
; CHECK-NEXT:    sllg %r0, %r0, 48
; CHECK-NEXT:    ldgr %f1, %r0
; CHECK-NEXT:    ler %f0, %f2
; CHECK-NEXT:    ler %f2, %f4
; CHECK-NEXT:    ler %f4, %f6
; CHECK-NEXT:    ler %f6, %f1
; CHECK-NEXT:    br %r14
  ret <4 x half> %Arg
}

define <8 x half> @pass_half_8(<1 x half> %Dummy, <8 x half> %Arg) {
; CHECK-LABEL: pass_half_8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    lgh %r0, 166(%r15)
; CHECK-NEXT:    # kill: def $f6h killed $f6h def $f6d
; CHECK-NEXT:    # kill: def $f4h killed $f4h def $f4d
; CHECK-NEXT:    # kill: def $f2h killed $f2h def $f2d
; CHECK-NEXT:    lgh %r1, 174(%r15)
; CHECK-NEXT:    sllg %r0, %r0, 48
; CHECK-NEXT:    ldgr %f0, %r0
; CHECK-NEXT:    lgh %r0, 182(%r15)
; CHECK-NEXT:    sllg %r1, %r1, 48
; CHECK-NEXT:    ldgr %f1, %r1
; CHECK-NEXT:    lgh %r1, 190(%r15)
; CHECK-NEXT:    sllg %r0, %r0, 48
; CHECK-NEXT:    lgh %r3, 198(%r15)
; CHECK-NEXT:    ldgr %f3, %r0
; CHECK-NEXT:    sllg %r0, %r1, 48
; CHECK-NEXT:    ldgr %f5, %r0
; CHECK-NEXT:    sllg %r0, %r3, 48
; CHECK-NEXT:    ldgr %f7, %r0
; CHECK-NEXT:    lgdr %r0, %f6
; CHECK-NEXT:    srlg %r0, %r0, 48
; CHECK-NEXT:    sth %r0, 4(%r2)
; CHECK-NEXT:    lgdr %r0, %f4
; CHECK-NEXT:    srlg %r0, %r0, 48
; CHECK-NEXT:    sth %r0, 2(%r2)
; CHECK-NEXT:    lgdr %r0, %f2
; CHECK-NEXT:    srlg %r0, %r0, 48
; CHECK-NEXT:    sth %r0, 0(%r2)
; CHECK-NEXT:    lgdr %r0, %f7
; CHECK-NEXT:    srlg %r0, %r0, 48
; CHECK-NEXT:    sth %r0, 14(%r2)
; CHECK-NEXT:    lgdr %r0, %f5
; CHECK-NEXT:    srlg %r0, %r0, 48
; CHECK-NEXT:    sth %r0, 12(%r2)
; CHECK-NEXT:    lgdr %r0, %f3
; CHECK-NEXT:    srlg %r0, %r0, 48
; CHECK-NEXT:    sth %r0, 10(%r2)
; CHECK-NEXT:    lgdr %r0, %f1
; CHECK-NEXT:    srlg %r0, %r0, 48
; CHECK-NEXT:    sth %r0, 8(%r2)
; CHECK-NEXT:    lgdr %r0, %f0
; CHECK-NEXT:    srlg %r0, %r0, 48
; CHECK-NEXT:    sth %r0, 6(%r2)
; CHECK-NEXT:    br %r14
  ret <8 x half> %Arg
}

define <16 x half> @pass_half_16(<1 x half> %Dummy, <16 x half> %Arg) {
; CHECK-LABEL: pass_half_16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    aghi %r15, -64
; CHECK-NEXT:    .cfi_def_cfa_offset 224
; CHECK-NEXT:    std %f8, 56(%r15) # 8-byte Spill
; CHECK-NEXT:    std %f9, 48(%r15) # 8-byte Spill
; CHECK-NEXT:    std %f10, 40(%r15) # 8-byte Spill
; CHECK-NEXT:    std %f11, 32(%r15) # 8-byte Spill
; CHECK-NEXT:    std %f12, 24(%r15) # 8-byte Spill
; CHECK-NEXT:    std %f13, 16(%r15) # 8-byte Spill
; CHECK-NEXT:    std %f14, 8(%r15) # 8-byte Spill
; CHECK-NEXT:    std %f15, 0(%r15) # 8-byte Spill
; CHECK-NEXT:    .cfi_offset %f8, -168
; CHECK-NEXT:    .cfi_offset %f9, -176
; CHECK-NEXT:    .cfi_offset %f10, -184
; CHECK-NEXT:    .cfi_offset %f11, -192
; CHECK-NEXT:    .cfi_offset %f12, -200
; CHECK-NEXT:    .cfi_offset %f13, -208
; CHECK-NEXT:    .cfi_offset %f14, -216
; CHECK-NEXT:    .cfi_offset %f15, -224
; CHECK-NEXT:    lgh %r0, 230(%r15)
; CHECK-NEXT:    # kill: def $f6h killed $f6h def $f6d
; CHECK-NEXT:    # kill: def $f4h killed $f4h def $f4d
; CHECK-NEXT:    # kill: def $f2h killed $f2h def $f2d
; CHECK-NEXT:    lgh %r1, 238(%r15)
; CHECK-NEXT:    sllg %r0, %r0, 48
; CHECK-NEXT:    ldgr %f0, %r0
; CHECK-NEXT:    lgh %r0, 246(%r15)
; CHECK-NEXT:    sllg %r1, %r1, 48
; CHECK-NEXT:    ldgr %f1, %r1
; CHECK-NEXT:    lgh %r1, 254(%r15)
; CHECK-NEXT:    sllg %r0, %r0, 48
; CHECK-NEXT:    ldgr %f3, %r0
; CHECK-NEXT:    lgh %r0, 262(%r15)
; CHECK-NEXT:    sllg %r1, %r1, 48
; CHECK-NEXT:    ldgr %f5, %r1
; CHECK-NEXT:    lgh %r1, 270(%r15)
; CHECK-NEXT:    sllg %r0, %r0, 48
; CHECK-NEXT:    ldgr %f7, %r0
; CHECK-NEXT:    lgh %r0, 278(%r15)
; CHECK-NEXT:    sllg %r1, %r1, 48
; CHECK-NEXT:    ldgr %f8, %r1
; CHECK-NEXT:    lgh %r1, 286(%r15)
; CHECK-NEXT:    sllg %r0, %r0, 48
; CHECK-NEXT:    ldgr %f9, %r0
; CHECK-NEXT:    lgh %r0, 294(%r15)
; CHECK-NEXT:    sllg %r1, %r1, 48
; CHECK-NEXT:    ldgr %f10, %r1
; CHECK-NEXT:    lgh %r1, 302(%r15)
; CHECK-NEXT:    sllg %r0, %r0, 48
; CHECK-NEXT:    ldgr %f11, %r0
; CHECK-NEXT:    lgh %r0, 310(%r15)
; CHECK-NEXT:    sllg %r1, %r1, 48
; CHECK-NEXT:    ldgr %f12, %r1
; CHECK-NEXT:    lgh %r1, 318(%r15)
; CHECK-NEXT:    sllg %r0, %r0, 48
; CHECK-NEXT:    lgh %r3, 326(%r15)
; CHECK-NEXT:    ldgr %f13, %r0
; CHECK-NEXT:    sllg %r0, %r1, 48
; CHECK-NEXT:    ldgr %f14, %r0
; CHECK-NEXT:    sllg %r0, %r3, 48
; CHECK-NEXT:    ldgr %f15, %r0
; CHECK-NEXT:    lgdr %r0, %f6
; CHECK-NEXT:    srlg %r0, %r0, 48
; CHECK-NEXT:    sth %r0, 4(%r2)
; CHECK-NEXT:    lgdr %r0, %f4
; CHECK-NEXT:    srlg %r0, %r0, 48
; CHECK-NEXT:    sth %r0, 2(%r2)
; CHECK-NEXT:    lgdr %r0, %f2
; CHECK-NEXT:    srlg %r0, %r0, 48
; CHECK-NEXT:    sth %r0, 0(%r2)
; CHECK-NEXT:    lgdr %r0, %f15
; CHECK-NEXT:    srlg %r0, %r0, 48
; CHECK-NEXT:    sth %r0, 30(%r2)
; CHECK-NEXT:    lgdr %r0, %f14
; CHECK-NEXT:    srlg %r0, %r0, 48
; CHECK-NEXT:    sth %r0, 28(%r2)
; CHECK-NEXT:    lgdr %r0, %f13
; CHECK-NEXT:    srlg %r0, %r0, 48
; CHECK-NEXT:    sth %r0, 26(%r2)
; CHECK-NEXT:    lgdr %r0, %f12
; CHECK-NEXT:    srlg %r0, %r0, 48
; CHECK-NEXT:    sth %r0, 24(%r2)
; CHECK-NEXT:    lgdr %r0, %f11
; CHECK-NEXT:    srlg %r0, %r0, 48
; CHECK-NEXT:    sth %r0, 22(%r2)
; CHECK-NEXT:    lgdr %r0, %f10
; CHECK-NEXT:    srlg %r0, %r0, 48
; CHECK-NEXT:    sth %r0, 20(%r2)
; CHECK-NEXT:    lgdr %r0, %f9
; CHECK-NEXT:    srlg %r0, %r0, 48
; CHECK-NEXT:    sth %r0, 18(%r2)
; CHECK-NEXT:    lgdr %r0, %f8
; CHECK-NEXT:    srlg %r0, %r0, 48
; CHECK-NEXT:    sth %r0, 16(%r2)
; CHECK-NEXT:    lgdr %r0, %f7
; CHECK-NEXT:    srlg %r0, %r0, 48
; CHECK-NEXT:    sth %r0, 14(%r2)
; CHECK-NEXT:    lgdr %r0, %f5
; CHECK-NEXT:    srlg %r0, %r0, 48
; CHECK-NEXT:    sth %r0, 12(%r2)
; CHECK-NEXT:    lgdr %r0, %f3
; CHECK-NEXT:    srlg %r0, %r0, 48
; CHECK-NEXT:    sth %r0, 10(%r2)
; CHECK-NEXT:    lgdr %r0, %f1
; CHECK-NEXT:    srlg %r0, %r0, 48
; CHECK-NEXT:    sth %r0, 8(%r2)
; CHECK-NEXT:    lgdr %r0, %f0
; CHECK-NEXT:    srlg %r0, %r0, 48
; CHECK-NEXT:    sth %r0, 6(%r2)
; CHECK-NEXT:    ld %f8, 56(%r15) # 8-byte Reload
; CHECK-NEXT:    ld %f9, 48(%r15) # 8-byte Reload
; CHECK-NEXT:    ld %f10, 40(%r15) # 8-byte Reload
; CHECK-NEXT:    ld %f11, 32(%r15) # 8-byte Reload
; CHECK-NEXT:    ld %f12, 24(%r15) # 8-byte Reload
; CHECK-NEXT:    ld %f13, 16(%r15) # 8-byte Reload
; CHECK-NEXT:    ld %f14, 8(%r15) # 8-byte Reload
; CHECK-NEXT:    ld %f15, 0(%r15) # 8-byte Reload
; CHECK-NEXT:    aghi %r15, 64
; CHECK-NEXT:    br %r14
  ret <16 x half> %Arg
}

define <24 x half> @pass_half_24(<1 x half> %Dummy, <24 x half> %Arg) {
; CHECK-LABEL: pass_half_24:
; CHECK:       # %bb.0:
; CHECK-NEXT:    stmg %r7, %r15, 56(%r15)
; CHECK-NEXT:    .cfi_offset %r7, -104
; CHECK-NEXT:    .cfi_offset %r8, -96
; CHECK-NEXT:    .cfi_offset %r9, -88
; CHECK-NEXT:    .cfi_offset %r10, -80
; CHECK-NEXT:    .cfi_offset %r11, -72
; CHECK-NEXT:    .cfi_offset %r12, -64
; CHECK-NEXT:    .cfi_offset %r13, -56
; CHECK-NEXT:    .cfi_offset %r14, -48
; CHECK-NEXT:    .cfi_offset %r15, -40
; CHECK-NEXT:    lgh %r0, 198(%r15)
; CHECK-NEXT:    # kill: def $f6h killed $f6h def $f6d
; CHECK-NEXT:    # kill: def $f4h killed $f4h def $f4d
; CHECK-NEXT:    # kill: def $f2h killed $f2h def $f2d
; CHECK-NEXT:    sllg %r0, %r0, 48
; CHECK-NEXT:    lgh %r1, 190(%r15)
; CHECK-NEXT:    ldgr %f0, %r0
; CHECK-NEXT:    lgdr %r0, %f0
; CHECK-NEXT:    srlg %r0, %r0, 48
; CHECK-NEXT:    sllg %r1, %r1, 48
; CHECK-NEXT:    lgh %r3, 182(%r15)
; CHECK-NEXT:    ldgr %f0, %r1
; CHECK-NEXT:    lgdr %r1, %f0
; CHECK-NEXT:    rosbg %r0, %r1, 32, 47, 32
; CHECK-NEXT:    sllg %r1, %r3, 48
; CHECK-NEXT:    lgh %r3, 174(%r15)
; CHECK-NEXT:    ldgr %f0, %r1
; CHECK-NEXT:    lgdr %r1, %f0
; CHECK-NEXT:    srlg %r1, %r1, 48
; CHECK-NEXT:    sllg %r3, %r3, 48
; CHECK-NEXT:    lgh %r4, 230(%r15)
; CHECK-NEXT:    ldgr %f0, %r3
; CHECK-NEXT:    lgdr %r3, %f0
; CHECK-NEXT:    rosbg %r1, %r3, 32, 47, 32
; CHECK-NEXT:    sllg %r3, %r4, 48
; CHECK-NEXT:    lgh %r4, 222(%r15)
; CHECK-NEXT:    ldgr %f0, %r3
; CHECK-NEXT:    lgdr %r3, %f0
; CHECK-NEXT:    srlg %r3, %r3, 48
; CHECK-NEXT:    sllg %r4, %r4, 48
; CHECK-NEXT:    lgh %r5, 214(%r15)
; CHECK-NEXT:    ldgr %f0, %r4
; CHECK-NEXT:    lgdr %r4, %f0
; CHECK-NEXT:    rosbg %r3, %r4, 32, 47, 32
; CHECK-NEXT:    sllg %r4, %r5, 48
; CHECK-NEXT:    lgh %r5, 206(%r15)
; CHECK-NEXT:    ldgr %f0, %r4
; CHECK-NEXT:    lgdr %r4, %f0
; CHECK-NEXT:    srlg %r4, %r4, 48
; CHECK-NEXT:    sllg %r5, %r5, 48
; CHECK-NEXT:    lgh %r14, 262(%r15)
; CHECK-NEXT:    ldgr %f0, %r5
; CHECK-NEXT:    lgdr %r5, %f0
; CHECK-NEXT:    rosbg %r4, %r5, 32, 47, 32
; CHECK-NEXT:    sllg %r5, %r14, 48
; CHECK-NEXT:    lgh %r14, 254(%r15)
; CHECK-NEXT:    ldgr %f0, %r5
; CHECK-NEXT:    lgdr %r5, %f0
; CHECK-NEXT:    srlg %r5, %r5, 48
; CHECK-NEXT:    sllg %r14, %r14, 48
; CHECK-NEXT:    lgh %r13, 246(%r15)
; CHECK-NEXT:    ldgr %f0, %r14
; CHECK-NEXT:    lgdr %r14, %f0
; CHECK-NEXT:    rosbg %r5, %r14, 32, 47, 32
; CHECK-NEXT:    sllg %r14, %r13, 48
; CHECK-NEXT:    lgh %r13, 238(%r15)
; CHECK-NEXT:    ldgr %f0, %r14
; CHECK-NEXT:    lgdr %r14, %f0
; CHECK-NEXT:    srlg %r14, %r14, 48
; CHECK-NEXT:    sllg %r13, %r13, 48
; CHECK-NEXT:    lgh %r12, 294(%r15)
; CHECK-NEXT:    ldgr %f0, %r13
; CHECK-NEXT:    lgdr %r13, %f0
; CHECK-NEXT:    rosbg %r14, %r13, 32, 47, 32
; CHECK-NEXT:    sllg %r13, %r12, 48
; CHECK-NEXT:    lgh %r12, 286(%r15)
; CHECK-NEXT:    ldgr %f0, %r13
; CHECK-NEXT:    lgdr %r13, %f0
; CHECK-NEXT:    srlg %r13, %r13, 48
; CHECK-NEXT:    sllg %r12, %r12, 48
; CHECK-NEXT:    lgh %r11, 278(%r15)
; CHECK-NEXT:    ldgr %f0, %r12
; CHECK-NEXT:    lgdr %r12, %f0
; CHECK-NEXT:    rosbg %r13, %r12, 32, 47, 32
; CHECK-NEXT:    sllg %r12, %r11, 48
; CHECK-NEXT:    lgh %r11, 270(%r15)
; CHECK-NEXT:    ldgr %f0, %r12
; CHECK-NEXT:    lgdr %r12, %f0
; CHECK-NEXT:    srlg %r12, %r12, 48
; CHECK-NEXT:    sllg %r11, %r11, 48
; CHECK-NEXT:    lgh %r10, 326(%r15)
; CHECK-NEXT:    ldgr %f0, %r11
; CHECK-NEXT:    lgdr %r11, %f0
; CHECK-NEXT:    rosbg %r12, %r11, 32, 47, 32
; CHECK-NEXT:    sllg %r11, %r10, 48
; CHECK-NEXT:    lgh %r10, 318(%r15)
; CHECK-NEXT:    ldgr %f0, %r11
; CHECK-NEXT:    lgdr %r11, %f0
; CHECK-NEXT:    srlg %r11, %r11, 48
; CHECK-NEXT:    sllg %r10, %r10, 48
; CHECK-NEXT:    lgh %r9, 310(%r15)
; CHECK-NEXT:    ldgr %f0, %r10
; CHECK-NEXT:    lgdr %r10, %f0
; CHECK-NEXT:    rosbg %r11, %r10, 32, 47, 32
; CHECK-NEXT:    sllg %r10, %r9, 48
; CHECK-NEXT:    lgh %r9, 302(%r15)
; CHECK-NEXT:    ldgr %f0, %r10
; CHECK-NEXT:    lgdr %r10, %f0
; CHECK-NEXT:    srlg %r10, %r10, 48
; CHECK-NEXT:    sllg %r9, %r9, 48
; CHECK-NEXT:    ldgr %f0, %r9
; CHECK-NEXT:    lgdr %r9, %f0
; CHECK-NEXT:    rosbg %r10, %r9, 32, 47, 32
; CHECK-NEXT:    lgdr %r9, %f4
; CHECK-NEXT:    lgh %r8, 166(%r15)
; CHECK-NEXT:    srlg %r9, %r9, 48
; CHECK-NEXT:    lgdr %r7, %f2
; CHECK-NEXT:    rosbg %r9, %r7, 32, 47, 32
; CHECK-NEXT:    sllg %r8, %r8, 48
; CHECK-NEXT:    ldgr %f0, %r8
; CHECK-NEXT:    lgdr %r8, %f0
; CHECK-NEXT:    srlg %r8, %r8, 48
; CHECK-NEXT:    lgdr %r7, %f6
; CHECK-NEXT:    rosbg %r8, %r7, 32, 47, 32
; CHECK-NEXT:    sllg %r1, %r1, 32
; CHECK-NEXT:    sllg %r4, %r4, 32
; CHECK-NEXT:    sllg %r14, %r14, 32
; CHECK-NEXT:    sllg %r12, %r12, 32
; CHECK-NEXT:    sllg %r10, %r10, 32
; CHECK-NEXT:    sllg %r9, %r9, 32
; CHECK-NEXT:    lr %r1, %r0
; CHECK-NEXT:    lr %r4, %r3
; CHECK-NEXT:    lr %r14, %r5
; CHECK-NEXT:    lr %r12, %r13
; CHECK-NEXT:    lr %r10, %r11
; CHECK-NEXT:    lr %r9, %r8
; CHECK-NEXT:    stg %r9, 0(%r2)
; CHECK-NEXT:    stg %r10, 40(%r2)
; CHECK-NEXT:    stg %r12, 32(%r2)
; CHECK-NEXT:    stg %r14, 24(%r2)
; CHECK-NEXT:    stg %r4, 16(%r2)
; CHECK-NEXT:    stg %r1, 8(%r2)
; CHECK-NEXT:    lmg %r7, %r15, 56(%r15)
; CHECK-NEXT:    br %r14
  ret <24 x half> %Arg
}