llvm/test/CodeGen/SystemZ/fp-half-vector-move.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z16 | FileCheck %s --check-prefix=VECTOR
;
; Test insertions into fp16 vectors.

define <8 x half> @f0(half %val) {
; CHECK-LABEL: f0:
; CHECK:       # %bb.0:
; CHECK-NEXT:    # kill: def $f0h killed $f0h def $f0d
; CHECK-NEXT:    lgdr %r0, %f0
; CHECK-NEXT:    srlg %r0, %r0, 48
; CHECK-NEXT:    sth %r0, 4(%r2)
; CHECK-NEXT:    br %r14
;
; VECTOR-LABEL: f0:
; VECTOR:       # %bb.0:
; VECTOR-NEXT:    # kill: def $f0h killed $f0h def $v0
; VECTOR-NEXT:    vreph %v24, %v0, 0
; VECTOR-NEXT:    br %r14
  %ret = insertelement <8 x half> poison, half %val, i32 2
  ret <8 x half> %ret
}

define <8 x half> @f1(half %val) {
; CHECK-LABEL: f1:
; CHECK:       # %bb.0:
; CHECK-NEXT:    # kill: def $f0h killed $f0h def $f0d
; CHECK-NEXT:    lgdr %r0, %f0
; CHECK-NEXT:    srlg %r0, %r0, 48
; CHECK-NEXT:    sth %r0, 6(%r2)
; CHECK-NEXT:    sth %r0, 4(%r2)
; CHECK-NEXT:    br %r14
;
; VECTOR-LABEL: f1:
; VECTOR:       # %bb.0:
; VECTOR-NEXT:    # kill: def $f0h killed $f0h def $v0
; VECTOR-NEXT:    vreph %v24, %v0, 0
; VECTOR-NEXT:    br %r14
  %v0 = insertelement <8 x half> poison, half %val, i32 2
  %ret = insertelement <8 x half> %v0, half %val, i32 3
  ret <8 x half> %ret
}

define <8 x half> @f2(half %val0, half %val1) {
; CHECK-LABEL: f2:
; CHECK:       # %bb.0:
; CHECK-NEXT:    # kill: def $f2h killed $f2h def $f2d
; CHECK-NEXT:    # kill: def $f0h killed $f0h def $f0d
; CHECK-NEXT:    lgdr %r0, %f2
; CHECK-NEXT:    srlg %r0, %r0, 48
; CHECK-NEXT:    sth %r0, 6(%r2)
; CHECK-NEXT:    lgdr %r0, %f0
; CHECK-NEXT:    srlg %r0, %r0, 48
; CHECK-NEXT:    sth %r0, 4(%r2)
; CHECK-NEXT:    br %r14
;
; VECTOR-LABEL: f2:
; VECTOR:       # %bb.0:
; VECTOR-NEXT:    # kill: def $f2h killed $f2h def $v2
; VECTOR-NEXT:    # kill: def $f0h killed $f0h def $v0
; VECTOR-NEXT:    vmrhh %v0, %v0, %v2
; VECTOR-NEXT:    vmrhf %v0, %v0, %v0
; VECTOR-NEXT:    vmrhg %v24, %v0, %v0
; VECTOR-NEXT:    br %r14
  %v0 = insertelement <8 x half> poison, half %val0, i32 2
  %ret = insertelement <8 x half> %v0, half %val1, i32 3
  ret <8 x half> %ret
}

define <8 x half> @f3(half %val0, half %val1) {
; CHECK-LABEL: f3:
; CHECK:       # %bb.0:
; CHECK-NEXT:    # kill: def $f2h killed $f2h def $f2d
; CHECK-NEXT:    # kill: def $f0h killed $f0h def $f0d
; CHECK-NEXT:    lgdr %r0, %f2
; CHECK-NEXT:    srlg %r0, %r0, 48
; CHECK-NEXT:    sth %r0, 10(%r2)
; CHECK-NEXT:    lgdr %r1, %f0
; CHECK-NEXT:    srlg %r1, %r1, 48
; CHECK-NEXT:    sth %r1, 8(%r2)
; CHECK-NEXT:    sth %r0, 6(%r2)
; CHECK-NEXT:    sth %r1, 4(%r2)
; CHECK-NEXT:    br %r14
;
; VECTOR-LABEL: f3:
; VECTOR:       # %bb.0:
; VECTOR-NEXT:    # kill: def $f2h killed $f2h def $v2
; VECTOR-NEXT:    # kill: def $f0h killed $f0h def $v0
; VECTOR-NEXT:    vmrhh %v0, %v0, %v2
; VECTOR-NEXT:    vmrhf %v0, %v0, %v0
; VECTOR-NEXT:    vmrhg %v24, %v0, %v0
; VECTOR-NEXT:    br %r14
  %v0 = insertelement <8 x half> poison, half %val0, i32 2
  %v1 = insertelement <8 x half> %v0, half %val1, i32 3
  %v2 = insertelement <8 x half> %v1, half %val0, i32 4
  %ret = insertelement <8 x half> %v2, half %val1, i32 5
  ret <8 x half> %ret
}

; Test creation of vregs where the arg gets one VR128 which is split into two
; VR16 parts.
define <2 x half> @f4(<2 x half> %0) {
; CHECK-LABEL: f4:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    lzer %f0
; CHECK-NEXT:    br %r14
;
; VECTOR-LABEL: f4:
; VECTOR:       # %bb.0: # %entry
; VECTOR-NEXT:    vreph %v0, %v24, 1
; VECTOR-NEXT:    vuplhh %v0, %v0
; VECTOR-NEXT:    vmrhf %v0, %v0, %v0
; VECTOR-NEXT:    vmrhg %v24, %v0, %v0
; VECTOR-NEXT:    br %r14
entry:
  br label %body

body:                                         ; preds = %entry
  %2 = insertelement <2 x half> %0, half 0x0000, i64 0
  ret <2 x half> %2
}