llvm/test/CodeGen/RISCV/zilx.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -verify-machineinstrs \
; RUN:   | FileCheck -check-prefix=RV32 %s
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+experimental-zilx -verify-machineinstrs \
; RUN:   | FileCheck -check-prefix=RV32-ZILX %s
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zba -verify-machineinstrs \
; RUN:   | FileCheck -check-prefix=RV32-ZBA %s
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zba,+experimental-zilx -verify-machineinstrs \
; RUN:   | FileCheck -check-prefix=RV32-ZBA-ZILX %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -verify-machineinstrs \
; RUN:   | FileCheck -check-prefix=RV64 %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+experimental-zilx -verify-machineinstrs \
; RUN:   | FileCheck -check-prefix=RV64-ZILX %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zba -verify-machineinstrs \
; RUN:   | FileCheck -check-prefix=RV64-ZBA %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zba,+experimental-zilx -verify-machineinstrs \
; RUN:   | FileCheck -check-prefix=RV64-ZBA-ZILX %s

;------------------------------------------------------------------------------
; Unscaled indexed loads: address = base + index.
;------------------------------------------------------------------------------

define i16 @lxh(ptr %a, iXLen %b) {
; RV32-LABEL: lxh:
; RV32:       # %bb.0:
; RV32-NEXT:    add a0, a0, a1
; RV32-NEXT:    lh a0, 0(a0)
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxh:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    lxh a0, (a0), a1
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxh:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    add a0, a0, a1
; RV32-ZBA-NEXT:    lh a0, 0(a0)
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxh:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    lxh a0, (a0), a1
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxh:
; RV64:       # %bb.0:
; RV64-NEXT:    add a0, a0, a1
; RV64-NEXT:    lh a0, 0(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxh:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    lxh a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxh:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    add a0, a0, a1
; RV64-ZBA-NEXT:    lh a0, 0(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxh:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    lxh a0, (a0), a1
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = getelementptr i8, ptr %a, iXLen %b
  %2 = load i16, ptr %1, align 2
  ret i16 %2
}

define i32 @lxhu(ptr %a, iXLen %b) {
; RV32-LABEL: lxhu:
; RV32:       # %bb.0:
; RV32-NEXT:    add a0, a0, a1
; RV32-NEXT:    lhu a0, 0(a0)
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxhu:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    lxhu a0, (a0), a1
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxhu:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    add a0, a0, a1
; RV32-ZBA-NEXT:    lhu a0, 0(a0)
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxhu:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    lxhu a0, (a0), a1
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxhu:
; RV64:       # %bb.0:
; RV64-NEXT:    add a0, a0, a1
; RV64-NEXT:    lhu a0, 0(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxhu:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    lxhu a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxhu:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    add a0, a0, a1
; RV64-ZBA-NEXT:    lhu a0, 0(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxhu:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    lxhu a0, (a0), a1
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = getelementptr i8, ptr %a, iXLen %b
  %2 = load i16, ptr %1, align 2
  %3 = zext i16 %2 to i32
  ret i32 %3
}

define i32 @lxw(ptr %a, iXLen %b) {
; RV32-LABEL: lxw:
; RV32:       # %bb.0:
; RV32-NEXT:    add a0, a0, a1
; RV32-NEXT:    lw a0, 0(a0)
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxw:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    lxw a0, (a0), a1
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxw:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    add a0, a0, a1
; RV32-ZBA-NEXT:    lw a0, 0(a0)
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxw:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    lxw a0, (a0), a1
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxw:
; RV64:       # %bb.0:
; RV64-NEXT:    add a0, a0, a1
; RV64-NEXT:    lw a0, 0(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxw:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    lxw a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxw:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    add a0, a0, a1
; RV64-ZBA-NEXT:    lw a0, 0(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxw:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    lxw a0, (a0), a1
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = getelementptr i8, ptr %a, iXLen %b
  %2 = load i32, ptr %1, align 4
  ret i32 %2
}

define i64 @lxwu(ptr %a, iXLen %b) {
; RV32-LABEL: lxwu:
; RV32:       # %bb.0:
; RV32-NEXT:    add a0, a0, a1
; RV32-NEXT:    lw a0, 0(a0)
; RV32-NEXT:    li a1, 0
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxwu:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    lxw a0, (a0), a1
; RV32-ZILX-NEXT:    li a1, 0
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxwu:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    add a0, a0, a1
; RV32-ZBA-NEXT:    lw a0, 0(a0)
; RV32-ZBA-NEXT:    li a1, 0
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxwu:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    lxw a0, (a0), a1
; RV32-ZBA-ZILX-NEXT:    li a1, 0
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxwu:
; RV64:       # %bb.0:
; RV64-NEXT:    add a0, a0, a1
; RV64-NEXT:    lwu a0, 0(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxwu:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    lxwu a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxwu:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    add a0, a0, a1
; RV64-ZBA-NEXT:    lwu a0, 0(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxwu:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    lxwu a0, (a0), a1
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = getelementptr i8, ptr %a, iXLen %b
  %2 = load i32, ptr %1, align 4
  %3 = zext i32 %2 to i64
  ret i64 %3
}

define i64 @lxd(ptr %a, iXLen %b) {
; RV32-LABEL: lxd:
; RV32:       # %bb.0:
; RV32-NEXT:    add a1, a0, a1
; RV32-NEXT:    lw a0, 0(a1)
; RV32-NEXT:    lw a1, 4(a1)
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxd:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    add a1, a0, a1
; RV32-ZILX-NEXT:    lw a0, 0(a1)
; RV32-ZILX-NEXT:    lw a1, 4(a1)
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxd:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    add a1, a0, a1
; RV32-ZBA-NEXT:    lw a0, 0(a1)
; RV32-ZBA-NEXT:    lw a1, 4(a1)
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxd:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    add a1, a0, a1
; RV32-ZBA-ZILX-NEXT:    lw a0, 0(a1)
; RV32-ZBA-ZILX-NEXT:    lw a1, 4(a1)
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxd:
; RV64:       # %bb.0:
; RV64-NEXT:    add a0, a0, a1
; RV64-NEXT:    ld a0, 0(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxd:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    lxd a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxd:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    add a0, a0, a1
; RV64-ZBA-NEXT:    ld a0, 0(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxd:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    lxd a0, (a0), a1
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = getelementptr i8, ptr %a, iXLen %b
  %2 = load i64, ptr %1, align 8
  ret i64 %2
}

;------------------------------------------------------------------------------
; Scaled indexed loads: address = base + (index << log2(access-size)).
; Byte loads are provided only in scaled form (the byte scale factor is 1).
;------------------------------------------------------------------------------

define i8 @lxsb_anyext(ptr %a, iXLen %b) {
; RV32-LABEL: lxsb_anyext:
; RV32:       # %bb.0:
; RV32-NEXT:    add a0, a0, a1
; RV32-NEXT:    lbu a0, 0(a0)
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxsb_anyext:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    lxsb a0, (a0), a1
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxsb_anyext:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    add a0, a0, a1
; RV32-ZBA-NEXT:    lbu a0, 0(a0)
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxsb_anyext:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    lxsb a0, (a0), a1
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxsb_anyext:
; RV64:       # %bb.0:
; RV64-NEXT:    add a0, a0, a1
; RV64-NEXT:    lbu a0, 0(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxsb_anyext:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    lxsb a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxsb_anyext:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    add a0, a0, a1
; RV64-ZBA-NEXT:    lbu a0, 0(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxsb_anyext:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    lxsb a0, (a0), a1
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = getelementptr i8, ptr %a, iXLen %b
  %2 = load i8, ptr %1, align 1
  ret i8 %2
}

define i32 @lxsb(ptr %a, iXLen %b) {
; RV32-LABEL: lxsb:
; RV32:       # %bb.0:
; RV32-NEXT:    add a0, a0, a1
; RV32-NEXT:    lb a0, 0(a0)
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxsb:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    lxsb a0, (a0), a1
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxsb:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    add a0, a0, a1
; RV32-ZBA-NEXT:    lb a0, 0(a0)
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxsb:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    lxsb a0, (a0), a1
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxsb:
; RV64:       # %bb.0:
; RV64-NEXT:    add a0, a0, a1
; RV64-NEXT:    lb a0, 0(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxsb:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    lxsb a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxsb:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    add a0, a0, a1
; RV64-ZBA-NEXT:    lb a0, 0(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxsb:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    lxsb a0, (a0), a1
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = getelementptr i8, ptr %a, iXLen %b
  %2 = load i8, ptr %1, align 1
  %3 = sext i8 %2 to i32
  ret i32 %3
}

define i32 @lxsbu(ptr %a, iXLen %b) {
; RV32-LABEL: lxsbu:
; RV32:       # %bb.0:
; RV32-NEXT:    add a0, a0, a1
; RV32-NEXT:    lbu a0, 0(a0)
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxsbu:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    lxsbu a0, (a0), a1
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxsbu:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    add a0, a0, a1
; RV32-ZBA-NEXT:    lbu a0, 0(a0)
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxsbu:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    lxsbu a0, (a0), a1
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxsbu:
; RV64:       # %bb.0:
; RV64-NEXT:    add a0, a0, a1
; RV64-NEXT:    lbu a0, 0(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxsbu:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    lxsbu a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxsbu:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    add a0, a0, a1
; RV64-ZBA-NEXT:    lbu a0, 0(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxsbu:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    lxsbu a0, (a0), a1
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = getelementptr i8, ptr %a, iXLen %b
  %2 = load i8, ptr %1, align 1
  %3 = zext i8 %2 to i32
  ret i32 %3
}

define i16 @lxsh_anyext(ptr %a, iXLen %b) {
; RV32-LABEL: lxsh_anyext:
; RV32:       # %bb.0:
; RV32-NEXT:    slli a1, a1, 1
; RV32-NEXT:    add a0, a0, a1
; RV32-NEXT:    lh a0, 0(a0)
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxsh_anyext:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    lxsh a0, (a0), a1
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxsh_anyext:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    sh1add a0, a1, a0
; RV32-ZBA-NEXT:    lh a0, 0(a0)
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxsh_anyext:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    lxsh a0, (a0), a1
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxsh_anyext:
; RV64:       # %bb.0:
; RV64-NEXT:    slli a1, a1, 1
; RV64-NEXT:    add a0, a0, a1
; RV64-NEXT:    lh a0, 0(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxsh_anyext:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    lxsh a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxsh_anyext:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    sh1add a0, a1, a0
; RV64-ZBA-NEXT:    lh a0, 0(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxsh_anyext:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    lxsh a0, (a0), a1
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = getelementptr i16, ptr %a, iXLen %b
  %2 = load i16, ptr %1, align 2
  ret i16 %2
}

define i32 @lxsh(ptr %a, iXLen %b) {
; RV32-LABEL: lxsh:
; RV32:       # %bb.0:
; RV32-NEXT:    slli a1, a1, 1
; RV32-NEXT:    add a0, a0, a1
; RV32-NEXT:    lh a0, 0(a0)
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxsh:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    lxsh a0, (a0), a1
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxsh:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    sh1add a0, a1, a0
; RV32-ZBA-NEXT:    lh a0, 0(a0)
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxsh:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    lxsh a0, (a0), a1
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxsh:
; RV64:       # %bb.0:
; RV64-NEXT:    slli a1, a1, 1
; RV64-NEXT:    add a0, a0, a1
; RV64-NEXT:    lh a0, 0(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxsh:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    lxsh a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxsh:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    sh1add a0, a1, a0
; RV64-ZBA-NEXT:    lh a0, 0(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxsh:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    lxsh a0, (a0), a1
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = getelementptr i16, ptr %a, iXLen %b
  %2 = load i16, ptr %1, align 2
  %3 = sext i16 %2 to i32
  ret i32 %3
}

define i32 @lxshu(ptr %a, iXLen %b) {
; RV32-LABEL: lxshu:
; RV32:       # %bb.0:
; RV32-NEXT:    slli a1, a1, 1
; RV32-NEXT:    add a0, a0, a1
; RV32-NEXT:    lhu a0, 0(a0)
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxshu:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    lxshu a0, (a0), a1
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxshu:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    sh1add a0, a1, a0
; RV32-ZBA-NEXT:    lhu a0, 0(a0)
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxshu:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    lxshu a0, (a0), a1
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxshu:
; RV64:       # %bb.0:
; RV64-NEXT:    slli a1, a1, 1
; RV64-NEXT:    add a0, a0, a1
; RV64-NEXT:    lhu a0, 0(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxshu:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    lxshu a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxshu:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    sh1add a0, a1, a0
; RV64-ZBA-NEXT:    lhu a0, 0(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxshu:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    lxshu a0, (a0), a1
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = getelementptr i16, ptr %a, iXLen %b
  %2 = load i16, ptr %1, align 2
  %3 = zext i16 %2 to i32
  ret i32 %3
}

define i32 @lxsw_anyext(ptr %a, iXLen %b) {
; RV32-LABEL: lxsw_anyext:
; RV32:       # %bb.0:
; RV32-NEXT:    slli a1, a1, 2
; RV32-NEXT:    add a0, a0, a1
; RV32-NEXT:    lw a0, 0(a0)
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxsw_anyext:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    lxsw a0, (a0), a1
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxsw_anyext:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    sh2add a0, a1, a0
; RV32-ZBA-NEXT:    lw a0, 0(a0)
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxsw_anyext:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    lxsw a0, (a0), a1
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxsw_anyext:
; RV64:       # %bb.0:
; RV64-NEXT:    slli a1, a1, 2
; RV64-NEXT:    add a0, a0, a1
; RV64-NEXT:    lw a0, 0(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxsw_anyext:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    lxsw a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxsw_anyext:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    sh2add a0, a1, a0
; RV64-ZBA-NEXT:    lw a0, 0(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxsw_anyext:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    lxsw a0, (a0), a1
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = getelementptr i32, ptr %a, iXLen %b
  %2 = load i32, ptr %1, align 4
  ret i32 %2
}

define i64 @lxsw(ptr %a, iXLen %b) {
; RV32-LABEL: lxsw:
; RV32:       # %bb.0:
; RV32-NEXT:    slli a1, a1, 2
; RV32-NEXT:    add a0, a0, a1
; RV32-NEXT:    lw a0, 0(a0)
; RV32-NEXT:    srai a1, a0, 31
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxsw:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    lxsw a0, (a0), a1
; RV32-ZILX-NEXT:    srai a1, a0, 31
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxsw:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    sh2add a0, a1, a0
; RV32-ZBA-NEXT:    lw a0, 0(a0)
; RV32-ZBA-NEXT:    srai a1, a0, 31
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxsw:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    lxsw a0, (a0), a1
; RV32-ZBA-ZILX-NEXT:    srai a1, a0, 31
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxsw:
; RV64:       # %bb.0:
; RV64-NEXT:    slli a1, a1, 2
; RV64-NEXT:    add a0, a0, a1
; RV64-NEXT:    lw a0, 0(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxsw:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    lxsw a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxsw:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    sh2add a0, a1, a0
; RV64-ZBA-NEXT:    lw a0, 0(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxsw:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    lxsw a0, (a0), a1
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = getelementptr i32, ptr %a, iXLen %b
  %2 = load i32, ptr %1, align 4
  %3 = sext i32 %2 to i64
  ret i64 %3
}

define i64 @lxswu(ptr %a, iXLen %b) {
; RV32-LABEL: lxswu:
; RV32:       # %bb.0:
; RV32-NEXT:    slli a1, a1, 2
; RV32-NEXT:    add a0, a0, a1
; RV32-NEXT:    lw a0, 0(a0)
; RV32-NEXT:    li a1, 0
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxswu:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    lxsw a0, (a0), a1
; RV32-ZILX-NEXT:    li a1, 0
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxswu:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    sh2add a0, a1, a0
; RV32-ZBA-NEXT:    lw a0, 0(a0)
; RV32-ZBA-NEXT:    li a1, 0
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxswu:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    lxsw a0, (a0), a1
; RV32-ZBA-ZILX-NEXT:    li a1, 0
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxswu:
; RV64:       # %bb.0:
; RV64-NEXT:    slli a1, a1, 2
; RV64-NEXT:    add a0, a0, a1
; RV64-NEXT:    lwu a0, 0(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxswu:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    lxswu a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxswu:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    sh2add a0, a1, a0
; RV64-ZBA-NEXT:    lwu a0, 0(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxswu:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    lxswu a0, (a0), a1
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = getelementptr i32, ptr %a, iXLen %b
  %2 = load i32, ptr %1, align 4
  %3 = zext i32 %2 to i64
  ret i64 %3
}

define i64 @lxsd(ptr %a, iXLen %b) {
; RV32-LABEL: lxsd:
; RV32:       # %bb.0:
; RV32-NEXT:    slli a1, a1, 3
; RV32-NEXT:    add a1, a0, a1
; RV32-NEXT:    lw a0, 0(a1)
; RV32-NEXT:    lw a1, 4(a1)
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxsd:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    slli a1, a1, 3
; RV32-ZILX-NEXT:    add a1, a0, a1
; RV32-ZILX-NEXT:    lw a0, 0(a1)
; RV32-ZILX-NEXT:    lw a1, 4(a1)
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxsd:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    sh3add a1, a1, a0
; RV32-ZBA-NEXT:    lw a0, 0(a1)
; RV32-ZBA-NEXT:    lw a1, 4(a1)
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxsd:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    sh3add a1, a1, a0
; RV32-ZBA-ZILX-NEXT:    lw a0, 0(a1)
; RV32-ZBA-ZILX-NEXT:    lw a1, 4(a1)
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxsd:
; RV64:       # %bb.0:
; RV64-NEXT:    slli a1, a1, 3
; RV64-NEXT:    add a0, a0, a1
; RV64-NEXT:    ld a0, 0(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxsd:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    lxsd a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxsd:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    sh3add a0, a1, a0
; RV64-ZBA-NEXT:    ld a0, 0(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxsd:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    lxsd a0, (a0), a1
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = getelementptr i64, ptr %a, iXLen %b
  %2 = load i64, ptr %1, align 8
  ret i64 %2
}

define i64 @lxsd_disjoint(ptr %a, iXLen %b) {
; RV32-LABEL: lxsd_disjoint:
; RV32:       # %bb.0:
; RV32-NEXT:    slli a1, a1, 3
; RV32-NEXT:    add a1, a1, a0
; RV32-NEXT:    lw a0, 96(a1)
; RV32-NEXT:    lw a1, 100(a1)
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxsd_disjoint:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    slli a1, a1, 3
; RV32-ZILX-NEXT:    add a1, a1, a0
; RV32-ZILX-NEXT:    lw a0, 96(a1)
; RV32-ZILX-NEXT:    lw a1, 100(a1)
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxsd_disjoint:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    sh3add a1, a1, a0
; RV32-ZBA-NEXT:    lw a0, 96(a1)
; RV32-ZBA-NEXT:    lw a1, 100(a1)
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxsd_disjoint:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    sh3add a1, a1, a0
; RV32-ZBA-ZILX-NEXT:    lw a0, 96(a1)
; RV32-ZBA-ZILX-NEXT:    lw a1, 100(a1)
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxsd_disjoint:
; RV64:       # %bb.0:
; RV64-NEXT:    slli a1, a1, 3
; RV64-NEXT:    add a0, a1, a0
; RV64-NEXT:    ld a0, 96(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxsd_disjoint:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    addi a0, a0, 96
; RV64-ZILX-NEXT:    lxsd a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxsd_disjoint:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    sh3add a0, a1, a0
; RV64-ZBA-NEXT:    ld a0, 96(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxsd_disjoint:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    sh3add a0, a1, a0
; RV64-ZBA-ZILX-NEXT:    ld a0, 96(a0)
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = add iXLen %b, 12
  %2 = getelementptr i64, ptr %a, iXLen %1
  %3 = load i64, ptr %2, align 8
  ret i64 %3
}

;------------------------------------------------------------------------------
; Scaled indexed loads with a zero-extended 32-bit index (RV64-only):
; address = base + (zext32(index) << log2(access-size)).
;------------------------------------------------------------------------------

define i8 @lxsuwb_anyext(ptr %a, i32 %b) {
; RV32-LABEL: lxsuwb_anyext:
; RV32:       # %bb.0:
; RV32-NEXT:    add a0, a0, a1
; RV32-NEXT:    lbu a0, 0(a0)
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxsuwb_anyext:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    lxsb a0, (a0), a1
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxsuwb_anyext:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    add a0, a0, a1
; RV32-ZBA-NEXT:    lbu a0, 0(a0)
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxsuwb_anyext:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    lxsb a0, (a0), a1
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxsuwb_anyext:
; RV64:       # %bb.0:
; RV64-NEXT:    slli a1, a1, 32
; RV64-NEXT:    srli a1, a1, 32
; RV64-NEXT:    add a0, a0, a1
; RV64-NEXT:    lbu a0, 0(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxsuwb_anyext:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    lxsuwb a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxsuwb_anyext:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    add.uw a0, a1, a0
; RV64-ZBA-NEXT:    lbu a0, 0(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxsuwb_anyext:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    lxsuwb a0, (a0), a1
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = zext i32 %b to i64
  %2 = getelementptr i8, ptr %a, i64 %1
  %3 = load i8, ptr %2, align 1
  ret i8 %3
}

define i32 @lxsuwb(ptr %a, i32 %b) {
; RV32-LABEL: lxsuwb:
; RV32:       # %bb.0:
; RV32-NEXT:    add a0, a0, a1
; RV32-NEXT:    lb a0, 0(a0)
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxsuwb:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    lxsb a0, (a0), a1
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxsuwb:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    add a0, a0, a1
; RV32-ZBA-NEXT:    lb a0, 0(a0)
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxsuwb:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    lxsb a0, (a0), a1
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxsuwb:
; RV64:       # %bb.0:
; RV64-NEXT:    slli a1, a1, 32
; RV64-NEXT:    srli a1, a1, 32
; RV64-NEXT:    add a0, a0, a1
; RV64-NEXT:    lb a0, 0(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxsuwb:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    lxsuwb a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxsuwb:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    add.uw a0, a1, a0
; RV64-ZBA-NEXT:    lb a0, 0(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxsuwb:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    lxsuwb a0, (a0), a1
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = zext i32 %b to i64
  %2 = getelementptr i8, ptr %a, i64 %1
  %3 = load i8, ptr %2, align 1
  %4 = sext i8 %3 to i32
  ret i32 %4
}

define i32 @lxsuwbu(ptr %a, i32 %b) {
; RV32-LABEL: lxsuwbu:
; RV32:       # %bb.0:
; RV32-NEXT:    add a0, a0, a1
; RV32-NEXT:    lbu a0, 0(a0)
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxsuwbu:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    lxsbu a0, (a0), a1
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxsuwbu:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    add a0, a0, a1
; RV32-ZBA-NEXT:    lbu a0, 0(a0)
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxsuwbu:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    lxsbu a0, (a0), a1
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxsuwbu:
; RV64:       # %bb.0:
; RV64-NEXT:    slli a1, a1, 32
; RV64-NEXT:    srli a1, a1, 32
; RV64-NEXT:    add a0, a0, a1
; RV64-NEXT:    lbu a0, 0(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxsuwbu:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    lxsuwbu a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxsuwbu:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    add.uw a0, a1, a0
; RV64-ZBA-NEXT:    lbu a0, 0(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxsuwbu:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    lxsuwbu a0, (a0), a1
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = zext i32 %b to i64
  %2 = getelementptr i8, ptr %a, i64 %1
  %3 = load i8, ptr %2, align 1
  %4 = zext i8 %3 to i32
  ret i32 %4
}

define i16 @lxsuwh_anyext(ptr %a, i32 %b) {
; RV32-LABEL: lxsuwh_anyext:
; RV32:       # %bb.0:
; RV32-NEXT:    slli a1, a1, 1
; RV32-NEXT:    add a0, a0, a1
; RV32-NEXT:    lh a0, 0(a0)
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxsuwh_anyext:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    lxsh a0, (a0), a1
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxsuwh_anyext:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    sh1add a0, a1, a0
; RV32-ZBA-NEXT:    lh a0, 0(a0)
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxsuwh_anyext:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    lxsh a0, (a0), a1
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxsuwh_anyext:
; RV64:       # %bb.0:
; RV64-NEXT:    slli a1, a1, 32
; RV64-NEXT:    srli a1, a1, 31
; RV64-NEXT:    add a0, a0, a1
; RV64-NEXT:    lh a0, 0(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxsuwh_anyext:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    lxsuwh a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxsuwh_anyext:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    sh1add.uw a0, a1, a0
; RV64-ZBA-NEXT:    lh a0, 0(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxsuwh_anyext:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    lxsuwh a0, (a0), a1
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = zext i32 %b to i64
  %2 = getelementptr i16, ptr %a, i64 %1
  %3 = load i16, ptr %2, align 2
  ret i16 %3
}

define i32 @lxsuwh(ptr %a, i32 %b) {
; RV32-LABEL: lxsuwh:
; RV32:       # %bb.0:
; RV32-NEXT:    slli a1, a1, 1
; RV32-NEXT:    add a0, a0, a1
; RV32-NEXT:    lh a0, 0(a0)
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxsuwh:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    lxsh a0, (a0), a1
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxsuwh:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    sh1add a0, a1, a0
; RV32-ZBA-NEXT:    lh a0, 0(a0)
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxsuwh:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    lxsh a0, (a0), a1
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxsuwh:
; RV64:       # %bb.0:
; RV64-NEXT:    slli a1, a1, 32
; RV64-NEXT:    srli a1, a1, 31
; RV64-NEXT:    add a0, a0, a1
; RV64-NEXT:    lh a0, 0(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxsuwh:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    lxsuwh a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxsuwh:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    sh1add.uw a0, a1, a0
; RV64-ZBA-NEXT:    lh a0, 0(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxsuwh:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    lxsuwh a0, (a0), a1
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = zext i32 %b to i64
  %2 = getelementptr i16, ptr %a, i64 %1
  %3 = load i16, ptr %2, align 2
  %4 = sext i16 %3 to i32
  ret i32 %4
}

define i32 @lxsuwhu(ptr %a, i32 %b) {
; RV32-LABEL: lxsuwhu:
; RV32:       # %bb.0:
; RV32-NEXT:    slli a1, a1, 1
; RV32-NEXT:    add a0, a0, a1
; RV32-NEXT:    lhu a0, 0(a0)
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxsuwhu:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    lxshu a0, (a0), a1
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxsuwhu:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    sh1add a0, a1, a0
; RV32-ZBA-NEXT:    lhu a0, 0(a0)
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxsuwhu:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    lxshu a0, (a0), a1
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxsuwhu:
; RV64:       # %bb.0:
; RV64-NEXT:    slli a1, a1, 32
; RV64-NEXT:    srli a1, a1, 31
; RV64-NEXT:    add a0, a0, a1
; RV64-NEXT:    lhu a0, 0(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxsuwhu:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    lxsuwhu a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxsuwhu:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    sh1add.uw a0, a1, a0
; RV64-ZBA-NEXT:    lhu a0, 0(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxsuwhu:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    lxsuwhu a0, (a0), a1
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = zext i32 %b to i64
  %2 = getelementptr i16, ptr %a, i64 %1
  %3 = load i16, ptr %2, align 2
  %4 = zext i16 %3 to i32
  ret i32 %4
}

define i32 @lxsuww_anyext(ptr %a, i32 %b) {
; RV32-LABEL: lxsuww_anyext:
; RV32:       # %bb.0:
; RV32-NEXT:    slli a1, a1, 2
; RV32-NEXT:    add a0, a0, a1
; RV32-NEXT:    lw a0, 0(a0)
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxsuww_anyext:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    lxsw a0, (a0), a1
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxsuww_anyext:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    sh2add a0, a1, a0
; RV32-ZBA-NEXT:    lw a0, 0(a0)
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxsuww_anyext:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    lxsw a0, (a0), a1
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxsuww_anyext:
; RV64:       # %bb.0:
; RV64-NEXT:    slli a1, a1, 32
; RV64-NEXT:    srli a1, a1, 30
; RV64-NEXT:    add a0, a0, a1
; RV64-NEXT:    lw a0, 0(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxsuww_anyext:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    lxsuww a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxsuww_anyext:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    sh2add.uw a0, a1, a0
; RV64-ZBA-NEXT:    lw a0, 0(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxsuww_anyext:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    lxsuww a0, (a0), a1
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = zext i32 %b to i64
  %2 = getelementptr i32, ptr %a, i64 %1
  %3 = load i32, ptr %2, align 4
  ret i32 %3
}

define i64 @lxsuww(ptr %a, i32 %b) {
; RV32-LABEL: lxsuww:
; RV32:       # %bb.0:
; RV32-NEXT:    slli a1, a1, 2
; RV32-NEXT:    add a0, a0, a1
; RV32-NEXT:    lw a0, 0(a0)
; RV32-NEXT:    srai a1, a0, 31
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxsuww:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    lxsw a0, (a0), a1
; RV32-ZILX-NEXT:    srai a1, a0, 31
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxsuww:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    sh2add a0, a1, a0
; RV32-ZBA-NEXT:    lw a0, 0(a0)
; RV32-ZBA-NEXT:    srai a1, a0, 31
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxsuww:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    lxsw a0, (a0), a1
; RV32-ZBA-ZILX-NEXT:    srai a1, a0, 31
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxsuww:
; RV64:       # %bb.0:
; RV64-NEXT:    slli a1, a1, 32
; RV64-NEXT:    srli a1, a1, 30
; RV64-NEXT:    add a0, a0, a1
; RV64-NEXT:    lw a0, 0(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxsuww:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    lxsuww a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxsuww:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    sh2add.uw a0, a1, a0
; RV64-ZBA-NEXT:    lw a0, 0(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxsuww:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    lxsuww a0, (a0), a1
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = zext i32 %b to i64
  %2 = getelementptr i32, ptr %a, i64 %1
  %3 = load i32, ptr %2, align 4
  %4 = sext i32 %3 to i64
  ret i64 %4
}

define i64 @lxsuwwu(ptr %a, i32 %b) {
; RV32-LABEL: lxsuwwu:
; RV32:       # %bb.0:
; RV32-NEXT:    slli a1, a1, 2
; RV32-NEXT:    add a0, a0, a1
; RV32-NEXT:    lw a0, 0(a0)
; RV32-NEXT:    li a1, 0
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxsuwwu:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    lxsw a0, (a0), a1
; RV32-ZILX-NEXT:    li a1, 0
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxsuwwu:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    sh2add a0, a1, a0
; RV32-ZBA-NEXT:    lw a0, 0(a0)
; RV32-ZBA-NEXT:    li a1, 0
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxsuwwu:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    lxsw a0, (a0), a1
; RV32-ZBA-ZILX-NEXT:    li a1, 0
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxsuwwu:
; RV64:       # %bb.0:
; RV64-NEXT:    slli a1, a1, 32
; RV64-NEXT:    srli a1, a1, 30
; RV64-NEXT:    add a0, a0, a1
; RV64-NEXT:    lwu a0, 0(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxsuwwu:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    lxsuwwu a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxsuwwu:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    sh2add.uw a0, a1, a0
; RV64-ZBA-NEXT:    lwu a0, 0(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxsuwwu:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    lxsuwwu a0, (a0), a1
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = zext i32 %b to i64
  %2 = getelementptr i32, ptr %a, i64 %1
  %3 = load i32, ptr %2, align 4
  %4 = zext i32 %3 to i64
  ret i64 %4
}

define i64 @lxsuwd(ptr %a, i32 %b) {
; RV32-LABEL: lxsuwd:
; RV32:       # %bb.0:
; RV32-NEXT:    slli a1, a1, 3
; RV32-NEXT:    add a1, a0, a1
; RV32-NEXT:    lw a0, 0(a1)
; RV32-NEXT:    lw a1, 4(a1)
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxsuwd:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    slli a1, a1, 3
; RV32-ZILX-NEXT:    add a1, a0, a1
; RV32-ZILX-NEXT:    lw a0, 0(a1)
; RV32-ZILX-NEXT:    lw a1, 4(a1)
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxsuwd:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    sh3add a1, a1, a0
; RV32-ZBA-NEXT:    lw a0, 0(a1)
; RV32-ZBA-NEXT:    lw a1, 4(a1)
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxsuwd:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    sh3add a1, a1, a0
; RV32-ZBA-ZILX-NEXT:    lw a0, 0(a1)
; RV32-ZBA-ZILX-NEXT:    lw a1, 4(a1)
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxsuwd:
; RV64:       # %bb.0:
; RV64-NEXT:    slli a1, a1, 32
; RV64-NEXT:    srli a1, a1, 29
; RV64-NEXT:    add a0, a0, a1
; RV64-NEXT:    ld a0, 0(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxsuwd:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    lxsuwd a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxsuwd:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    sh3add.uw a0, a1, a0
; RV64-ZBA-NEXT:    ld a0, 0(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxsuwd:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    lxsuwd a0, (a0), a1
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = zext i32 %b to i64
  %2 = getelementptr i64, ptr %a, i64 %1
  %3 = load i64, ptr %2, align 8
  ret i64 %3
}

;------------------------------------------------------------------------------
; Mismatched shift amount: the shift does not match the access size, so the
; scaled forms must not be selected.
;------------------------------------------------------------------------------

define zeroext i8 @lxsbu_shl_too_large(ptr %a, iXLen %b) {
; RV32-LABEL: lxsbu_shl_too_large:
; RV32:       # %bb.0:
; RV32-NEXT:    slli a1, a1, 2
; RV32-NEXT:    add a0, a0, a1
; RV32-NEXT:    lbu a0, 0(a0)
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxsbu_shl_too_large:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    slli a1, a1, 2
; RV32-ZILX-NEXT:    lxsbu a0, (a0), a1
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxsbu_shl_too_large:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    sh2add a0, a1, a0
; RV32-ZBA-NEXT:    lbu a0, 0(a0)
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxsbu_shl_too_large:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    slli a1, a1, 2
; RV32-ZBA-ZILX-NEXT:    lxsbu a0, (a0), a1
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxsbu_shl_too_large:
; RV64:       # %bb.0:
; RV64-NEXT:    slli a1, a1, 2
; RV64-NEXT:    add a0, a0, a1
; RV64-NEXT:    lbu a0, 0(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxsbu_shl_too_large:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    slli a1, a1, 2
; RV64-ZILX-NEXT:    lxsbu a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxsbu_shl_too_large:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    sh2add a0, a1, a0
; RV64-ZBA-NEXT:    lbu a0, 0(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxsbu_shl_too_large:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    slli a1, a1, 2
; RV64-ZBA-ZILX-NEXT:    lxsbu a0, (a0), a1
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = getelementptr i32, ptr %a, iXLen %b
  %2 = load i8, ptr %1, align 1
  ret i8 %2
}

define signext i16 @lxsh_shl_too_large(ptr %a, iXLen %b) {
; RV32-LABEL: lxsh_shl_too_large:
; RV32:       # %bb.0:
; RV32-NEXT:    slli a1, a1, 2
; RV32-NEXT:    add a0, a0, a1
; RV32-NEXT:    lh a0, 0(a0)
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxsh_shl_too_large:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    slli a1, a1, 2
; RV32-ZILX-NEXT:    lxh a0, (a0), a1
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxsh_shl_too_large:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    sh2add a0, a1, a0
; RV32-ZBA-NEXT:    lh a0, 0(a0)
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxsh_shl_too_large:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    slli a1, a1, 2
; RV32-ZBA-ZILX-NEXT:    lxh a0, (a0), a1
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxsh_shl_too_large:
; RV64:       # %bb.0:
; RV64-NEXT:    slli a1, a1, 2
; RV64-NEXT:    add a0, a0, a1
; RV64-NEXT:    lh a0, 0(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxsh_shl_too_large:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    slli a1, a1, 2
; RV64-ZILX-NEXT:    lxh a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxsh_shl_too_large:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    sh2add a0, a1, a0
; RV64-ZBA-NEXT:    lh a0, 0(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxsh_shl_too_large:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    slli a1, a1, 2
; RV64-ZBA-ZILX-NEXT:    lxh a0, (a0), a1
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = getelementptr i32, ptr %a, iXLen %b
  %2 = load i16, ptr %1, align 2
  ret i16 %2
}

define i32 @lxsw_shl_too_small(ptr %a, iXLen %b) {
; RV32-LABEL: lxsw_shl_too_small:
; RV32:       # %bb.0:
; RV32-NEXT:    slli a1, a1, 1
; RV32-NEXT:    add a0, a0, a1
; RV32-NEXT:    lw a0, 0(a0)
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxsw_shl_too_small:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    slli a1, a1, 1
; RV32-ZILX-NEXT:    lxw a0, (a0), a1
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxsw_shl_too_small:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    sh1add a0, a1, a0
; RV32-ZBA-NEXT:    lw a0, 0(a0)
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxsw_shl_too_small:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    slli a1, a1, 1
; RV32-ZBA-ZILX-NEXT:    lxw a0, (a0), a1
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxsw_shl_too_small:
; RV64:       # %bb.0:
; RV64-NEXT:    slli a1, a1, 1
; RV64-NEXT:    add a0, a0, a1
; RV64-NEXT:    lw a0, 0(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxsw_shl_too_small:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    slli a1, a1, 1
; RV64-ZILX-NEXT:    lxw a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxsw_shl_too_small:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    sh1add a0, a1, a0
; RV64-ZBA-NEXT:    lw a0, 0(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxsw_shl_too_small:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    slli a1, a1, 1
; RV64-ZBA-ZILX-NEXT:    lxw a0, (a0), a1
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = getelementptr i16, ptr %a, iXLen %b
  %2 = load i32, ptr %1, align 4
  ret i32 %2
}

define i32 @lxsw_shl_too_large(ptr %a, iXLen %b) {
; RV32-LABEL: lxsw_shl_too_large:
; RV32:       # %bb.0:
; RV32-NEXT:    slli a1, a1, 3
; RV32-NEXT:    add a0, a0, a1
; RV32-NEXT:    lw a0, 0(a0)
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxsw_shl_too_large:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    slli a1, a1, 3
; RV32-ZILX-NEXT:    lxw a0, (a0), a1
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxsw_shl_too_large:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    sh3add a0, a1, a0
; RV32-ZBA-NEXT:    lw a0, 0(a0)
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxsw_shl_too_large:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    slli a1, a1, 3
; RV32-ZBA-ZILX-NEXT:    lxw a0, (a0), a1
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxsw_shl_too_large:
; RV64:       # %bb.0:
; RV64-NEXT:    slli a1, a1, 3
; RV64-NEXT:    add a0, a0, a1
; RV64-NEXT:    lw a0, 0(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxsw_shl_too_large:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    slli a1, a1, 3
; RV64-ZILX-NEXT:    lxw a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxsw_shl_too_large:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    sh3add a0, a1, a0
; RV64-ZBA-NEXT:    lw a0, 0(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxsw_shl_too_large:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    slli a1, a1, 3
; RV64-ZBA-ZILX-NEXT:    lxw a0, (a0), a1
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = getelementptr i64, ptr %a, iXLen %b
  %2 = load i32, ptr %1, align 4
  ret i32 %2
}

define i64 @lxsd_shl_too_small(ptr %a, iXLen %b) {
; RV32-LABEL: lxsd_shl_too_small:
; RV32:       # %bb.0:
; RV32-NEXT:    slli a1, a1, 2
; RV32-NEXT:    add a1, a0, a1
; RV32-NEXT:    lw a0, 0(a1)
; RV32-NEXT:    lw a1, 4(a1)
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxsd_shl_too_small:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    addi a2, a0, 4
; RV32-ZILX-NEXT:    lxsw a0, (a0), a1
; RV32-ZILX-NEXT:    lxsw a1, (a2), a1
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxsd_shl_too_small:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    sh2add a1, a1, a0
; RV32-ZBA-NEXT:    lw a0, 0(a1)
; RV32-ZBA-NEXT:    lw a1, 4(a1)
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxsd_shl_too_small:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    sh2add a1, a1, a0
; RV32-ZBA-ZILX-NEXT:    lw a0, 0(a1)
; RV32-ZBA-ZILX-NEXT:    lw a1, 4(a1)
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxsd_shl_too_small:
; RV64:       # %bb.0:
; RV64-NEXT:    slli a1, a1, 2
; RV64-NEXT:    add a0, a0, a1
; RV64-NEXT:    ld a0, 0(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxsd_shl_too_small:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    slli a1, a1, 2
; RV64-ZILX-NEXT:    lxd a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxsd_shl_too_small:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    sh2add a0, a1, a0
; RV64-ZBA-NEXT:    ld a0, 0(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxsd_shl_too_small:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    slli a1, a1, 2
; RV64-ZBA-ZILX-NEXT:    lxd a0, (a0), a1
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = getelementptr i32, ptr %a, iXLen %b
  %2 = load i64, ptr %1, align 8
  ret i64 %2
}

define signext i16 @lxsuwh_shl_too_large(ptr %a, i32 %b) {
; RV32-LABEL: lxsuwh_shl_too_large:
; RV32:       # %bb.0:
; RV32-NEXT:    slli a1, a1, 2
; RV32-NEXT:    add a0, a0, a1
; RV32-NEXT:    lh a0, 0(a0)
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxsuwh_shl_too_large:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    slli a1, a1, 2
; RV32-ZILX-NEXT:    lxh a0, (a0), a1
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxsuwh_shl_too_large:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    sh2add a0, a1, a0
; RV32-ZBA-NEXT:    lh a0, 0(a0)
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxsuwh_shl_too_large:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    slli a1, a1, 2
; RV32-ZBA-ZILX-NEXT:    lxh a0, (a0), a1
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxsuwh_shl_too_large:
; RV64:       # %bb.0:
; RV64-NEXT:    slli a1, a1, 32
; RV64-NEXT:    srli a1, a1, 30
; RV64-NEXT:    add a0, a0, a1
; RV64-NEXT:    lh a0, 0(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxsuwh_shl_too_large:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    slli a1, a1, 32
; RV64-ZILX-NEXT:    srli a1, a1, 30
; RV64-ZILX-NEXT:    lxh a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxsuwh_shl_too_large:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    sh2add.uw a0, a1, a0
; RV64-ZBA-NEXT:    lh a0, 0(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxsuwh_shl_too_large:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    slli.uw a1, a1, 2
; RV64-ZBA-ZILX-NEXT:    lxh a0, (a0), a1
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = zext i32 %b to i64
  %2 = getelementptr i32, ptr %a, i64 %1
  %3 = load i16, ptr %2, align 2
  ret i16 %3
}

define i32 @lxsuww_shl_too_small(ptr %a, i32 %b) {
; RV32-LABEL: lxsuww_shl_too_small:
; RV32:       # %bb.0:
; RV32-NEXT:    slli a1, a1, 1
; RV32-NEXT:    add a0, a0, a1
; RV32-NEXT:    lw a0, 0(a0)
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxsuww_shl_too_small:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    slli a1, a1, 1
; RV32-ZILX-NEXT:    lxw a0, (a0), a1
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxsuww_shl_too_small:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    sh1add a0, a1, a0
; RV32-ZBA-NEXT:    lw a0, 0(a0)
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxsuww_shl_too_small:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    slli a1, a1, 1
; RV32-ZBA-ZILX-NEXT:    lxw a0, (a0), a1
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxsuww_shl_too_small:
; RV64:       # %bb.0:
; RV64-NEXT:    slli a1, a1, 32
; RV64-NEXT:    srli a1, a1, 31
; RV64-NEXT:    add a0, a0, a1
; RV64-NEXT:    lw a0, 0(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxsuww_shl_too_small:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    slli a1, a1, 32
; RV64-ZILX-NEXT:    srli a1, a1, 31
; RV64-ZILX-NEXT:    lxw a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxsuww_shl_too_small:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    sh1add.uw a0, a1, a0
; RV64-ZBA-NEXT:    lw a0, 0(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxsuww_shl_too_small:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    slli.uw a1, a1, 1
; RV64-ZBA-ZILX-NEXT:    lxw a0, (a0), a1
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = zext i32 %b to i64
  %2 = getelementptr i16, ptr %a, i64 %1
  %3 = load i32, ptr %2, align 4
  ret i32 %3
}

define i32 @lxsuww_shl_too_large(ptr %a, i32 %b) {
; RV32-LABEL: lxsuww_shl_too_large:
; RV32:       # %bb.0:
; RV32-NEXT:    slli a1, a1, 3
; RV32-NEXT:    add a0, a0, a1
; RV32-NEXT:    lw a0, 0(a0)
; RV32-NEXT:    ret
;
; RV32-ZILX-LABEL: lxsuww_shl_too_large:
; RV32-ZILX:       # %bb.0:
; RV32-ZILX-NEXT:    slli a1, a1, 3
; RV32-ZILX-NEXT:    lxw a0, (a0), a1
; RV32-ZILX-NEXT:    ret
;
; RV32-ZBA-LABEL: lxsuww_shl_too_large:
; RV32-ZBA:       # %bb.0:
; RV32-ZBA-NEXT:    sh3add a0, a1, a0
; RV32-ZBA-NEXT:    lw a0, 0(a0)
; RV32-ZBA-NEXT:    ret
;
; RV32-ZBA-ZILX-LABEL: lxsuww_shl_too_large:
; RV32-ZBA-ZILX:       # %bb.0:
; RV32-ZBA-ZILX-NEXT:    slli a1, a1, 3
; RV32-ZBA-ZILX-NEXT:    lxw a0, (a0), a1
; RV32-ZBA-ZILX-NEXT:    ret
;
; RV64-LABEL: lxsuww_shl_too_large:
; RV64:       # %bb.0:
; RV64-NEXT:    slli a1, a1, 32
; RV64-NEXT:    srli a1, a1, 29
; RV64-NEXT:    add a0, a0, a1
; RV64-NEXT:    lw a0, 0(a0)
; RV64-NEXT:    ret
;
; RV64-ZILX-LABEL: lxsuww_shl_too_large:
; RV64-ZILX:       # %bb.0:
; RV64-ZILX-NEXT:    slli a1, a1, 32
; RV64-ZILX-NEXT:    srli a1, a1, 29
; RV64-ZILX-NEXT:    lxw a0, (a0), a1
; RV64-ZILX-NEXT:    ret
;
; RV64-ZBA-LABEL: lxsuww_shl_too_large:
; RV64-ZBA:       # %bb.0:
; RV64-ZBA-NEXT:    sh3add.uw a0, a1, a0
; RV64-ZBA-NEXT:    lw a0, 0(a0)
; RV64-ZBA-NEXT:    ret
;
; RV64-ZBA-ZILX-LABEL: lxsuww_shl_too_large:
; RV64-ZBA-ZILX:       # %bb.0:
; RV64-ZBA-ZILX-NEXT:    slli.uw a1, a1, 3
; RV64-ZBA-ZILX-NEXT:    lxw a0, (a0), a1
; RV64-ZBA-ZILX-NEXT:    ret
  %1 = zext i32 %b to i64
  %2 = getelementptr i64, ptr %a, i64 %1
  %3 = load i32, ptr %2, align 4
  ret i32 %3
}