llvm/test/CodeGen/RISCV/udiv-const-optimization.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv64-unknown-linux-gnu -mattr=+m | FileCheck %s

; Test optimization of 32-bit unsigned division by constants with 33-bit magic
; constants (IsAdd=true) on RISC-V64. The optimization uses the mulhu instruction.

define i32 @udiv_by_7(i32 %x) nounwind {
; CHECK-LABEL: udiv_by_7:
; CHECK:       # %bb.0:
; CHECK-NEXT:    slli a0, a0, 32
; CHECK-NEXT:    lui a1, 293
; CHECK-NEXT:    srli a0, a0, 32
; CHECK-NEXT:    addi a1, a1, -1755
; CHECK-NEXT:    slli a1, a1, 12
; CHECK-NEXT:    addi a1, a1, -1755
; CHECK-NEXT:    slli a1, a1, 29
; CHECK-NEXT:    mulhu a0, a0, a1
; CHECK-NEXT:    ret
  %div = udiv i32 %x, 7
  ret i32 %div
}

define i32 @udiv_by_19(i32 %x) nounwind {
; CHECK-LABEL: udiv_by_19:
; CHECK:       # %bb.0:
; CHECK-NEXT:    slli a0, a0, 32
; CHECK-NEXT:    lui a1, 717447
; CHECK-NEXT:    srli a0, a0, 32
; CHECK-NEXT:    addi a1, a1, -1077
; CHECK-NEXT:    slli a1, a1, 31
; CHECK-NEXT:    srli a1, a1, 4
; CHECK-NEXT:    mulhu a0, a0, a1
; CHECK-NEXT:    ret
  %div = udiv i32 %x, 19
  ret i32 %div
}

define i32 @udiv_by_21(i32 %x) nounwind {
; CHECK-LABEL: udiv_by_21:
; CHECK:       # %bb.0:
; CHECK-NEXT:    slli a0, a0, 32
; CHECK-NEXT:    lui a1, 549254
; CHECK-NEXT:    srli a0, a0, 32
; CHECK-NEXT:    addi a1, a1, 391
; CHECK-NEXT:    slli a1, a1, 31
; CHECK-NEXT:    srli a1, a1, 4
; CHECK-NEXT:    mulhu a0, a0, a1
; CHECK-NEXT:    ret
  %div = udiv i32 %x, 21
  ret i32 %div
}

; Test non-optimized case
define i32 @udiv_by_3(i32 %x) nounwind {
; CHECK-LABEL: udiv_by_3:
; CHECK:       # %bb.0:
; CHECK-NEXT:    slli a0, a0, 32
; CHECK-NEXT:    lui a1, 699051
; CHECK-NEXT:    addi a1, a1, -1365
; CHECK-NEXT:    slli a1, a1, 32
; CHECK-NEXT:    mulhu a0, a0, a1
; CHECK-NEXT:    srli a0, a0, 33
; CHECK-NEXT:    ret
  %div = udiv i32 %x, 3
  ret i32 %div
}