llvm/test/CodeGen/RISCV/stack-protector-vector-clobber.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
;; Test that stack protection with vector clobbers and inline asm register
;; constraints works correctly. This is a regression test for issue #198699. It
;; has been produced from the repro case at
;; https://github.com/llvm/llvm-project/issues/198699
;
; RUN: llc -mtriple=riscv64 -mattr=+v < %s | FileCheck %s --check-prefix=RV64V

define range(i64 0, -9223372036854775808) i64 @test_stack_protector_with_vector_clobber(ptr nofree noundef %0) #0 {
; RV64V-LABEL: test_stack_protector_with_vector_clobber:
; RV64V:       # %bb.0:
; RV64V-NEXT:    li a1, 2
; RV64V-NEXT:    ld t2, 0(a0)
; RV64V-NEXT:    #APP
; RV64V-NEXT:    #NO_APP
; RV64V-NEXT:    bge t2, a1, .LBB0_2
; RV64V-NEXT:  # %bb.1:
; RV64V-NEXT:    li a0, 0
; RV64V-NEXT:    ret
; RV64V-NEXT:  .LBB0_2:
; RV64V-NEXT:    addi sp, sp, -16
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    lui t0, 1
; RV64V-NEXT:  .LBB0_3: # =>This Inner Loop Header: Depth=1
; RV64V-NEXT:    sub sp, sp, t0
; RV64V-NEXT:    sd zero, 0(sp)
; RV64V-NEXT:    sub t1, t1, t0
; RV64V-NEXT:    bge t1, t0, .LBB0_3
; RV64V-NEXT:  # %bb.4:
; RV64V-NEXT:    sub sp, sp, t1
; RV64V-NEXT:    vsetivli zero, 8, e64, m8, ta, ma
; RV64V-NEXT:    vle64.v v8, (a0)
; RV64V-NEXT:    addi a1, sp, 16
; RV64V-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    #APP
; RV64V-NEXT:    #NO_APP
; RV64V-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vsetivli zero, 8, e64, m8, ta, ma
; RV64V-NEXT:    vse64.v v8, (a0)
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    add sp, sp, a0
; RV64V-NEXT:    addi sp, sp, 16
; RV64V-NEXT:    mv a0, t2
; RV64V-NEXT:    ret
  %2 = load i64, ptr %0, align 8
  ; Inline asm using register x7 (t2)
  %3 = tail call i64 asm sideeffect "", "={x7},{x7}"(i64 %2)
  %4 = icmp slt i64 %3, 2
  br i1 %4, label %7, label %5

5:
  ; Load vector
  %6 = tail call <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64> poison, ptr nonnull %0, i64 8)
  ; Inline asm that clobbers all vector registers
  tail call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31},~{memory}"()
  ; Store vector
  tail call void @llvm.riscv.vse.nxv8i64.p0.i64(<vscale x 8 x i64> %6, ptr nonnull %0, i64 8)
  br label %7

7:
  %8 = phi i64 [ %3, %5 ], [ 0, %1 ]
  ret i64 %8
}

declare <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr, i64)
declare void @llvm.riscv.vse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr, i64)

attributes #0 = { noinline nounwind "probe-stack"="inline-asm" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+v" }