llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-sdnode.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfa,+v \
; RUN:     -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfa,+v \
; RUN:     -verify-machineinstrs < %s | FileCheck %s

define <1 x bfloat> @vfsub_vv_v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb) {
; CHECK-LABEL: vfsub_vv_v1bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 1, e16alt, mf4, ta, ma
; CHECK-NEXT:    vfsub.vv v8, v8, v9
; CHECK-NEXT:    ret
  %vc = fsub <1 x bfloat> %va, %vb
  ret <1 x bfloat> %vc
}

define <1 x bfloat> @vfsub_vf_v1bf16(<1 x bfloat> %va, bfloat %b) {
; CHECK-LABEL: vfsub_vf_v1bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 1, e16alt, mf4, ta, ma
; CHECK-NEXT:    vfsub.vf v8, v8, fa0
; CHECK-NEXT:    ret
  %head = insertelement <1 x bfloat> poison, bfloat %b, i32 0
  %splat = shufflevector <1 x bfloat> %head, <1 x bfloat> poison, <1 x i32> zeroinitializer
  %vc = fsub <1 x bfloat> %va, %splat
  ret <1 x bfloat> %vc
}

define <2 x bfloat> @vfsub_vv_v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb) {
; CHECK-LABEL: vfsub_vv_v2bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 2, e16alt, mf4, ta, ma
; CHECK-NEXT:    vfsub.vv v8, v8, v9
; CHECK-NEXT:    ret
  %vc = fsub <2 x bfloat> %va, %vb
  ret <2 x bfloat> %vc
}

define <2 x bfloat> @vfsub_vf_v2bf16(<2 x bfloat> %va, bfloat %b) {
; CHECK-LABEL: vfsub_vf_v2bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 2, e16alt, mf4, ta, ma
; CHECK-NEXT:    vfsub.vf v8, v8, fa0
; CHECK-NEXT:    ret
  %head = insertelement <2 x bfloat> poison, bfloat %b, i32 0
  %splat = shufflevector <2 x bfloat> %head, <2 x bfloat> poison, <2 x i32> zeroinitializer
  %vc = fsub <2 x bfloat> %va, %splat
  ret <2 x bfloat> %vc
}

define <4 x bfloat> @vfsub_vv_v4bf16(<4 x bfloat> %va, <4 x bfloat> %vb) {
; CHECK-LABEL: vfsub_vv_v4bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e16alt, mf2, ta, ma
; CHECK-NEXT:    vfsub.vv v8, v8, v9
; CHECK-NEXT:    ret
  %vc = fsub <4 x bfloat> %va, %vb
  ret <4 x bfloat> %vc
}

define <4 x bfloat> @vfsub_vf_v4bf16(<4 x bfloat> %va, bfloat %b) {
; CHECK-LABEL: vfsub_vf_v4bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e16alt, mf2, ta, ma
; CHECK-NEXT:    vfsub.vf v8, v8, fa0
; CHECK-NEXT:    ret
  %head = insertelement <4 x bfloat> poison, bfloat %b, i32 0
  %splat = shufflevector <4 x bfloat> %head, <4 x bfloat> poison, <4 x i32> zeroinitializer
  %vc = fsub <4 x bfloat> %va, %splat
  ret <4 x bfloat> %vc
}

define <8 x bfloat> @vfsub_vv_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb) {
; CHECK-LABEL: vfsub_vv_v8bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e16alt, m1, ta, ma
; CHECK-NEXT:    vfsub.vv v8, v8, v9
; CHECK-NEXT:    ret
  %vc = fsub <8 x bfloat> %va, %vb
  ret <8 x bfloat> %vc
}

define <8 x bfloat> @vfsub_vf_v8bf16(<8 x bfloat> %va, bfloat %b) {
; CHECK-LABEL: vfsub_vf_v8bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e16alt, m1, ta, ma
; CHECK-NEXT:    vfsub.vf v8, v8, fa0
; CHECK-NEXT:    ret
  %head = insertelement <8 x bfloat> poison, bfloat %b, i32 0
  %splat = shufflevector <8 x bfloat> %head, <8 x bfloat> poison, <8 x i32> zeroinitializer
  %vc = fsub <8 x bfloat> %va, %splat
  ret <8 x bfloat> %vc
}

define <16 x bfloat> @vfsub_vv_v16bf16(<16 x bfloat> %va, <16 x bfloat> %vb) {
; CHECK-LABEL: vfsub_vv_v16bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e16alt, m2, ta, ma
; CHECK-NEXT:    vfsub.vv v8, v8, v10
; CHECK-NEXT:    ret
  %vc = fsub <16 x bfloat> %va, %vb
  ret <16 x bfloat> %vc
}

define <16 x bfloat> @vfsub_vf_v16bf16(<16 x bfloat> %va, bfloat %b) {
; CHECK-LABEL: vfsub_vf_v16bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e16alt, m2, ta, ma
; CHECK-NEXT:    vfsub.vf v8, v8, fa0
; CHECK-NEXT:    ret
  %head = insertelement <16 x bfloat> poison, bfloat %b, i32 0
  %splat = shufflevector <16 x bfloat> %head, <16 x bfloat> poison, <16 x i32> zeroinitializer
  %vc = fsub <16 x bfloat> %va, %splat
  ret <16 x bfloat> %vc
}

define <32 x bfloat> @vfsub_vv_v32bf16(<32 x bfloat> %va, <32 x bfloat> %vb) {
; CHECK-LABEL: vfsub_vv_v32bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a0, 32
; CHECK-NEXT:    vsetvli zero, a0, e16alt, m4, ta, ma
; CHECK-NEXT:    vfsub.vv v8, v8, v12
; CHECK-NEXT:    ret
  %vc = fsub <32 x bfloat> %va, %vb
  ret <32 x bfloat> %vc
}

define <32 x bfloat> @vfsub_vf_v32bf16(<32 x bfloat> %va, bfloat %b) {
; CHECK-LABEL: vfsub_vf_v32bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a0, 32
; CHECK-NEXT:    vsetvli zero, a0, e16alt, m4, ta, ma
; CHECK-NEXT:    vfsub.vf v8, v8, fa0
; CHECK-NEXT:    ret
  %head = insertelement <32 x bfloat> poison, bfloat %b, i32 0
  %splat = shufflevector <32 x bfloat> %head, <32 x bfloat> poison, <32 x i32> zeroinitializer
  %vc = fsub <32 x bfloat> %va, %splat
  ret <32 x bfloat> %vc
}

define <64 x bfloat> @vfsub_vv_v64bf16(<64 x bfloat> %va, <64 x bfloat> %vb) {
; CHECK-LABEL: vfsub_vv_v64bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a0, 64
; CHECK-NEXT:    vsetvli zero, a0, e16alt, m8, ta, ma
; CHECK-NEXT:    vfsub.vv v8, v8, v16
; CHECK-NEXT:    ret
  %vc = fsub <64 x bfloat> %va, %vb
  ret <64 x bfloat> %vc
}

define <64 x bfloat> @vfsub_vf_v64bf16(<64 x bfloat> %va, bfloat %b) {
; CHECK-LABEL: vfsub_vf_v64bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a0, 64
; CHECK-NEXT:    vsetvli zero, a0, e16alt, m8, ta, ma
; CHECK-NEXT:    vfsub.vf v8, v8, fa0
; CHECK-NEXT:    ret
  %head = insertelement <64 x bfloat> poison, bfloat %b, i32 0
  %splat = shufflevector <64 x bfloat> %head, <64 x bfloat> poison, <64 x i32> zeroinitializer
  %vc = fsub <64 x bfloat> %va, %splat
  ret <64 x bfloat> %vc
}