Google Git
Sign in
llvm/llvm-project.git/refs/heads/main/./llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
blob: 9b2f220dd802e0dea53e8a8bf1d984ecf52bd271 [file] [edit]
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+m -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+m -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb,+m -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb,+m -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
define <vscale x 1 x i8> @vp_cttz_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vand.vv v9, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vzext.vf2 v10, v9
; CHECK-NEXT: vfwcvt.f.xu.v v9, v10
; CHECK-NEXT: vnsrl.wi v9, v9, 23
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT: vnsrl.wi v9, v9, 0
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vsub.vx v8, v9, a0
; CHECK-NEXT: vmerge.vim v8, v8, 8, v0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv1i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 1 x i8> @llvm.vp.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i8> %v
}
define <vscale x 1 x i8> @vp_cttz_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv1i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vand.vv v9, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vzext.vf2 v10, v9
; CHECK-NEXT: vfwcvt.f.xu.v v9, v10
; CHECK-NEXT: vnsrl.wi v9, v9, 23
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT: vnsrl.wi v9, v9, 0
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vsub.vx v8, v9, a0
; CHECK-NEXT: vmerge.vim v8, v8, 8, v0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv1i8_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 1 x i8> @llvm.vp.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 false, <vscale x 1 x i1> splat (i1 true), i32 %evl)
ret <vscale x 1 x i8> %v
}
define <vscale x 2 x i8> @vp_cttz_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vand.vv v9, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vzext.vf2 v10, v9
; CHECK-NEXT: vfwcvt.f.xu.v v9, v10
; CHECK-NEXT: vnsrl.wi v9, v9, 23
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v9, v9, 0
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vsub.vx v8, v9, a0
; CHECK-NEXT: vmerge.vim v8, v8, 8, v0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv2i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i8> %v
}
define <vscale x 2 x i8> @vp_cttz_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv2i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vand.vv v9, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vzext.vf2 v10, v9
; CHECK-NEXT: vfwcvt.f.xu.v v9, v10
; CHECK-NEXT: vnsrl.wi v9, v9, 23
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v9, v9, 0
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vsub.vx v8, v9, a0
; CHECK-NEXT: vmerge.vim v8, v8, 8, v0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv2i8_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 false, <vscale x 2 x i1> splat (i1 true), i32 %evl)
ret <vscale x 2 x i8> %v
}
define <vscale x 4 x i8> @vp_cttz_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vand.vv v9, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vzext.vf2 v12, v9
; CHECK-NEXT: vfwcvt.f.xu.v v10, v12
; CHECK-NEXT: vnsrl.wi v9, v10, 23
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v9, v9, 0
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vsub.vx v8, v9, a0
; CHECK-NEXT: vmerge.vim v8, v8, 8, v0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv4i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 4 x i8> @llvm.vp.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i8> %v
}
define <vscale x 4 x i8> @vp_cttz_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv4i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vand.vv v9, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vzext.vf2 v12, v9
; CHECK-NEXT: vfwcvt.f.xu.v v10, v12
; CHECK-NEXT: vnsrl.wi v9, v10, 23
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v9, v9, 0
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vsub.vx v8, v9, a0
; CHECK-NEXT: vmerge.vim v8, v8, 8, v0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv4i8_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 4 x i8> @llvm.vp.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 false, <vscale x 4 x i1> splat (i1 true), i32 %evl)
ret <vscale x 4 x i8> %v
}
define <vscale x 8 x i8> @vp_cttz_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vand.vv v9, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vzext.vf2 v10, v9
; CHECK-NEXT: vfwcvt.f.xu.v v12, v10
; CHECK-NEXT: vnsrl.wi v10, v12, 23
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v9, v10, 0
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vsub.vx v8, v9, a0
; CHECK-NEXT: vmerge.vim v8, v8, 8, v0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv8i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 8 x i8> @llvm.vp.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i8> %v
}
define <vscale x 8 x i8> @vp_cttz_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv8i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vand.vv v9, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vzext.vf2 v10, v9
; CHECK-NEXT: vfwcvt.f.xu.v v12, v10
; CHECK-NEXT: vnsrl.wi v10, v12, 23
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v9, v10, 0
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vsub.vx v8, v9, a0
; CHECK-NEXT: vmerge.vim v8, v8, 8, v0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv8i8_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 8 x i8> @llvm.vp.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 false, <vscale x 8 x i1> splat (i1 true), i32 %evl)
ret <vscale x 8 x i8> %v
}
define <vscale x 16 x i8> @vp_cttz_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vand.vv v10, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vzext.vf2 v12, v10
; CHECK-NEXT: vfwcvt.f.xu.v v16, v12
; CHECK-NEXT: vnsrl.wi v12, v16, 23
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v10, v12, 0
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vsub.vx v8, v10, a0
; CHECK-NEXT: vmerge.vim v8, v8, 8, v0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv16i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.vp.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i8> %v
}
define <vscale x 16 x i8> @vp_cttz_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv16i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vand.vv v10, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vzext.vf2 v12, v10
; CHECK-NEXT: vfwcvt.f.xu.v v16, v12
; CHECK-NEXT: vnsrl.wi v12, v16, 23
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v10, v12, 0
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vsub.vx v8, v10, a0
; CHECK-NEXT: vmerge.vim v8, v8, 8, v0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv16i8_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.vp.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 false, <vscale x 16 x i1> splat (i1 true), i32 %evl)
ret <vscale x 16 x i8> %v
}
define <vscale x 32 x i8> @vp_cttz_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-NEXT: vadd.vi v12, v8, -1
; CHECK-NEXT: vnot.v v8, v8
; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vv v8, v8, v12
; CHECK-NEXT: vsrl.vi v12, v8, 1
; CHECK-NEXT: vand.vx v12, v12, a0
; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vsub.vv v8, v8, v12
; CHECK-NEXT: vand.vx v12, v8, a0
; CHECK-NEXT: vsrl.vi v8, v8, 2
; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: vadd.vv v8, v12, v8
; CHECK-NEXT: vsrl.vi v12, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v12
; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv32i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 32 x i8> @llvm.vp.cttz.nxv32i8(<vscale x 32 x i8> %va, i1 false, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i8> %v
}
define <vscale x 32 x i8> @vp_cttz_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv32i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-NEXT: vadd.vi v12, v8, -1
; CHECK-NEXT: vnot.v v8, v8
; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vv v8, v8, v12
; CHECK-NEXT: vsrl.vi v12, v8, 1
; CHECK-NEXT: vand.vx v12, v12, a0
; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vsub.vv v8, v8, v12
; CHECK-NEXT: vand.vx v12, v8, a0
; CHECK-NEXT: vsrl.vi v8, v8, 2
; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: vadd.vv v8, v12, v8
; CHECK-NEXT: vsrl.vi v12, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v12
; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv32i8_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 32 x i8> @llvm.vp.cttz.nxv32i8(<vscale x 32 x i8> %va, i1 false, <vscale x 32 x i1> splat (i1 true), i32 %evl)
ret <vscale x 32 x i8> %v
}
define <vscale x 64 x i8> @vp_cttz_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vadd.vi v16, v8, -1
; CHECK-NEXT: vnot.v v8, v8
; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vv v8, v8, v16
; CHECK-NEXT: vsrl.vi v16, v8, 1
; CHECK-NEXT: vand.vx v16, v16, a0
; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vsub.vv v8, v8, v16
; CHECK-NEXT: vand.vx v16, v8, a0
; CHECK-NEXT: vsrl.vi v8, v8, 2
; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: vadd.vv v8, v16, v8
; CHECK-NEXT: vsrl.vi v16, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v16
; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv64i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 64 x i8> @llvm.vp.cttz.nxv64i8(<vscale x 64 x i8> %va, i1 false, <vscale x 64 x i1> %m, i32 %evl)
ret <vscale x 64 x i8> %v
}
define <vscale x 64 x i8> @vp_cttz_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv64i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vadd.vi v16, v8, -1
; CHECK-NEXT: vnot.v v8, v8
; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vv v8, v8, v16
; CHECK-NEXT: vsrl.vi v16, v8, 1
; CHECK-NEXT: vand.vx v16, v16, a0
; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vsub.vv v8, v8, v16
; CHECK-NEXT: vand.vx v16, v8, a0
; CHECK-NEXT: vsrl.vi v8, v8, 2
; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: vadd.vv v8, v16, v8
; CHECK-NEXT: vsrl.vi v16, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v16
; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv64i8_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 64 x i8> @llvm.vp.cttz.nxv64i8(<vscale x 64 x i8> %va, i1 false, <vscale x 64 x i1> splat (i1 true), i32 %evl)
ret <vscale x 64 x i8> %v
}
define <vscale x 1 x i16> @vp_cttz_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vand.vv v9, v8, v9
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vfwcvt.f.xu.v v8, v9
; CHECK-NEXT: vnsrl.wi v8, v8, 23
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv1i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 1 x i16> @llvm.vp.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i16> %v
}
define <vscale x 1 x i16> @vp_cttz_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv1i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vand.vv v9, v8, v9
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vfwcvt.f.xu.v v8, v9
; CHECK-NEXT: vnsrl.wi v8, v8, 23
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv1i16_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 1 x i16> @llvm.vp.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 false, <vscale x 1 x i1> splat (i1 true), i32 %evl)
ret <vscale x 1 x i16> %v
}
define <vscale x 2 x i16> @vp_cttz_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vand.vv v9, v8, v9
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vfwcvt.f.xu.v v8, v9
; CHECK-NEXT: vnsrl.wi v8, v8, 23
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv2i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i16> %v
}
define <vscale x 2 x i16> @vp_cttz_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv2i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vand.vv v9, v8, v9
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vfwcvt.f.xu.v v8, v9
; CHECK-NEXT: vnsrl.wi v8, v8, 23
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv2i16_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 false, <vscale x 2 x i1> splat (i1 true), i32 %evl)
ret <vscale x 2 x i16> %v
}
define <vscale x 4 x i16> @vp_cttz_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vand.vv v10, v8, v9
; CHECK-NEXT: vfwcvt.f.xu.v v8, v10
; CHECK-NEXT: vnsrl.wi v10, v8, 23
; CHECK-NEXT: vsub.vx v8, v10, a0
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv4i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 4 x i16> @llvm.vp.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i16> %v
}
define <vscale x 4 x i16> @vp_cttz_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv4i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vand.vv v10, v8, v9
; CHECK-NEXT: vfwcvt.f.xu.v v8, v10
; CHECK-NEXT: vnsrl.wi v10, v8, 23
; CHECK-NEXT: vsub.vx v8, v10, a0
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv4i16_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 4 x i16> @llvm.vp.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 false, <vscale x 4 x i1> splat (i1 true), i32 %evl)
ret <vscale x 4 x i16> %v
}
define <vscale x 8 x i16> @vp_cttz_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vand.vv v12, v8, v10
; CHECK-NEXT: vfwcvt.f.xu.v v8, v12
; CHECK-NEXT: vnsrl.wi v12, v8, 23
; CHECK-NEXT: vsub.vx v8, v12, a0
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv8i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 8 x i16> @llvm.vp.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i16> %v
}
define <vscale x 8 x i16> @vp_cttz_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv8i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vand.vv v12, v8, v10
; CHECK-NEXT: vfwcvt.f.xu.v v8, v12
; CHECK-NEXT: vnsrl.wi v12, v8, 23
; CHECK-NEXT: vsub.vx v8, v12, a0
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv8i16_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 8 x i16> @llvm.vp.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 false, <vscale x 8 x i1> splat (i1 true), i32 %evl)
ret <vscale x 8 x i16> %v
}
define <vscale x 16 x i16> @vp_cttz_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vand.vv v16, v8, v12
; CHECK-NEXT: vfwcvt.f.xu.v v8, v16
; CHECK-NEXT: vnsrl.wi v16, v8, 23
; CHECK-NEXT: vsub.vx v8, v16, a0
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv16i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 16 x i16> @llvm.vp.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i16> %v
}
define <vscale x 16 x i16> @vp_cttz_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv16i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vand.vv v16, v8, v12
; CHECK-NEXT: vfwcvt.f.xu.v v8, v16
; CHECK-NEXT: vnsrl.wi v16, v8, 23
; CHECK-NEXT: vsub.vx v8, v16, a0
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv16i16_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 16 x i16> @llvm.vp.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 false, <vscale x 16 x i1> splat (i1 true), i32 %evl)
ret <vscale x 16 x i16> %v
}
define <vscale x 32 x i16> @vp_cttz_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-NEXT: vadd.vi v16, v8, -1
; CHECK-NEXT: vnot.v v8, v8
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vand.vv v8, v8, v16
; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v16, v8, 1
; CHECK-NEXT: vand.vx v16, v16, a0
; CHECK-NEXT: lui a0, 3
; CHECK-NEXT: addi a0, a0, 819
; CHECK-NEXT: vsub.vv v8, v8, v16
; CHECK-NEXT: vand.vx v16, v8, a0
; CHECK-NEXT: vsrl.vi v8, v8, 2
; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: lui a0, 1
; CHECK-NEXT: addi a0, a0, -241
; CHECK-NEXT: vadd.vv v8, v16, v8
; CHECK-NEXT: vsrl.vi v16, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v16
; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: li a0, 257
; CHECK-NEXT: vmul.vx v8, v8, a0
; CHECK-NEXT: vsrl.vi v8, v8, 8
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv32i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 32 x i16> @llvm.vp.cttz.nxv32i16(<vscale x 32 x i16> %va, i1 false, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i16> %v
}
define <vscale x 32 x i16> @vp_cttz_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv32i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-NEXT: vadd.vi v16, v8, -1
; CHECK-NEXT: vnot.v v8, v8
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vand.vv v8, v8, v16
; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v16, v8, 1
; CHECK-NEXT: vand.vx v16, v16, a0
; CHECK-NEXT: lui a0, 3
; CHECK-NEXT: addi a0, a0, 819
; CHECK-NEXT: vsub.vv v8, v8, v16
; CHECK-NEXT: vand.vx v16, v8, a0
; CHECK-NEXT: vsrl.vi v8, v8, 2
; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: lui a0, 1
; CHECK-NEXT: addi a0, a0, -241
; CHECK-NEXT: vadd.vv v8, v16, v8
; CHECK-NEXT: vsrl.vi v16, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v16
; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: li a0, 257
; CHECK-NEXT: vmul.vx v8, v8, a0
; CHECK-NEXT: vsrl.vi v8, v8, 8
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv32i16_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 32 x i16> @llvm.vp.cttz.nxv32i16(<vscale x 32 x i16> %va, i1 false, <vscale x 32 x i1> splat (i1 true), i32 %evl)
ret <vscale x 32 x i16> %v
}
define <vscale x 1 x i32> @vp_cttz_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: li a0, 52
; CHECK-NEXT: vand.vv v9, v8, v9
; CHECK-NEXT: vfwcvt.f.xu.v v10, v9
; CHECK-NEXT: vnsrl.wx v9, v10, a0
; CHECK-NEXT: li a0, 1023
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vsub.vx v8, v9, a0
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv1i32:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 1 x i32> @llvm.vp.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i32> %v
}
define <vscale x 1 x i32> @vp_cttz_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv1i32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: li a0, 52
; CHECK-NEXT: vand.vv v9, v8, v9
; CHECK-NEXT: vfwcvt.f.xu.v v10, v9
; CHECK-NEXT: vnsrl.wx v9, v10, a0
; CHECK-NEXT: li a0, 1023
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vsub.vx v8, v9, a0
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv1i32_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 1 x i32> @llvm.vp.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 false, <vscale x 1 x i1> splat (i1 true), i32 %evl)
ret <vscale x 1 x i32> %v
}
define <vscale x 2 x i32> @vp_cttz_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: li a0, 52
; CHECK-NEXT: vand.vv v9, v8, v9
; CHECK-NEXT: vfwcvt.f.xu.v v10, v9
; CHECK-NEXT: vnsrl.wx v9, v10, a0
; CHECK-NEXT: li a0, 1023
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vsub.vx v8, v9, a0
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv2i32:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.vp.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i32> %v
}
define <vscale x 2 x i32> @vp_cttz_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv2i32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: li a0, 52
; CHECK-NEXT: vand.vv v9, v8, v9
; CHECK-NEXT: vfwcvt.f.xu.v v10, v9
; CHECK-NEXT: vnsrl.wx v9, v10, a0
; CHECK-NEXT: li a0, 1023
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vsub.vx v8, v9, a0
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv2i32_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.vp.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 false, <vscale x 2 x i1> splat (i1 true), i32 %evl)
ret <vscale x 2 x i32> %v
}
define <vscale x 4 x i32> @vp_cttz_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0
; CHECK-NEXT: li a0, 52
; CHECK-NEXT: vand.vv v10, v8, v10
; CHECK-NEXT: vfwcvt.f.xu.v v12, v10
; CHECK-NEXT: vnsrl.wx v10, v12, a0
; CHECK-NEXT: li a0, 1023
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vsub.vx v8, v10, a0
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv4i32:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 4 x i32> @llvm.vp.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i32> %v
}
define <vscale x 4 x i32> @vp_cttz_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv4i32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0
; CHECK-NEXT: li a0, 52
; CHECK-NEXT: vand.vv v10, v8, v10
; CHECK-NEXT: vfwcvt.f.xu.v v12, v10
; CHECK-NEXT: vnsrl.wx v10, v12, a0
; CHECK-NEXT: li a0, 1023
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vsub.vx v8, v10, a0
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv4i32_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 4 x i32> @llvm.vp.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 false, <vscale x 4 x i1> splat (i1 true), i32 %evl)
ret <vscale x 4 x i32> %v
}
define <vscale x 8 x i32> @vp_cttz_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0
; CHECK-NEXT: li a0, 52
; CHECK-NEXT: vand.vv v12, v8, v12
; CHECK-NEXT: vfwcvt.f.xu.v v16, v12
; CHECK-NEXT: vnsrl.wx v12, v16, a0
; CHECK-NEXT: li a0, 1023
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vsub.vx v8, v12, a0
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv8i32:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.vp.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i32> %v
}
define <vscale x 8 x i32> @vp_cttz_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv8i32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0
; CHECK-NEXT: li a0, 52
; CHECK-NEXT: vand.vv v12, v8, v12
; CHECK-NEXT: vfwcvt.f.xu.v v16, v12
; CHECK-NEXT: vnsrl.wx v12, v16, a0
; CHECK-NEXT: li a0, 1023
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vsub.vx v8, v12, a0
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv8i32_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.vp.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 false, <vscale x 8 x i1> splat (i1 true), i32 %evl)
ret <vscale x 8 x i32> %v
}
define <vscale x 16 x i32> @vp_cttz_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: li a1, 127
; CHECK-NEXT: vand.vv v16, v8, v16
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vfcvt.f.xu.v v8, v16
; CHECK-NEXT: vsrl.vi v8, v8, 23
; CHECK-NEXT: vsub.vx v8, v8, a1
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vmerge.vxm v8, v8, a1, v0
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv16i32:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.vp.cttz.nxv16i32(<vscale x 16 x i32> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i32> %v
}
define <vscale x 16 x i32> @vp_cttz_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv16i32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: li a1, 127
; CHECK-NEXT: vand.vv v16, v8, v16
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vfcvt.f.xu.v v8, v16
; CHECK-NEXT: vsrl.vi v8, v8, 23
; CHECK-NEXT: vsub.vx v8, v8, a1
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vmerge.vxm v8, v8, a1, v0
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv16i32_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.vp.cttz.nxv16i32(<vscale x 16 x i32> %va, i1 false, <vscale x 16 x i1> splat (i1 true), i32 %evl)
ret <vscale x 16 x i32> %v
}
define <vscale x 1 x i64> @vp_cttz_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: li a1, 52
; CHECK-NEXT: vand.vv v9, v8, v9
; CHECK-NEXT: vfcvt.f.xu.v v9, v9
; CHECK-NEXT: vsrl.vx v9, v9, a1
; CHECK-NEXT: li a1, 1023
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vsub.vx v8, v9, a1
; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vmerge.vxm v8, v8, a1, v0
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv1i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 1 x i64> @llvm.vp.cttz.nxv1i64(<vscale x 1 x i64> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %v
}
define <vscale x 1 x i64> @vp_cttz_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv1i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: li a1, 52
; CHECK-NEXT: vand.vv v9, v8, v9
; CHECK-NEXT: vfcvt.f.xu.v v9, v9
; CHECK-NEXT: vsrl.vx v9, v9, a1
; CHECK-NEXT: li a1, 1023
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vsub.vx v8, v9, a1
; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vmerge.vxm v8, v8, a1, v0
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv1i64_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 1 x i64> @llvm.vp.cttz.nxv1i64(<vscale x 1 x i64> %va, i1 false, <vscale x 1 x i1> splat (i1 true), i32 %evl)
ret <vscale x 1 x i64> %v
}
define <vscale x 2 x i64> @vp_cttz_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: li a1, 52
; CHECK-NEXT: vand.vv v10, v8, v10
; CHECK-NEXT: vfcvt.f.xu.v v10, v10
; CHECK-NEXT: vsrl.vx v10, v10, a1
; CHECK-NEXT: li a1, 1023
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vsub.vx v8, v10, a1
; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vmerge.vxm v8, v8, a1, v0
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv2i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 2 x i64> @llvm.vp.cttz.nxv2i64(<vscale x 2 x i64> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v
}
define <vscale x 2 x i64> @vp_cttz_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv2i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: li a1, 52
; CHECK-NEXT: vand.vv v10, v8, v10
; CHECK-NEXT: vfcvt.f.xu.v v10, v10
; CHECK-NEXT: vsrl.vx v10, v10, a1
; CHECK-NEXT: li a1, 1023
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vsub.vx v8, v10, a1
; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vmerge.vxm v8, v8, a1, v0
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv2i64_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 2 x i64> @llvm.vp.cttz.nxv2i64(<vscale x 2 x i64> %va, i1 false, <vscale x 2 x i1> splat (i1 true), i32 %evl)
ret <vscale x 2 x i64> %v
}
define <vscale x 4 x i64> @vp_cttz_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: li a1, 52
; CHECK-NEXT: vand.vv v12, v8, v12
; CHECK-NEXT: vfcvt.f.xu.v v12, v12
; CHECK-NEXT: vsrl.vx v12, v12, a1
; CHECK-NEXT: li a1, 1023
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vsub.vx v8, v12, a1
; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vmerge.vxm v8, v8, a1, v0
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv4i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 4 x i64> @llvm.vp.cttz.nxv4i64(<vscale x 4 x i64> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v
}
define <vscale x 4 x i64> @vp_cttz_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv4i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: li a1, 52
; CHECK-NEXT: vand.vv v12, v8, v12
; CHECK-NEXT: vfcvt.f.xu.v v12, v12
; CHECK-NEXT: vsrl.vx v12, v12, a1
; CHECK-NEXT: li a1, 1023
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vsub.vx v8, v12, a1
; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vmerge.vxm v8, v8, a1, v0
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv4i64_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 4 x i64> @llvm.vp.cttz.nxv4i64(<vscale x 4 x i64> %va, i1 false, <vscale x 4 x i1> splat (i1 true), i32 %evl)
ret <vscale x 4 x i64> %v
}
define <vscale x 7 x i64> @vp_cttz_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv7i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: li a1, 52
; CHECK-NEXT: vand.vv v16, v8, v16
; CHECK-NEXT: vfcvt.f.xu.v v16, v16
; CHECK-NEXT: vsrl.vx v16, v16, a1
; CHECK-NEXT: li a1, 1023
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vsub.vx v8, v16, a1
; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vmerge.vxm v8, v8, a1, v0
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv7i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 7 x i64> @llvm.vp.cttz.nxv7i64(<vscale x 7 x i64> %va, i1 false, <vscale x 7 x i1> %m, i32 %evl)
ret <vscale x 7 x i64> %v
}
define <vscale x 7 x i64> @vp_cttz_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv7i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: li a1, 52
; CHECK-NEXT: vand.vv v16, v8, v16
; CHECK-NEXT: vfcvt.f.xu.v v16, v16
; CHECK-NEXT: vsrl.vx v16, v16, a1
; CHECK-NEXT: li a1, 1023
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vsub.vx v8, v16, a1
; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vmerge.vxm v8, v8, a1, v0
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv7i64_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 7 x i64> @llvm.vp.cttz.nxv7i64(<vscale x 7 x i64> %va, i1 false, <vscale x 7 x i1> splat (i1 true), i32 %evl)
ret <vscale x 7 x i64> %v
}
define <vscale x 8 x i64> @vp_cttz_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: li a1, 52
; CHECK-NEXT: vand.vv v16, v8, v16
; CHECK-NEXT: vfcvt.f.xu.v v16, v16
; CHECK-NEXT: vsrl.vx v16, v16, a1
; CHECK-NEXT: li a1, 1023
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vsub.vx v8, v16, a1
; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vmerge.vxm v8, v8, a1, v0
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv8i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 8 x i64> @llvm.vp.cttz.nxv8i64(<vscale x 8 x i64> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v
}
define <vscale x 8 x i64> @vp_cttz_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv8i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: li a1, 52
; CHECK-NEXT: vand.vv v16, v8, v16
; CHECK-NEXT: vfcvt.f.xu.v v16, v16
; CHECK-NEXT: vsrl.vx v16, v16, a1
; CHECK-NEXT: li a1, 1023
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vsub.vx v8, v16, a1
; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vmerge.vxm v8, v8, a1, v0
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv8i64_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 8 x i64> @llvm.vp.cttz.nxv8i64(<vscale x 8 x i64> %va, i1 false, <vscale x 8 x i1> splat (i1 true), i32 %evl)
ret <vscale x 8 x i64> %v
}
define <vscale x 16 x i64> @vp_cttz_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv16i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v24, v8, 0
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vand.vv v8, v8, v24
; CHECK-NEXT: vrsub.vi v24, v16, 0
; CHECK-NEXT: vand.vv v24, v16, v24
; CHECK-NEXT: vmseq.vi v7, v16, 0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: li a1, 52
; CHECK-NEXT: li a2, 1023
; CHECK-NEXT: li a3, 64
; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: vfcvt.f.xu.v v16, v24
; CHECK-NEXT: vsrl.vx v8, v8, a1
; CHECK-NEXT: vsrl.vx v16, v16, a1
; CHECK-NEXT: vsub.vx v8, v8, a2
; CHECK-NEXT: vsub.vx v16, v16, a2
; CHECK-NEXT: vmerge.vxm v8, v8, a3, v0
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vmerge.vxm v16, v16, a3, v0
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv16i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: vctz.v v16, v16
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 16 x i64> @llvm.vp.cttz.nxv16i64(<vscale x 16 x i64> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i64> %v
}
define <vscale x 16 x i64> @vp_cttz_nxv16i64_unmasked(<vscale x 16 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv16i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v24, v8, 0
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vand.vv v8, v8, v24
; CHECK-NEXT: vrsub.vi v24, v16, 0
; CHECK-NEXT: vand.vv v24, v16, v24
; CHECK-NEXT: vmseq.vi v7, v16, 0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: li a1, 52
; CHECK-NEXT: li a2, 1023
; CHECK-NEXT: li a3, 64
; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: vfcvt.f.xu.v v16, v24
; CHECK-NEXT: vsrl.vx v8, v8, a1
; CHECK-NEXT: vsrl.vx v16, v16, a1
; CHECK-NEXT: vsub.vx v8, v8, a2
; CHECK-NEXT: vsub.vx v16, v16, a2
; CHECK-NEXT: vmerge.vxm v8, v8, a3, v0
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vmerge.vxm v16, v16, a3, v0
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv16i64_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: vctz.v v16, v16
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 16 x i64> @llvm.vp.cttz.nxv16i64(<vscale x 16 x i64> %va, i1 false, <vscale x 16 x i1> splat (i1 true), i32 %evl)
ret <vscale x 16 x i64> %v
}
define <vscale x 1 x i8> @vp_cttz_zero_undef_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: vand.vv v8, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vzext.vf2 v9, v8
; CHECK-NEXT: vfwcvt.f.xu.v v8, v9
; CHECK-NEXT: vnsrl.wi v8, v8, 23
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv1i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 1 x i8> @llvm.vp.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i8> %v
}
define <vscale x 1 x i8> @vp_cttz_zero_undef_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv1i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: vand.vv v8, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vzext.vf2 v9, v8
; CHECK-NEXT: vfwcvt.f.xu.v v8, v9
; CHECK-NEXT: vnsrl.wi v8, v8, 23
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv1i8_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 1 x i8> @llvm.vp.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 true, <vscale x 1 x i1> splat (i1 true), i32 %evl)
ret <vscale x 1 x i8> %v
}
define <vscale x 2 x i8> @vp_cttz_zero_undef_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: vand.vv v8, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vzext.vf2 v9, v8
; CHECK-NEXT: vfwcvt.f.xu.v v8, v9
; CHECK-NEXT: vnsrl.wi v8, v8, 23
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv2i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i8> %v
}
define <vscale x 2 x i8> @vp_cttz_zero_undef_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv2i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: vand.vv v8, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vzext.vf2 v9, v8
; CHECK-NEXT: vfwcvt.f.xu.v v8, v9
; CHECK-NEXT: vnsrl.wi v8, v8, 23
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv2i8_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 true, <vscale x 2 x i1> splat (i1 true), i32 %evl)
ret <vscale x 2 x i8> %v
}
define <vscale x 4 x i8> @vp_cttz_zero_undef_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: vand.vv v8, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vzext.vf2 v10, v8
; CHECK-NEXT: vfwcvt.f.xu.v v8, v10
; CHECK-NEXT: vnsrl.wi v10, v8, 23
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv4i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 4 x i8> @llvm.vp.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i8> %v
}
define <vscale x 4 x i8> @vp_cttz_zero_undef_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv4i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: vand.vv v8, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vzext.vf2 v10, v8
; CHECK-NEXT: vfwcvt.f.xu.v v8, v10
; CHECK-NEXT: vnsrl.wi v10, v8, 23
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv4i8_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 4 x i8> @llvm.vp.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 true, <vscale x 4 x i1> splat (i1 true), i32 %evl)
ret <vscale x 4 x i8> %v
}
define <vscale x 8 x i8> @vp_cttz_zero_undef_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: vand.vv v8, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vzext.vf2 v12, v8
; CHECK-NEXT: vfwcvt.f.xu.v v8, v12
; CHECK-NEXT: vnsrl.wi v12, v8, 23
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv8i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 8 x i8> @llvm.vp.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i8> %v
}
define <vscale x 8 x i8> @vp_cttz_zero_undef_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv8i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: vand.vv v8, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vzext.vf2 v12, v8
; CHECK-NEXT: vfwcvt.f.xu.v v8, v12
; CHECK-NEXT: vnsrl.wi v12, v8, 23
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv8i8_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 8 x i8> @llvm.vp.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 true, <vscale x 8 x i1> splat (i1 true), i32 %evl)
ret <vscale x 8 x i8> %v
}
define <vscale x 16 x i8> @vp_cttz_zero_undef_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0
; CHECK-NEXT: vand.vv v8, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vzext.vf2 v16, v8
; CHECK-NEXT: vfwcvt.f.xu.v v8, v16
; CHECK-NEXT: vnsrl.wi v16, v8, 23
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v16, 0
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.vp.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i8> %v
}
define <vscale x 16 x i8> @vp_cttz_zero_undef_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv16i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0
; CHECK-NEXT: vand.vv v8, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vzext.vf2 v16, v8
; CHECK-NEXT: vfwcvt.f.xu.v v8, v16
; CHECK-NEXT: vnsrl.wi v16, v8, 23
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v16, 0
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i8_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.vp.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 true, <vscale x 16 x i1> splat (i1 true), i32 %evl)
ret <vscale x 16 x i8> %v
}
define <vscale x 32 x i8> @vp_cttz_zero_undef_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-NEXT: vadd.vi v12, v8, -1
; CHECK-NEXT: vnot.v v8, v8
; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vv v8, v8, v12
; CHECK-NEXT: vsrl.vi v12, v8, 1
; CHECK-NEXT: vand.vx v12, v12, a0
; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vsub.vv v8, v8, v12
; CHECK-NEXT: vand.vx v12, v8, a0
; CHECK-NEXT: vsrl.vi v8, v8, 2
; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: vadd.vv v8, v12, v8
; CHECK-NEXT: vsrl.vi v12, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v12
; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv32i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 32 x i8> @llvm.vp.cttz.nxv32i8(<vscale x 32 x i8> %va, i1 true, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i8> %v
}
define <vscale x 32 x i8> @vp_cttz_zero_undef_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv32i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-NEXT: vadd.vi v12, v8, -1
; CHECK-NEXT: vnot.v v8, v8
; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vv v8, v8, v12
; CHECK-NEXT: vsrl.vi v12, v8, 1
; CHECK-NEXT: vand.vx v12, v12, a0
; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vsub.vv v8, v8, v12
; CHECK-NEXT: vand.vx v12, v8, a0
; CHECK-NEXT: vsrl.vi v8, v8, 2
; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: vadd.vv v8, v12, v8
; CHECK-NEXT: vsrl.vi v12, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v12
; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv32i8_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 32 x i8> @llvm.vp.cttz.nxv32i8(<vscale x 32 x i8> %va, i1 true, <vscale x 32 x i1> splat (i1 true), i32 %evl)
ret <vscale x 32 x i8> %v
}
define <vscale x 64 x i8> @vp_cttz_zero_undef_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vadd.vi v16, v8, -1
; CHECK-NEXT: vnot.v v8, v8
; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vv v8, v8, v16
; CHECK-NEXT: vsrl.vi v16, v8, 1
; CHECK-NEXT: vand.vx v16, v16, a0
; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vsub.vv v8, v8, v16
; CHECK-NEXT: vand.vx v16, v8, a0
; CHECK-NEXT: vsrl.vi v8, v8, 2
; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: vadd.vv v8, v16, v8
; CHECK-NEXT: vsrl.vi v16, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v16
; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv64i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 64 x i8> @llvm.vp.cttz.nxv64i8(<vscale x 64 x i8> %va, i1 true, <vscale x 64 x i1> %m, i32 %evl)
ret <vscale x 64 x i8> %v
}
define <vscale x 64 x i8> @vp_cttz_zero_undef_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv64i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vadd.vi v16, v8, -1
; CHECK-NEXT: vnot.v v8, v8
; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vv v8, v8, v16
; CHECK-NEXT: vsrl.vi v16, v8, 1
; CHECK-NEXT: vand.vx v16, v16, a0
; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vsub.vv v8, v8, v16
; CHECK-NEXT: vand.vx v16, v8, a0
; CHECK-NEXT: vsrl.vi v8, v8, 2
; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: vadd.vv v8, v16, v8
; CHECK-NEXT: vsrl.vi v16, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v16
; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv64i8_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 64 x i8> @llvm.vp.cttz.nxv64i8(<vscale x 64 x i8> %va, i1 true, <vscale x 64 x i1> splat (i1 true), i32 %evl)
ret <vscale x 64 x i8> %v
}
define <vscale x 1 x i16> @vp_cttz_zero_undef_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: vand.vv v8, v8, v9
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
; CHECK-NEXT: vnsrl.wi v8, v9, 23
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv1i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 1 x i16> @llvm.vp.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i16> %v
}
define <vscale x 1 x i16> @vp_cttz_zero_undef_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv1i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: vand.vv v8, v8, v9
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
; CHECK-NEXT: vnsrl.wi v8, v9, 23
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv1i16_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 1 x i16> @llvm.vp.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 true, <vscale x 1 x i1> splat (i1 true), i32 %evl)
ret <vscale x 1 x i16> %v
}
define <vscale x 2 x i16> @vp_cttz_zero_undef_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: vand.vv v8, v8, v9
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
; CHECK-NEXT: vnsrl.wi v8, v9, 23
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv2i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i16> %v
}
define <vscale x 2 x i16> @vp_cttz_zero_undef_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv2i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: vand.vv v8, v8, v9
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
; CHECK-NEXT: vnsrl.wi v8, v9, 23
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv2i16_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 true, <vscale x 2 x i1> splat (i1 true), i32 %evl)
ret <vscale x 2 x i16> %v
}
define <vscale x 4 x i16> @vp_cttz_zero_undef_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: vand.vv v10, v8, v9
; CHECK-NEXT: vfwcvt.f.xu.v v8, v10
; CHECK-NEXT: vnsrl.wi v10, v8, 23
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsub.vx v8, v10, a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv4i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 4 x i16> @llvm.vp.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i16> %v
}
define <vscale x 4 x i16> @vp_cttz_zero_undef_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv4i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: vand.vv v10, v8, v9
; CHECK-NEXT: vfwcvt.f.xu.v v8, v10
; CHECK-NEXT: vnsrl.wi v10, v8, 23
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsub.vx v8, v10, a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv4i16_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 4 x i16> @llvm.vp.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 true, <vscale x 4 x i1> splat (i1 true), i32 %evl)
ret <vscale x 4 x i16> %v
}
define <vscale x 8 x i16> @vp_cttz_zero_undef_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0
; CHECK-NEXT: vand.vv v12, v8, v10
; CHECK-NEXT: vfwcvt.f.xu.v v8, v12
; CHECK-NEXT: vnsrl.wi v12, v8, 23
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsub.vx v8, v12, a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv8i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 8 x i16> @llvm.vp.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i16> %v
}
define <vscale x 8 x i16> @vp_cttz_zero_undef_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv8i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0
; CHECK-NEXT: vand.vv v12, v8, v10
; CHECK-NEXT: vfwcvt.f.xu.v v8, v12
; CHECK-NEXT: vnsrl.wi v12, v8, 23
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsub.vx v8, v12, a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv8i16_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 8 x i16> @llvm.vp.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 true, <vscale x 8 x i1> splat (i1 true), i32 %evl)
ret <vscale x 8 x i16> %v
}
define <vscale x 16 x i16> @vp_cttz_zero_undef_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0
; CHECK-NEXT: vand.vv v16, v8, v12
; CHECK-NEXT: vfwcvt.f.xu.v v8, v16
; CHECK-NEXT: vnsrl.wi v16, v8, 23
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsub.vx v8, v16, a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 16 x i16> @llvm.vp.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i16> %v
}
define <vscale x 16 x i16> @vp_cttz_zero_undef_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv16i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0
; CHECK-NEXT: vand.vv v16, v8, v12
; CHECK-NEXT: vfwcvt.f.xu.v v8, v16
; CHECK-NEXT: vnsrl.wi v16, v8, 23
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsub.vx v8, v16, a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i16_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 16 x i16> @llvm.vp.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 true, <vscale x 16 x i1> splat (i1 true), i32 %evl)
ret <vscale x 16 x i16> %v
}
define <vscale x 32 x i16> @vp_cttz_zero_undef_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-NEXT: vadd.vi v16, v8, -1
; CHECK-NEXT: vnot.v v8, v8
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vand.vv v8, v8, v16
; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v16, v8, 1
; CHECK-NEXT: vand.vx v16, v16, a0
; CHECK-NEXT: lui a0, 3
; CHECK-NEXT: addi a0, a0, 819
; CHECK-NEXT: vsub.vv v8, v8, v16
; CHECK-NEXT: vand.vx v16, v8, a0
; CHECK-NEXT: vsrl.vi v8, v8, 2
; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: lui a0, 1
; CHECK-NEXT: addi a0, a0, -241
; CHECK-NEXT: vadd.vv v8, v16, v8
; CHECK-NEXT: vsrl.vi v16, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v16
; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: li a0, 257
; CHECK-NEXT: vmul.vx v8, v8, a0
; CHECK-NEXT: vsrl.vi v8, v8, 8
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv32i16:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 32 x i16> @llvm.vp.cttz.nxv32i16(<vscale x 32 x i16> %va, i1 true, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i16> %v
}
define <vscale x 32 x i16> @vp_cttz_zero_undef_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv32i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-NEXT: vadd.vi v16, v8, -1
; CHECK-NEXT: vnot.v v8, v8
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vand.vv v8, v8, v16
; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v16, v8, 1
; CHECK-NEXT: vand.vx v16, v16, a0
; CHECK-NEXT: lui a0, 3
; CHECK-NEXT: addi a0, a0, 819
; CHECK-NEXT: vsub.vv v8, v8, v16
; CHECK-NEXT: vand.vx v16, v8, a0
; CHECK-NEXT: vsrl.vi v8, v8, 2
; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: lui a0, 1
; CHECK-NEXT: addi a0, a0, -241
; CHECK-NEXT: vadd.vv v8, v16, v8
; CHECK-NEXT: vsrl.vi v16, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v16
; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: li a0, 257
; CHECK-NEXT: vmul.vx v8, v8, a0
; CHECK-NEXT: vsrl.vi v8, v8, 8
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv32i16_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 32 x i16> @llvm.vp.cttz.nxv32i16(<vscale x 32 x i16> %va, i1 true, <vscale x 32 x i1> splat (i1 true), i32 %evl)
ret <vscale x 32 x i16> %v
}
define <vscale x 1 x i32> @vp_cttz_zero_undef_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: li a0, 52
; CHECK-NEXT: vand.vv v8, v8, v9
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
; CHECK-NEXT: vnsrl.wx v8, v9, a0
; CHECK-NEXT: li a0, 1023
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv1i32:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 1 x i32> @llvm.vp.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i32> %v
}
define <vscale x 1 x i32> @vp_cttz_zero_undef_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv1i32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: li a0, 52
; CHECK-NEXT: vand.vv v8, v8, v9
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
; CHECK-NEXT: vnsrl.wx v8, v9, a0
; CHECK-NEXT: li a0, 1023
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv1i32_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 1 x i32> @llvm.vp.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 true, <vscale x 1 x i1> splat (i1 true), i32 %evl)
ret <vscale x 1 x i32> %v
}
define <vscale x 2 x i32> @vp_cttz_zero_undef_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: li a0, 52
; CHECK-NEXT: vand.vv v10, v8, v9
; CHECK-NEXT: vfwcvt.f.xu.v v8, v10
; CHECK-NEXT: vnsrl.wx v10, v8, a0
; CHECK-NEXT: li a0, 1023
; CHECK-NEXT: vsub.vx v8, v10, a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv2i32:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.vp.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i32> %v
}
define <vscale x 2 x i32> @vp_cttz_zero_undef_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv2i32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: li a0, 52
; CHECK-NEXT: vand.vv v10, v8, v9
; CHECK-NEXT: vfwcvt.f.xu.v v8, v10
; CHECK-NEXT: vnsrl.wx v10, v8, a0
; CHECK-NEXT: li a0, 1023
; CHECK-NEXT: vsub.vx v8, v10, a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv2i32_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.vp.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 true, <vscale x 2 x i1> splat (i1 true), i32 %evl)
ret <vscale x 2 x i32> %v
}
define <vscale x 4 x i32> @vp_cttz_zero_undef_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0
; CHECK-NEXT: li a0, 52
; CHECK-NEXT: vand.vv v12, v8, v10
; CHECK-NEXT: vfwcvt.f.xu.v v8, v12
; CHECK-NEXT: vnsrl.wx v12, v8, a0
; CHECK-NEXT: li a0, 1023
; CHECK-NEXT: vsub.vx v8, v12, a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv4i32:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 4 x i32> @llvm.vp.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i32> %v
}
define <vscale x 4 x i32> @vp_cttz_zero_undef_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv4i32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0
; CHECK-NEXT: li a0, 52
; CHECK-NEXT: vand.vv v12, v8, v10
; CHECK-NEXT: vfwcvt.f.xu.v v8, v12
; CHECK-NEXT: vnsrl.wx v12, v8, a0
; CHECK-NEXT: li a0, 1023
; CHECK-NEXT: vsub.vx v8, v12, a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv4i32_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 4 x i32> @llvm.vp.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 true, <vscale x 4 x i1> splat (i1 true), i32 %evl)
ret <vscale x 4 x i32> %v
}
define <vscale x 8 x i32> @vp_cttz_zero_undef_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0
; CHECK-NEXT: li a0, 52
; CHECK-NEXT: vand.vv v16, v8, v12
; CHECK-NEXT: vfwcvt.f.xu.v v8, v16
; CHECK-NEXT: vnsrl.wx v16, v8, a0
; CHECK-NEXT: li a0, 1023
; CHECK-NEXT: vsub.vx v8, v16, a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv8i32:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.vp.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i32> %v
}
define <vscale x 8 x i32> @vp_cttz_zero_undef_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv8i32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0
; CHECK-NEXT: li a0, 52
; CHECK-NEXT: vand.vv v16, v8, v12
; CHECK-NEXT: vfwcvt.f.xu.v v8, v16
; CHECK-NEXT: vnsrl.wx v16, v8, a0
; CHECK-NEXT: li a0, 1023
; CHECK-NEXT: vsub.vx v8, v16, a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv8i32_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.vp.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 true, <vscale x 8 x i1> splat (i1 true), i32 %evl)
ret <vscale x 8 x i32> %v
}
define <vscale x 16 x i32> @vp_cttz_zero_undef_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vand.vv v8, v8, v16
; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: vsrl.vi v8, v8, 23
; CHECK-NEXT: li a1, 127
; CHECK-NEXT: vsub.vx v8, v8, a1
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i32:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.vp.cttz.nxv16i32(<vscale x 16 x i32> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i32> %v
}
define <vscale x 16 x i32> @vp_cttz_zero_undef_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv16i32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vand.vv v8, v8, v16
; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: vsrl.vi v8, v8, 23
; CHECK-NEXT: li a1, 127
; CHECK-NEXT: vsub.vx v8, v8, a1
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i32_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.vp.cttz.nxv16i32(<vscale x 16 x i32> %va, i1 true, <vscale x 16 x i1> splat (i1 true), i32 %evl)
ret <vscale x 16 x i32> %v
}
define <vscale x 1 x i64> @vp_cttz_zero_undef_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: li a1, 52
; CHECK-NEXT: vand.vv v8, v8, v9
; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: vsrl.vx v8, v8, a1
; CHECK-NEXT: li a1, 1023
; CHECK-NEXT: vsub.vx v8, v8, a1
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv1i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 1 x i64> @llvm.vp.cttz.nxv1i64(<vscale x 1 x i64> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %v
}
define <vscale x 1 x i64> @vp_cttz_zero_undef_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv1i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: li a1, 52
; CHECK-NEXT: vand.vv v8, v8, v9
; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: vsrl.vx v8, v8, a1
; CHECK-NEXT: li a1, 1023
; CHECK-NEXT: vsub.vx v8, v8, a1
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv1i64_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 1 x i64> @llvm.vp.cttz.nxv1i64(<vscale x 1 x i64> %va, i1 true, <vscale x 1 x i1> splat (i1 true), i32 %evl)
ret <vscale x 1 x i64> %v
}
define <vscale x 2 x i64> @vp_cttz_zero_undef_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: li a1, 52
; CHECK-NEXT: vand.vv v8, v8, v10
; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: vsrl.vx v8, v8, a1
; CHECK-NEXT: li a1, 1023
; CHECK-NEXT: vsub.vx v8, v8, a1
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv2i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 2 x i64> @llvm.vp.cttz.nxv2i64(<vscale x 2 x i64> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v
}
define <vscale x 2 x i64> @vp_cttz_zero_undef_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv2i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: li a1, 52
; CHECK-NEXT: vand.vv v8, v8, v10
; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: vsrl.vx v8, v8, a1
; CHECK-NEXT: li a1, 1023
; CHECK-NEXT: vsub.vx v8, v8, a1
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv2i64_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 2 x i64> @llvm.vp.cttz.nxv2i64(<vscale x 2 x i64> %va, i1 true, <vscale x 2 x i1> splat (i1 true), i32 %evl)
ret <vscale x 2 x i64> %v
}
define <vscale x 4 x i64> @vp_cttz_zero_undef_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: li a1, 52
; CHECK-NEXT: vand.vv v8, v8, v12
; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: vsrl.vx v8, v8, a1
; CHECK-NEXT: li a1, 1023
; CHECK-NEXT: vsub.vx v8, v8, a1
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv4i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 4 x i64> @llvm.vp.cttz.nxv4i64(<vscale x 4 x i64> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v
}
define <vscale x 4 x i64> @vp_cttz_zero_undef_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv4i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: li a1, 52
; CHECK-NEXT: vand.vv v8, v8, v12
; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: vsrl.vx v8, v8, a1
; CHECK-NEXT: li a1, 1023
; CHECK-NEXT: vsub.vx v8, v8, a1
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv4i64_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 4 x i64> @llvm.vp.cttz.nxv4i64(<vscale x 4 x i64> %va, i1 true, <vscale x 4 x i1> splat (i1 true), i32 %evl)
ret <vscale x 4 x i64> %v
}
define <vscale x 7 x i64> @vp_cttz_zero_undef_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv7i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: li a1, 52
; CHECK-NEXT: vand.vv v8, v8, v16
; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: vsrl.vx v8, v8, a1
; CHECK-NEXT: li a1, 1023
; CHECK-NEXT: vsub.vx v8, v8, a1
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv7i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 7 x i64> @llvm.vp.cttz.nxv7i64(<vscale x 7 x i64> %va, i1 true, <vscale x 7 x i1> %m, i32 %evl)
ret <vscale x 7 x i64> %v
}
define <vscale x 7 x i64> @vp_cttz_zero_undef_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv7i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: li a1, 52
; CHECK-NEXT: vand.vv v8, v8, v16
; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: vsrl.vx v8, v8, a1
; CHECK-NEXT: li a1, 1023
; CHECK-NEXT: vsub.vx v8, v8, a1
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv7i64_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 7 x i64> @llvm.vp.cttz.nxv7i64(<vscale x 7 x i64> %va, i1 true, <vscale x 7 x i1> splat (i1 true), i32 %evl)
ret <vscale x 7 x i64> %v
}
define <vscale x 8 x i64> @vp_cttz_zero_undef_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: li a1, 52
; CHECK-NEXT: vand.vv v8, v8, v16
; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: vsrl.vx v8, v8, a1
; CHECK-NEXT: li a1, 1023
; CHECK-NEXT: vsub.vx v8, v8, a1
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv8i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 8 x i64> @llvm.vp.cttz.nxv8i64(<vscale x 8 x i64> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v
}
define <vscale x 8 x i64> @vp_cttz_zero_undef_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv8i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: li a1, 52
; CHECK-NEXT: vand.vv v8, v8, v16
; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: vsrl.vx v8, v8, a1
; CHECK-NEXT: li a1, 1023
; CHECK-NEXT: vsub.vx v8, v8, a1
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv8i64_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 8 x i64> @llvm.vp.cttz.nxv8i64(<vscale x 8 x i64> %va, i1 true, <vscale x 8 x i1> splat (i1 true), i32 %evl)
ret <vscale x 8 x i64> %v
}
define <vscale x 16 x i64> @vp_cttz_zero_undef_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv16i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v24, v8, 0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: li a1, 52
; CHECK-NEXT: li a2, 1023
; CHECK-NEXT: vand.vv v8, v8, v24
; CHECK-NEXT: vrsub.vi v24, v16, 0
; CHECK-NEXT: vand.vv v16, v16, v24
; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: vfcvt.f.xu.v v16, v16
; CHECK-NEXT: vsrl.vx v8, v8, a1
; CHECK-NEXT: vsrl.vx v16, v16, a1
; CHECK-NEXT: vsub.vx v8, v8, a2
; CHECK-NEXT: vsub.vx v16, v16, a2
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: vctz.v v16, v16
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 16 x i64> @llvm.vp.cttz.nxv16i64(<vscale x 16 x i64> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i64> %v
}
define <vscale x 16 x i64> @vp_cttz_zero_undef_nxv16i64_unmasked(<vscale x 16 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv16i64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v24, v8, 0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: li a1, 52
; CHECK-NEXT: li a2, 1023
; CHECK-NEXT: vand.vv v8, v8, v24
; CHECK-NEXT: vrsub.vi v24, v16, 0
; CHECK-NEXT: vand.vv v16, v16, v24
; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: vfcvt.f.xu.v v16, v16
; CHECK-NEXT: vsrl.vx v8, v8, a1
; CHECK-NEXT: vsrl.vx v16, v16, a1
; CHECK-NEXT: vsub.vx v8, v8, a2
; CHECK-NEXT: vsub.vx v16, v16, a2
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i64_unmasked:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: vctz.v v16, v16
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 16 x i64> @llvm.vp.cttz.nxv16i64(<vscale x 16 x i64> %va, i1 true, <vscale x 16 x i1> splat (i1 true), i32 %evl)
ret <vscale x 16 x i64> %v
}
; Test promotion.
define <vscale x 1 x i9> @vp_cttz_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv1i9:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 512
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
; CHECK-NEXT: vor.vx v8, v8, a0
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: vand.vv v8, v8, v9
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
; CHECK-NEXT: vnsrl.wi v8, v9, 23
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv1i9:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: li a0, 512
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
; CHECK-ZVBB-NEXT: vor.vx v8, v8, a0
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 1 x i9> @llvm.vp.cttz.nxv1i9(<vscale x 1 x i9> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i9> %v
}
define <vscale x 1 x i9> @vp_zero_undef_cttz_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_zero_undef_cttz_nxv1i9:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: vand.vv v8, v8, v9
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
; CHECK-NEXT: vnsrl.wi v8, v9, 23
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_zero_undef_cttz_nxv1i9:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 1 x i9> @llvm.vp.cttz.nxv1i9(<vscale x 1 x i9> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i9> %v
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; RV32: {{.*}}
; RV64: {{.*}}