llvm/test/CodeGen/NVPTX/cache-hint-atomics.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --filter "^\s*(?:mov\.b64|ld(?:\.[A-Za-z0-9_:]+)*\.global|st(?:\.[A-Za-z0-9_:]+)*\.global|atom(?:\.[A-Za-z0-9_:]+)*(?:\.global|\.shared)|\.reg \.b128)" --version 6
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_100 -mattr=+ptx88 | FileCheck %s
; RUN: %if ptxas-sm_100 && ptxas-isa-8.8 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_100 -mattr=+ptx88 | %ptxas-verify -arch=sm_100 %}

define i32 @atomic_load_l1_hint(ptr addrspace(1) %p) {
; CHECK-LABEL: atomic_load_l1_hint(
; CHECK:    ld.acquire.sys.global.L1::evict_first.b32 %r1, [%rd1];
  %v = load atomic i32, ptr addrspace(1) %p acquire, align 4, !mem.cache_hint !0
  ret i32 %v
}

define void @atomic_store_l2_cache_policy(ptr addrspace(1) %p, i32 %v) {
; CHECK-LABEL: atomic_store_l2_cache_policy(
; CHECK:    mov.b64 %rd2, 12345;
; CHECK:    st.release.sys.global.L2::cache_hint.b32 [%rd1], %r1, %rd2;
  store atomic i32 %v, ptr addrspace(1) %p release, align 4, !mem.cache_hint !2
  ret void
}

define i32 @atomicrmw_add_l2_cache_policy(ptr addrspace(1) %p, i32 %v) {
; CHECK-LABEL: atomicrmw_add_l2_cache_policy(
; CHECK:    mov.b64 %rd2, 12345;
; CHECK:    atom.relaxed.sys.global.add.L2::cache_hint.u32 %r2, [%rd1], %r1, %rd2;
  %old = atomicrmw add ptr addrspace(1) %p, i32 %v monotonic, align 4, !mem.cache_hint !1
  ret i32 %old
}

; PTX atom only supports L2::cache_hint. Other cache hints must be dropped.
define i32 @atomicrmw_add_drops_unsupported_hints(ptr addrspace(1) %p, i32 %v) {
; CHECK-LABEL: atomicrmw_add_drops_unsupported_hints(
; CHECK:    mov.b64 %rd2, 12345;
; CHECK:    atom.relaxed.sys.global.add.L2::cache_hint.u32 %r2, [%rd1], %r1, %rd2;
  %old = atomicrmw add ptr addrspace(1) %p, i32 %v monotonic, align 4, !mem.cache_hint !3
  ret i32 %old
}

; PTX atom.cas does not have a .level::cache_hint operand.
define i32 @atomicrmw_xchg_l2_cache_policy(ptr addrspace(1) %p) {
; CHECK-LABEL: atomicrmw_xchg_l2_cache_policy(
; CHECK:    mov.b64 %rd2, 12345;
; CHECK:    atom.relaxed.sys.global.exch.L2::cache_hint.b32 %r1, [%rd1], 42, %rd2;
  %old = atomicrmw xchg ptr addrspace(1) %p, i32 42 monotonic, align 4, !mem.cache_hint !1
  ret i32 %old
}

define i32 @cmpxchg_l2_cache_policy(ptr addrspace(1) %p, i32 %cmp, i32 %new) {
; CHECK-LABEL: cmpxchg_l2_cache_policy(
; CHECK:    atom.relaxed.sys.global.cas.b32 %r3, [%rd1], %r1, %r2;
  %pair = cmpxchg ptr addrspace(1) %p, i32 %cmp, i32 %new monotonic monotonic, align 4, !mem.cache_hint !3
  %old = extractvalue { i32, i1 } %pair, 0
  ret i32 %old
}

; L2::cache_hint is not supported on shared memory.
define i32 @atomicrmw_shared_l2_cache_policy(ptr addrspace(3) %p, i32 %v) {
; CHECK-LABEL: atomicrmw_shared_l2_cache_policy(
; CHECK:    atom.relaxed.sys.shared.add.u32 %r2, [%rd1], %r1;
  %old = atomicrmw add ptr addrspace(3) %p, i32 %v monotonic, align 4, !mem.cache_hint !1
  ret i32 %old
}

define i128 @atomicrmw_xchg_l2_cache_policy_b128(ptr addrspace(1) %p, i128 %v) {
; CHECK-LABEL: atomicrmw_xchg_l2_cache_policy_b128(
; CHECK:    mov.b64 %rd2, 12345;
; CHECK:    .reg .b128 amt, dst;
; CHECK:    atom.relaxed.sys.global.exch.L2::cache_hint.b128 dst, [%rd1], amt, %rd2;
  %old = atomicrmw xchg ptr addrspace(1) %p, i128 %v monotonic, align 16, !mem.cache_hint !1
  ret i128 %old
}

!0 = !{i32 0, !10}
!1 = !{i32 0, !11}
!2 = !{i32 1, !11}
!3 = !{i32 0, !12}
!10 = !{!"nvvm.l1_eviction", !"first"}
!11 = !{!"nvvm.l2_cache_hint", i64 12345}
!12 = !{!"nvvm.l1_eviction", !"first", !"nvvm.l2_eviction", !"last", !"nvvm.l2_prefetch_size", !"128B", !"nvvm.l2_cache_hint", i64 12345}