llvm/test/CodeGen/LoongArch/lasx/vec-sext.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx,+lasx %s -o - | FileCheck %s --check-prefixes=CHECK,LA32
; RUN: llc --mtriple=loongarch64 --mattr=+lsx,+lasx %s -o - | FileCheck %s --check-prefixes=CHECK,LA64

define void @load_sext_2i8_to_2i64(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_sext_2i8_to_2i64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    ld.h $a0, $a0, 0
; CHECK-NEXT:    vinsgr2vr.h $vr0, $a0, 0
; CHECK-NEXT:    vext2xv.d.b $xr0, $xr0
; CHECK-NEXT:    vst $vr0, $a1, 0
; CHECK-NEXT:    ret
entry:
  %A = load <2 x i8>, ptr %ptr
  %B = sext <2 x i8> %A to <2 x i64>
  store <2 x i64> %B, ptr %dst
  ret void
}

define void @load_sext_4i8_to_4i32(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_sext_4i8_to_4i32:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    ld.w $a0, $a0, 0
; CHECK-NEXT:    vinsgr2vr.w $vr0, $a0, 0
; CHECK-NEXT:    vext2xv.w.b $xr0, $xr0
; CHECK-NEXT:    vst $vr0, $a1, 0
; CHECK-NEXT:    ret
entry:
  %A = load <4 x i8>, ptr %ptr
  %B = sext <4 x i8> %A to <4 x i32>
  store <4 x i32> %B, ptr %dst
  ret void
}

define void @load_sext_8i8_to_8i16(ptr %ptr, ptr %dst) {
; LA32-LABEL: load_sext_8i8_to_8i16:
; LA32:       # %bb.0: # %entry
; LA32-NEXT:    ld.w $a2, $a0, 0
; LA32-NEXT:    ld.w $a0, $a0, 4
; LA32-NEXT:    vinsgr2vr.w $vr0, $a2, 0
; LA32-NEXT:    vinsgr2vr.w $vr0, $a0, 1
; LA32-NEXT:    vext2xv.h.b $xr0, $xr0
; LA32-NEXT:    vst $vr0, $a1, 0
; LA32-NEXT:    ret
;
; LA64-LABEL: load_sext_8i8_to_8i16:
; LA64:       # %bb.0: # %entry
; LA64-NEXT:    ld.d $a0, $a0, 0
; LA64-NEXT:    vinsgr2vr.d $vr0, $a0, 0
; LA64-NEXT:    vext2xv.h.b $xr0, $xr0
; LA64-NEXT:    vst $vr0, $a1, 0
; LA64-NEXT:    ret
entry:
  %A = load <8 x i8>, ptr %ptr
  %B = sext <8 x i8> %A to <8 x i16>
  store <8 x i16> %B, ptr %dst
  ret void
}

define void @load_sext_2i16_to_2i64(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_sext_2i16_to_2i64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    ld.w $a0, $a0, 0
; CHECK-NEXT:    vinsgr2vr.w $vr0, $a0, 0
; CHECK-NEXT:    vext2xv.d.h $xr0, $xr0
; CHECK-NEXT:    vst $vr0, $a1, 0
; CHECK-NEXT:    ret
entry:
  %A = load <2 x i16>, ptr %ptr
  %B = sext <2 x i16> %A to <2 x i64>
  store <2 x i64> %B, ptr %dst
  ret void
}

define void @load_sext_4i16_to_4i32(ptr %ptr, ptr %dst) {
; LA32-LABEL: load_sext_4i16_to_4i32:
; LA32:       # %bb.0: # %entry
; LA32-NEXT:    ld.w $a2, $a0, 0
; LA32-NEXT:    ld.w $a0, $a0, 4
; LA32-NEXT:    vinsgr2vr.w $vr0, $a2, 0
; LA32-NEXT:    vinsgr2vr.w $vr0, $a0, 1
; LA32-NEXT:    vext2xv.w.h $xr0, $xr0
; LA32-NEXT:    vst $vr0, $a1, 0
; LA32-NEXT:    ret
;
; LA64-LABEL: load_sext_4i16_to_4i32:
; LA64:       # %bb.0: # %entry
; LA64-NEXT:    ld.d $a0, $a0, 0
; LA64-NEXT:    vinsgr2vr.d $vr0, $a0, 0
; LA64-NEXT:    vext2xv.w.h $xr0, $xr0
; LA64-NEXT:    vst $vr0, $a1, 0
; LA64-NEXT:    ret
entry:
  %A = load <4 x i16>, ptr %ptr
  %B = sext <4 x i16> %A to <4 x i32>
  store <4 x i32> %B, ptr %dst
  ret void
}

define void @load_sext_2i32_to_2i64(ptr %ptr, ptr %dst) {
; LA32-LABEL: load_sext_2i32_to_2i64:
; LA32:       # %bb.0: # %entry
; LA32-NEXT:    ld.w $a2, $a0, 0
; LA32-NEXT:    ld.w $a0, $a0, 4
; LA32-NEXT:    vinsgr2vr.w $vr0, $a2, 0
; LA32-NEXT:    vinsgr2vr.w $vr0, $a0, 1
; LA32-NEXT:    vext2xv.d.w $xr0, $xr0
; LA32-NEXT:    vst $vr0, $a1, 0
; LA32-NEXT:    ret
;
; LA64-LABEL: load_sext_2i32_to_2i64:
; LA64:       # %bb.0: # %entry
; LA64-NEXT:    ld.d $a0, $a0, 0
; LA64-NEXT:    vinsgr2vr.d $vr0, $a0, 0
; LA64-NEXT:    vext2xv.d.w $xr0, $xr0
; LA64-NEXT:    vst $vr0, $a1, 0
; LA64-NEXT:    ret
entry:
  %A = load <2 x i32>, ptr %ptr
  %B = sext <2 x i32> %A to <2 x i64>
  store <2 x i64> %B, ptr %dst
  ret void
}

define void @load_sext_16i8_to_16i16(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_sext_16i8_to_16i16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vld $vr0, $a0, 0
; CHECK-NEXT:    vext2xv.h.b $xr0, $xr0
; CHECK-NEXT:    xvst $xr0, $a1, 0
; CHECK-NEXT:    ret
entry:
  %A = load <16 x i8>, ptr %ptr
  %B = sext <16 x i8> %A to <16 x i16>
  store <16 x i16> %B, ptr %dst
  ret void
}

define void @load_sext_16i8_to_16i32(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_sext_16i8_to_16i32:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vld $vr0, $a0, 0
; CHECK-NEXT:    vext2xv.h.b $xr0, $xr0
; CHECK-NEXT:    xvpermi.q $xr1, $xr0, 1
; CHECK-NEXT:    vext2xv.w.h $xr1, $xr1
; CHECK-NEXT:    vext2xv.w.h $xr0, $xr0
; CHECK-NEXT:    xvst $xr0, $a1, 0
; CHECK-NEXT:    xvst $xr1, $a1, 32
; CHECK-NEXT:    ret
entry:
  %A = load <16 x i8>, ptr %ptr
  %B = sext <16 x i8> %A to <16 x i32>
  store <16 x i32> %B, ptr %dst
  ret void
}

define void @load_sext_16i8_to_16i64(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_sext_16i8_to_16i64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vld $vr0, $a0, 0
; CHECK-NEXT:    vext2xv.h.b $xr0, $xr0
; CHECK-NEXT:    xvpermi.q $xr1, $xr0, 1
; CHECK-NEXT:    vext2xv.w.h $xr1, $xr1
; CHECK-NEXT:    xvpermi.q $xr2, $xr1, 1
; CHECK-NEXT:    vext2xv.d.w $xr2, $xr2
; CHECK-NEXT:    vext2xv.w.h $xr0, $xr0
; CHECK-NEXT:    xvpermi.q $xr3, $xr0, 1
; CHECK-NEXT:    vext2xv.d.w $xr3, $xr3
; CHECK-NEXT:    vext2xv.d.w $xr1, $xr1
; CHECK-NEXT:    vext2xv.d.w $xr0, $xr0
; CHECK-NEXT:    xvst $xr0, $a1, 0
; CHECK-NEXT:    xvst $xr1, $a1, 64
; CHECK-NEXT:    xvst $xr3, $a1, 32
; CHECK-NEXT:    xvst $xr2, $a1, 96
; CHECK-NEXT:    ret
entry:
  %A = load <16 x i8>, ptr %ptr
  %B = sext <16 x i8> %A to <16 x i64>
  store <16 x i64> %B, ptr %dst
  ret void
}

define void @load_sext_8i16_to_8i32(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_sext_8i16_to_8i32:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vld $vr0, $a0, 0
; CHECK-NEXT:    vext2xv.w.h $xr0, $xr0
; CHECK-NEXT:    xvst $xr0, $a1, 0
; CHECK-NEXT:    ret
entry:
  %A = load <8 x i16>, ptr %ptr
  %B = sext <8 x i16> %A to <8 x i32>
  store <8 x i32> %B, ptr %dst
  ret void
}

define void @load_sext_8i16_to_8i64(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_sext_8i16_to_8i64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vld $vr0, $a0, 0
; CHECK-NEXT:    vext2xv.w.h $xr0, $xr0
; CHECK-NEXT:    xvpermi.q $xr1, $xr0, 1
; CHECK-NEXT:    vext2xv.d.w $xr1, $xr1
; CHECK-NEXT:    vext2xv.d.w $xr0, $xr0
; CHECK-NEXT:    xvst $xr0, $a1, 0
; CHECK-NEXT:    xvst $xr1, $a1, 32
; CHECK-NEXT:    ret
entry:
  %A = load <8 x i16>, ptr %ptr
  %B = sext <8 x i16> %A to <8 x i64>
  store <8 x i64> %B, ptr %dst
  ret void
}

define void @load_sext_4i32_to_4i64(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_sext_4i32_to_4i64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vld $vr0, $a0, 0
; CHECK-NEXT:    vext2xv.d.w $xr0, $xr0
; CHECK-NEXT:    xvst $xr0, $a1, 0
; CHECK-NEXT:    ret
entry:
  %A = load <4 x i32>, ptr %ptr
  %B = sext <4 x i32> %A to <4 x i64>
  store <4 x i64> %B, ptr %dst
  ret void
}

define void @load_sext_invec_v16i8_to_v2i64(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_sext_invec_v16i8_to_v2i64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vld $vr0, $a0, 0
; CHECK-NEXT:    vext2xv.d.b $xr0, $xr0
; CHECK-NEXT:    vst $vr0, $a1, 0
; CHECK-NEXT:    ret
  %A = load <16 x i8>, ptr %ptr
  %B = shufflevector <16 x i8> %A, <16 x i8> poison,
            <2 x i32> <i32 0, i32 1>
  %C = sext <2 x i8> %B to <2 x i64>
  store <2 x i64> %C, ptr %dst
  ret void
}

define void @load_sext_invec_v8i16_to_v2i64(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_sext_invec_v8i16_to_v2i64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vld $vr0, $a0, 0
; CHECK-NEXT:    vext2xv.d.h $xr0, $xr0
; CHECK-NEXT:    vst $vr0, $a1, 0
; CHECK-NEXT:    ret
  %A = load <8 x i16>, ptr %ptr
  %B = shufflevector <8 x i16> %A, <8 x i16> poison,
            <2 x i32> <i32 0, i32 1>
  %C = sext <2 x i16> %B to <2 x i64>
  store <2 x i64> %C, ptr %dst
  ret void
}

define void @load_sext_invec_v4i32_to_v2i64(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_sext_invec_v4i32_to_v2i64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vld $vr0, $a0, 0
; CHECK-NEXT:    vext2xv.d.w $xr0, $xr0
; CHECK-NEXT:    vst $vr0, $a1, 0
; CHECK-NEXT:    ret
  %A = load <4 x i32>, ptr %ptr
  %B = shufflevector <4 x i32> %A, <4 x i32> poison,
            <2 x i32> <i32 0, i32 1>
  %C = sext <2 x i32> %B to <2 x i64>
  store <2 x i64> %C, ptr %dst
  ret void
}

define void @load_sext_invec_v16i8_to_v4i32(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_sext_invec_v16i8_to_v4i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vld $vr0, $a0, 0
; CHECK-NEXT:    vext2xv.w.b $xr0, $xr0
; CHECK-NEXT:    vst $vr0, $a1, 0
; CHECK-NEXT:    ret
  %A = load <16 x i8>, ptr %ptr
  %B = shufflevector <16 x i8> %A, <16 x i8> poison,
            <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %C = sext <4 x i8> %B to <4 x i32>
  store <4 x i32> %C, ptr %dst
  ret void
}

define void @load_sext_invec_v8i16_to_v4i32(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_sext_invec_v8i16_to_v4i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vld $vr0, $a0, 0
; CHECK-NEXT:    vext2xv.w.h $xr0, $xr0
; CHECK-NEXT:    vst $vr0, $a1, 0
; CHECK-NEXT:    ret
  %A = load <8 x i16>, ptr %ptr
  %B = shufflevector <8 x i16> %A, <8 x i16> poison,
            <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %C = sext <4 x i16> %B to <4 x i32>
  store <4 x i32> %C, ptr %dst
  ret void
}

define void @load_sext_invec_v32i8_to_v4i64(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_sext_invec_v32i8_to_v4i64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xvld $xr0, $a0, 0
; CHECK-NEXT:    vext2xv.d.b $xr0, $xr0
; CHECK-NEXT:    xvst $xr0, $a1, 0
; CHECK-NEXT:    ret
  %A = load <32 x i8>, ptr %ptr
  %B = shufflevector <32 x i8> %A, <32 x i8> poison,
            <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %C = sext <4 x i8> %B to <4 x i64>
  store <4 x i64> %C, ptr %dst
  ret void
}

define void @load_sext_invec_v16i16_to_v4i64(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_sext_invec_v16i16_to_v4i64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xvld $xr0, $a0, 0
; CHECK-NEXT:    vext2xv.d.h $xr0, $xr0
; CHECK-NEXT:    xvst $xr0, $a1, 0
; CHECK-NEXT:    ret
  %A = load <16 x i16>, ptr %ptr
  %B = shufflevector <16 x i16> %A, <16 x i16> poison,
            <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %C = sext <4 x i16> %B to <4 x i64>
  store <4 x i64> %C, ptr %dst
  ret void
}

define void @load_sext_invec_v8i32_to_v4i64(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_sext_invec_v8i32_to_v4i64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vld $vr0, $a0, 0
; CHECK-NEXT:    vext2xv.d.w $xr0, $xr0
; CHECK-NEXT:    xvst $xr0, $a1, 0
; CHECK-NEXT:    ret
  %A = load <8 x i32>, ptr %ptr
  %B = shufflevector <8 x i32> %A, <8 x i32> poison,
            <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %C = sext <4 x i32> %B to <4 x i64>
  store <4 x i64> %C, ptr %dst
  ret void
}

define void @load_sext_invec_v16i8_to_v8i16(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_sext_invec_v16i8_to_v8i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vld $vr0, $a0, 0
; CHECK-NEXT:    vext2xv.h.b $xr0, $xr0
; CHECK-NEXT:    vst $vr0, $a1, 0
; CHECK-NEXT:    ret
  %A = load <16 x i8>, ptr %ptr
  %B = shufflevector <16 x i8> %A, <16 x i8> poison,
            <8 x i32> <i32 0, i32 1, i32 2, i32 3,
                        i32 4, i32 5, i32 6, i32 7>
  %C = sext <8 x i8> %B to <8 x i16>
  store <8 x i16> %C, ptr %dst
  ret void
}

define void @load_sext_invec_v32i8_to_v16i16(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_sext_invec_v32i8_to_v16i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vld $vr0, $a0, 0
; CHECK-NEXT:    vext2xv.h.b $xr0, $xr0
; CHECK-NEXT:    xvst $xr0, $a1, 0
; CHECK-NEXT:    ret
  %A = load <32 x i8>, ptr %ptr
  %B = shufflevector <32 x i8> %A, <32 x i8> poison,
            <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
  %C = sext <16 x i8> %B to <16 x i16>
  store <16 x i16> %C, ptr %dst
  ret void
}

define void @load_sext_invec_v32i8_to_v8i32(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_sext_invec_v32i8_to_v8i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xvld $xr0, $a0, 0
; CHECK-NEXT:    vext2xv.w.b $xr0, $xr0
; CHECK-NEXT:    xvst $xr0, $a1, 0
; CHECK-NEXT:    ret
  %A = load <32 x i8>, ptr %ptr
  %B = shufflevector <32 x i8> %A, <32 x i8> poison,
            <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
  %C = sext <8 x i8> %B to <8 x i32>
  store <8 x i32> %C, ptr %dst
  ret void
}

define void @load_sext_invec_v16i16_to_v8i32(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_sext_invec_v16i16_to_v8i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vld $vr0, $a0, 0
; CHECK-NEXT:    vext2xv.w.h $xr0, $xr0
; CHECK-NEXT:    xvst $xr0, $a1, 0
; CHECK-NEXT:    ret
  %A = load <16 x i16>, ptr %ptr
  %B = shufflevector <16 x i16> %A, <16 x i16> poison,
            <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
  %C = sext <8 x i16> %B to <8 x i32>
  store <8 x i32> %C, ptr %dst
  ret void
}

define void @load_sext_invec_v16i8_to_v8i32(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_sext_invec_v16i8_to_v8i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vld $vr0, $a0, 0
; CHECK-NEXT:    vext2xv.w.b $xr0, $xr0
; CHECK-NEXT:    xvst $xr0, $a1, 0
; CHECK-NEXT:    ret
  %A = load <16 x i8>, ptr %ptr
  %B = shufflevector <16 x i8> %A, <16 x i8> poison,
            <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
  %C = sext <8 x i8> %B to <8 x i32>
  store <8 x i32> %C, ptr %dst
  ret void
}