llvm/test/CodeGen/LoongArch/lasx/vec-reduce-umin.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx %s -o - | FileCheck %s --check-prefixes=CHECK,LA32
; RUN: llc --mtriple=loongarch64 --mattr=+lasx %s -o - | FileCheck %s --check-prefixes=CHECK,LA64

define void @vec_reduce_umin_v32i8(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: vec_reduce_umin_v32i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xvld $xr0, $a0, 0
; CHECK-NEXT:    xvpermi.q $xr1, $xr0, 1
; CHECK-NEXT:    vmin.bu $vr0, $vr0, $vr1
; CHECK-NEXT:    vbsrl.v $vr1, $vr0, 8
; CHECK-NEXT:    vmin.bu $vr0, $vr1, $vr0
; CHECK-NEXT:    vbsrl.v $vr1, $vr0, 4
; CHECK-NEXT:    vmin.bu $vr0, $vr1, $vr0
; CHECK-NEXT:    vbsrl.v $vr1, $vr0, 2
; CHECK-NEXT:    vmin.bu $vr0, $vr1, $vr0
; CHECK-NEXT:    vbsrl.v $vr1, $vr0, 1
; CHECK-NEXT:    vmin.bu $vr0, $vr1, $vr0
; CHECK-NEXT:    vstelm.b $vr0, $a1, 0, 0
; CHECK-NEXT:    ret
  %v = load <32 x i8>, ptr %src
  %res = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> %v)
  store i8 %res, ptr %dst
  ret void
}

define void @vec_reduce_umin_v16i16(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: vec_reduce_umin_v16i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xvld $xr0, $a0, 0
; CHECK-NEXT:    xvpermi.q $xr1, $xr0, 1
; CHECK-NEXT:    vmin.hu $vr0, $vr0, $vr1
; CHECK-NEXT:    vbsrl.v $vr1, $vr0, 8
; CHECK-NEXT:    vmin.hu $vr0, $vr1, $vr0
; CHECK-NEXT:    vbsrl.v $vr1, $vr0, 4
; CHECK-NEXT:    vmin.hu $vr0, $vr1, $vr0
; CHECK-NEXT:    vbsrl.v $vr1, $vr0, 2
; CHECK-NEXT:    vmin.hu $vr0, $vr1, $vr0
; CHECK-NEXT:    vstelm.h $vr0, $a1, 0, 0
; CHECK-NEXT:    ret
  %v = load <16 x i16>, ptr %src
  %res = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> %v)
  store i16 %res, ptr %dst
  ret void
}

define void @vec_reduce_umin_v8i32(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_umin_v8i32:
; LA32:       # %bb.0:
; LA32-NEXT:    xvld $xr0, $a0, 0
; LA32-NEXT:    xvpermi.q $xr1, $xr0, 1
; LA32-NEXT:    vmin.wu $vr0, $vr0, $vr1
; LA32-NEXT:    vbsrl.v $vr1, $vr0, 8
; LA32-NEXT:    vmin.wu $vr0, $vr1, $vr0
; LA32-NEXT:    vbsrl.v $vr1, $vr0, 4
; LA32-NEXT:    vmin.wu $vr0, $vr1, $vr0
; LA32-NEXT:    vpickve2gr.w $a0, $vr0, 0
; LA32-NEXT:    st.w $a0, $a1, 0
; LA32-NEXT:    ret
;
; LA64-LABEL: vec_reduce_umin_v8i32:
; LA64:       # %bb.0:
; LA64-NEXT:    xvld $xr0, $a0, 0
; LA64-NEXT:    xvpermi.q $xr1, $xr0, 1
; LA64-NEXT:    vmin.wu $vr0, $vr0, $vr1
; LA64-NEXT:    vbsrl.v $vr1, $vr0, 8
; LA64-NEXT:    vmin.wu $vr0, $vr1, $vr0
; LA64-NEXT:    vbsrl.v $vr1, $vr0, 4
; LA64-NEXT:    vmin.wu $vr0, $vr1, $vr0
; LA64-NEXT:    vstelm.w $vr0, $a1, 0, 0
; LA64-NEXT:    ret
  %v = load <8 x i32>, ptr %src
  %res = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> %v)
  store i32 %res, ptr %dst
  ret void
}

define void @vec_reduce_umin_v4i64(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_umin_v4i64:
; LA32:       # %bb.0:
; LA32-NEXT:    xvld $xr0, $a0, 0
; LA32-NEXT:    xvpermi.q $xr1, $xr0, 1
; LA32-NEXT:    vmin.du $vr0, $vr0, $vr1
; LA32-NEXT:    vpickve2gr.w $a0, $vr0, 3
; LA32-NEXT:    vpickve2gr.w $a2, $vr0, 1
; LA32-NEXT:    sltu $a3, $a2, $a0
; LA32-NEXT:    xor $a4, $a2, $a0
; LA32-NEXT:    sltui $a4, $a4, 1
; LA32-NEXT:    masknez $a3, $a3, $a4
; LA32-NEXT:    vpickve2gr.w $a5, $vr0, 2
; LA32-NEXT:    vpickve2gr.w $a6, $vr0, 0
; LA32-NEXT:    sltu $a7, $a6, $a5
; LA32-NEXT:    maskeqz $a4, $a7, $a4
; LA32-NEXT:    or $a3, $a4, $a3
; LA32-NEXT:    masknez $a4, $a5, $a3
; LA32-NEXT:    maskeqz $a5, $a6, $a3
; LA32-NEXT:    or $a4, $a5, $a4
; LA32-NEXT:    masknez $a0, $a0, $a3
; LA32-NEXT:    maskeqz $a2, $a2, $a3
; LA32-NEXT:    or $a0, $a2, $a0
; LA32-NEXT:    st.w $a0, $a1, 4
; LA32-NEXT:    st.w $a4, $a1, 0
; LA32-NEXT:    ret
;
; LA64-LABEL: vec_reduce_umin_v4i64:
; LA64:       # %bb.0:
; LA64-NEXT:    xvld $xr0, $a0, 0
; LA64-NEXT:    xvpermi.q $xr1, $xr0, 1
; LA64-NEXT:    vmin.du $vr0, $vr0, $vr1
; LA64-NEXT:    vbsrl.v $vr1, $vr0, 8
; LA64-NEXT:    vmin.du $vr0, $vr1, $vr0
; LA64-NEXT:    vstelm.d $vr0, $a1, 0, 0
; LA64-NEXT:    ret
  %v = load <4 x i64>, ptr %src
  %res = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> %v)
  store i64 %res, ptr %dst
  ret void
}