llvm/test/CodeGen/ARM/vector-interleave-store.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=armv8-none-eabihf -mattr=+neon,+fullfp16 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-IAENABLED
; RUN: llc -mtriple=armv8-none-eabihf -mattr=+neon,+fullfp16 -lower-interleaved-accesses=false -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-IADISABLED

define arm_aapcs_vfpcc void @arm_vector_interleave_idx_st2(ptr %dst, <4 x float> %v0, <4 x float> %v1) {
; CHECK-LABEL: arm_vector_interleave_idx_st2:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    @ kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
; CHECK-NEXT:    @ kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
; CHECK-NEXT:    vst2.32 {d0, d1, d2, d3}, [r0:128]
; CHECK-NEXT:    bx lr
entry:
  %interleave = call <8 x float> @llvm.vector.interleave2.v8f32(<4 x float> %v0, <4 x float> %v1)
  store <8 x float> %interleave, ptr %dst, align 16
  ret void
}

define arm_aapcs_vfpcc void @arm_vector_interleave_idx_st3(ptr %dst, <4 x float> %v0, <4 x float> %v1, <4 x float> %v2) {
; CHECK-LABEL: arm_vector_interleave_idx_st3:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT:    @ kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT:    @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT:    vst3.32 {d0, d2, d4}, [r0:64]!
; CHECK-NEXT:    vst3.32 {d1, d3, d5}, [r0:64]
; CHECK-NEXT:    bx lr
entry:
  %interleave = call <12 x float> @llvm.vector.interleave3.v12f32(<4 x float> %v0, <4 x float> %v1, <4 x float> %v2)
  store <12 x float> %interleave, ptr %dst, align 16
  ret void
}

define arm_aapcs_vfpcc void @arm_vector_interleave_idx_st4(ptr %dst, <4 x float> %v0, <4 x float> %v1, <4 x float> %v2, <4 x float> %v3) {
; CHECK-LABEL: arm_vector_interleave_idx_st4:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    @ kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT:    @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT:    @ kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT:    @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT:    vst4.32 {d0, d2, d4, d6}, [r0:128]!
; CHECK-NEXT:    vst4.32 {d1, d3, d5, d7}, [r0:128]
; CHECK-NEXT:    bx lr
entry:
  %interleave = call <16 x float> @llvm.vector.interleave4.v16f32(<4 x float> %v0, <4 x float> %v1, <4 x float> %v2, <4 x float> %v3)
  store <16 x float> %interleave, ptr %dst, align 16
  ret void
}

define arm_aapcs_vfpcc void @vector_interleave2_v8i8(ptr %dst, <8 x i8> %v0, <8 x i8> %v1) {
; CHECK-LABEL: vector_interleave2_v8i8:
; CHECK:       @ %bb.0:
; CHECK-NEXT:    @ kill: def $d1 killed $d1 killed $q0 def $q0
; CHECK-NEXT:    @ kill: def $d0 killed $d0 killed $q0 def $q0
; CHECK-NEXT:    vst2.8 {d0, d1}, [r0:64]
; CHECK-NEXT:    bx lr
  %interleave = call <16 x i8> @llvm.vector.interleave2.v16i8(<8 x i8> %v0, <8 x i8> %v1)
  store <16 x i8> %interleave, ptr %dst
  ret void
}

define arm_aapcs_vfpcc void @vector_interleave2_v8i16(ptr %dst, <8 x i16> %v0, <8 x i16> %v1) {
; CHECK-LABEL: vector_interleave2_v8i16:
; CHECK:       @ %bb.0:
; CHECK-NEXT:    @ kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
; CHECK-NEXT:    @ kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
; CHECK-NEXT:    vst2.16 {d0, d1, d2, d3}, [r0:256]
; CHECK-NEXT:    bx lr
  %interleave = call <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16> %v0, <8 x i16> %v1)
  store <16 x i16> %interleave, ptr %dst
  ret void
}

define arm_aapcs_vfpcc void @vector_interleave2_v8f16(ptr %dst, <8 x half> %v0, <8 x half> %v1) {
; CHECK-LABEL: vector_interleave2_v8f16:
; CHECK:       @ %bb.0:
; CHECK-NEXT:    @ kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
; CHECK-NEXT:    @ kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
; CHECK-NEXT:    vst2.16 {d0, d1, d2, d3}, [r0:256]
; CHECK-NEXT:    bx lr
  %interleave = call <16 x half> @llvm.vector.interleave2.v16f16(<8 x half> %v0, <8 x half> %v1)
  store <16 x half> %interleave, ptr %dst
  ret void
}

define arm_aapcs_vfpcc void @vector_interleave2_v8i32(ptr %dst, <8 x i32> %v0, <8 x i32> %v1) {
; CHECK-LABEL: vector_interleave2_v8i32:
; CHECK:       @ %bb.0:
; CHECK-NEXT:    @ kill: def $q3 killed $q3 killed $q2_q3 def $q2_q3
; CHECK-NEXT:    vorr q9, q2, q2
; CHECK-NEXT:    vorr q8, q0, q0
; CHECK-NEXT:    vorr q2, q1, q1
; CHECK-NEXT:    vst2.32 {d16, d17, d18, d19}, [r0:256]!
; CHECK-NEXT:    vst2.32 {d4, d5, d6, d7}, [r0:256]
; CHECK-NEXT:    bx lr
  %interleave = call <16 x i32> @llvm.vector.interleave2.v16i32(<8 x i32> %v0, <8 x i32> %v1)
  store <16 x i32> %interleave, ptr %dst
  ret void
}

define arm_aapcs_vfpcc void @vector_interleave2_v3i32(ptr %dst, <3 x i32> %v0, <3 x i32> %v1) {
; CHECK-LABEL: vector_interleave2_v3i32:
; CHECK:       @ %bb.0:
; CHECK-NEXT:    vzip.32 q0, q1
; CHECK-NEXT:    vdup.32 q8, d1[1]
; CHECK-NEXT:    vext.32 q9, q0, q0, #3
; CHECK-NEXT:    vdup.32 d20, d2[1]
; CHECK-NEXT:    vext.32 q8, q9, q8, #1
; CHECK-NEXT:    vdup.32 d21, d2[0]
; CHECK-NEXT:    vst1.32 {d16, d17}, [r0:128]!
; CHECK-NEXT:    vext.32 d18, d21, d20, #1
; CHECK-NEXT:    vstr d18, [r0]
; CHECK-NEXT:    bx lr
  %interleave = call <6 x i32> @llvm.vector.interleave2.v6i32(<3 x i32> %v0, <3 x i32> %v1)
  store <6 x i32> %interleave, ptr %dst
  ret void
}

define arm_aapcs_vfpcc void @vector_interleave2_v8f32(ptr %dst, <8 x float> %v0, <8 x float> %v1) {
; CHECK-LABEL: vector_interleave2_v8f32:
; CHECK:       @ %bb.0:
; CHECK-NEXT:    @ kill: def $q3 killed $q3 killed $q2_q3 def $q2_q3
; CHECK-NEXT:    vorr q9, q2, q2
; CHECK-NEXT:    vorr q8, q0, q0
; CHECK-NEXT:    vorr q2, q1, q1
; CHECK-NEXT:    vst2.32 {d16, d17, d18, d19}, [r0:256]!
; CHECK-NEXT:    vst2.32 {d4, d5, d6, d7}, [r0:256]
; CHECK-NEXT:    bx lr
  %interleave = call <16 x float> @llvm.vector.interleave2.v16f32(<8 x float> %v0, <8 x float> %v1)
  store <16 x float> %interleave, ptr %dst
  ret void
}

define arm_aapcs_vfpcc void @vector_interleave3_v8i8(ptr %dst, <8 x i8> %v0, <8 x i8> %v1, <8 x i8> %v2) {
; CHECK-LABEL: vector_interleave3_v8i8:
; CHECK:       @ %bb.0:
; CHECK-NEXT:    @ kill: def $d2 killed $d2 killed $q0_q1 def $q0_q1
; CHECK-NEXT:    @ kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1
; CHECK-NEXT:    @ kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1
; CHECK-NEXT:    vst3.8 {d0, d1, d2}, [r0:64]
; CHECK-NEXT:    bx lr
  %interleave = call <24 x i8> @llvm.vector.interleave3.v24i8(<8 x i8> %v0, <8 x i8> %v1, <8 x i8> %v2)
  store <24 x i8> %interleave, ptr %dst
  ret void
}

define arm_aapcs_vfpcc void @vector_interleave3_v8i16(ptr %dst, <8 x i16> %v0, <8 x i16> %v1, <8 x i16> %v2) {
; CHECK-LABEL: vector_interleave3_v8i16:
; CHECK:       @ %bb.0:
; CHECK-NEXT:    @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT:    @ kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT:    @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT:    vst3.16 {d0, d2, d4}, [r0:64]!
; CHECK-NEXT:    vst3.16 {d1, d3, d5}, [r0:64]
; CHECK-NEXT:    bx lr
  %interleave = call <24 x i16> @llvm.vector.interleave3.v24i16(<8 x i16> %v0, <8 x i16> %v1, <8 x i16> %v2)
  store <24 x i16> %interleave, ptr %dst
  ret void
}

define arm_aapcs_vfpcc void @vector_interleave3_v8f16(ptr %dst, <8 x half> %v0, <8 x half> %v1, <8 x half> %v2) {
; CHECK-LABEL: vector_interleave3_v8f16:
; CHECK:       @ %bb.0:
; CHECK-NEXT:    @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT:    @ kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT:    @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT:    vst3.16 {d0, d2, d4}, [r0:64]!
; CHECK-NEXT:    vst3.16 {d1, d3, d5}, [r0:64]
; CHECK-NEXT:    bx lr
  %interleave = call <24 x half> @llvm.vector.interleave3.v24f16(<8 x half> %v0, <8 x half> %v1, <8 x half> %v2)
  store <24 x half> %interleave, ptr %dst
  ret void
}

define arm_aapcs_vfpcc void @vector_interleave3_v8i32(ptr %dst, <8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
; CHECK-LABEL: vector_interleave3_v8i32:
; CHECK:       @ %bb.0:
; CHECK-NEXT:    .vsave {d8, d9, d10, d11}
; CHECK-NEXT:    vpush {d8, d9, d10, d11}
; CHECK-NEXT:    @ kill: def $q3 killed $q3 killed $q2_q3_q4_q5 def $q2_q3_q4_q5
; CHECK-NEXT:    vorr q9, q2, q2
; CHECK-NEXT:    add r1, sp, #32
; CHECK-NEXT:    vorr q8, q0, q0
; CHECK-NEXT:    vld1.64 {d20, d21}, [r1]
; CHECK-NEXT:    vorr q2, q1, q1
; CHECK-NEXT:    add r1, sp, #48
; CHECK-NEXT:    vst3.32 {d16, d18, d20}, [r0:64]!
; CHECK-NEXT:    vst3.32 {d17, d19, d21}, [r0:64]!
; CHECK-NEXT:    vld1.64 {d8, d9}, [r1]
; CHECK-NEXT:    vst3.32 {d4, d6, d8}, [r0:64]!
; CHECK-NEXT:    vst3.32 {d5, d7, d9}, [r0:64]
; CHECK-NEXT:    vpop {d8, d9, d10, d11}
; CHECK-NEXT:    bx lr
  %interleave = call <24 x i32> @llvm.vector.interleave3.v24i32(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2)
  store <24 x i32> %interleave, ptr %dst
  ret void
}

define arm_aapcs_vfpcc void @vector_interleave3_v8f32(ptr %dst, <8 x float> %v0, <8 x float> %v1, <8 x float> %v2) {
; CHECK-LABEL: vector_interleave3_v8f32:
; CHECK:       @ %bb.0:
; CHECK-NEXT:    .vsave {d8, d9, d10, d11}
; CHECK-NEXT:    vpush {d8, d9, d10, d11}
; CHECK-NEXT:    @ kill: def $q3 killed $q3 killed $q2_q3_q4_q5 def $q2_q3_q4_q5
; CHECK-NEXT:    vorr q9, q2, q2
; CHECK-NEXT:    add r1, sp, #32
; CHECK-NEXT:    vorr q8, q0, q0
; CHECK-NEXT:    vld1.64 {d20, d21}, [r1]
; CHECK-NEXT:    vorr q2, q1, q1
; CHECK-NEXT:    add r1, sp, #48
; CHECK-NEXT:    vst3.32 {d16, d18, d20}, [r0:64]!
; CHECK-NEXT:    vst3.32 {d17, d19, d21}, [r0:64]!
; CHECK-NEXT:    vld1.64 {d8, d9}, [r1]
; CHECK-NEXT:    vst3.32 {d4, d6, d8}, [r0:64]!
; CHECK-NEXT:    vst3.32 {d5, d7, d9}, [r0:64]
; CHECK-NEXT:    vpop {d8, d9, d10, d11}
; CHECK-NEXT:    bx lr
  %interleave = call <24 x float> @llvm.vector.interleave3.v24f32(<8 x float> %v0, <8 x float> %v1, <8 x float> %v2)
  store <24 x float> %interleave, ptr %dst
  ret void
}

define arm_aapcs_vfpcc void @vector_interleave4_v8i8(ptr %dst, <8 x i8> %v0, <8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3) {
; CHECK-LABEL: vector_interleave4_v8i8:
; CHECK:       @ %bb.0:
; CHECK-NEXT:    @ kill: def $d3 killed $d3 killed $q0_q1 def $q0_q1
; CHECK-NEXT:    @ kill: def $d2 killed $d2 killed $q0_q1 def $q0_q1
; CHECK-NEXT:    @ kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1
; CHECK-NEXT:    @ kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1
; CHECK-NEXT:    vst4.8 {d0, d1, d2, d3}, [r0:256]
; CHECK-NEXT:    bx lr
  %interleave = call <32 x i8> @llvm.vector.interleave4.v32i8(<8 x i8> %v0, <8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3)
  store <32 x i8> %interleave, ptr %dst
  ret void
}

define arm_aapcs_vfpcc void @vector_interleave4_v8i16(ptr %dst, <8 x i16> %v0, <8 x i16> %v1, <8 x i16> %v2, <8 x i16> %v3) {
; CHECK-LABEL: vector_interleave4_v8i16:
; CHECK:       @ %bb.0:
; CHECK-NEXT:    @ kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT:    @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT:    @ kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT:    @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT:    vst4.16 {d0, d2, d4, d6}, [r0:256]!
; CHECK-NEXT:    vst4.16 {d1, d3, d5, d7}, [r0:256]
; CHECK-NEXT:    bx lr
  %interleave = call <32 x i16> @llvm.vector.interleave4.v32i16(<8 x i16> %v0, <8 x i16> %v1, <8 x i16> %v2, <8 x i16> %v3)
  store <32 x i16> %interleave, ptr %dst
  ret void
}

define arm_aapcs_vfpcc void @vector_interleave4_v8f16(ptr %dst, <8 x half> %v0, <8 x half> %v1, <8 x half> %v2, <8 x half> %v3) {
; CHECK-LABEL: vector_interleave4_v8f16:
; CHECK:       @ %bb.0:
; CHECK-NEXT:    @ kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT:    @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT:    @ kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT:    @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT:    vst4.16 {d0, d2, d4, d6}, [r0:256]!
; CHECK-NEXT:    vst4.16 {d1, d3, d5, d7}, [r0:256]
; CHECK-NEXT:    bx lr
  %interleave = call <32 x half> @llvm.vector.interleave4.v32f16(<8 x half> %v0, <8 x half> %v1, <8 x half> %v2, <8 x half> %v3)
  store <32 x half> %interleave, ptr %dst
  ret void
}

define arm_aapcs_vfpcc void @vector_interleave4_v8i32(ptr %dst, <8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, <8 x i32> %v3) {
; CHECK-LABEL: vector_interleave4_v8i32:
; CHECK:       @ %bb.0:
; CHECK-NEXT:    .vsave {d8, d9, d10, d11}
; CHECK-NEXT:    vpush {d8, d9, d10, d11}
; CHECK-NEXT:    @ kill: def $q3 killed $q3 killed $q2_q3_q4_q5 def $q2_q3_q4_q5
; CHECK-NEXT:    vorr q9, q2, q2
; CHECK-NEXT:    add r1, sp, #64
; CHECK-NEXT:    vorr q8, q0, q0
; CHECK-NEXT:    vld1.64 {d22, d23}, [r1]
; CHECK-NEXT:    add r1, sp, #32
; CHECK-NEXT:    vorr q2, q1, q1
; CHECK-NEXT:    vld1.64 {d20, d21}, [r1]
; CHECK-NEXT:    add r1, sp, #80
; CHECK-NEXT:    vst4.32 {d16, d18, d20, d22}, [r0:256]!
; CHECK-NEXT:    vld1.64 {d10, d11}, [r1]
; CHECK-NEXT:    add r1, sp, #48
; CHECK-NEXT:    vst4.32 {d17, d19, d21, d23}, [r0:256]!
; CHECK-NEXT:    vld1.64 {d8, d9}, [r1]
; CHECK-NEXT:    vst4.32 {d4, d6, d8, d10}, [r0:256]!
; CHECK-NEXT:    vst4.32 {d5, d7, d9, d11}, [r0:256]
; CHECK-NEXT:    vpop {d8, d9, d10, d11}
; CHECK-NEXT:    bx lr
  %interleave = call <32 x i32> @llvm.vector.interleave4.v32i32(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, <8 x i32> %v3)
  store <32 x i32> %interleave, ptr %dst
  ret void
}

define arm_aapcs_vfpcc void @vector_interleave4_v8f32(ptr %dst, <8 x float> %v0, <8 x float> %v1, <8 x float> %v2, <8 x float> %v3) {
; CHECK-LABEL: vector_interleave4_v8f32:
; CHECK:       @ %bb.0:
; CHECK-NEXT:    .vsave {d8, d9, d10, d11}
; CHECK-NEXT:    vpush {d8, d9, d10, d11}
; CHECK-NEXT:    @ kill: def $q3 killed $q3 killed $q2_q3_q4_q5 def $q2_q3_q4_q5
; CHECK-NEXT:    vorr q9, q2, q2
; CHECK-NEXT:    add r1, sp, #64
; CHECK-NEXT:    vorr q8, q0, q0
; CHECK-NEXT:    vld1.64 {d22, d23}, [r1]
; CHECK-NEXT:    add r1, sp, #32
; CHECK-NEXT:    vorr q2, q1, q1
; CHECK-NEXT:    vld1.64 {d20, d21}, [r1]
; CHECK-NEXT:    add r1, sp, #80
; CHECK-NEXT:    vst4.32 {d16, d18, d20, d22}, [r0:256]!
; CHECK-NEXT:    vld1.64 {d10, d11}, [r1]
; CHECK-NEXT:    add r1, sp, #48
; CHECK-NEXT:    vst4.32 {d17, d19, d21, d23}, [r0:256]!
; CHECK-NEXT:    vld1.64 {d8, d9}, [r1]
; CHECK-NEXT:    vst4.32 {d4, d6, d8, d10}, [r0:256]!
; CHECK-NEXT:    vst4.32 {d5, d7, d9, d11}, [r0:256]
; CHECK-NEXT:    vpop {d8, d9, d10, d11}
; CHECK-NEXT:    bx lr
  %interleave = call <32 x float> @llvm.vector.interleave4.v32f32(<8 x float> %v0, <8 x float> %v1, <8 x float> %v2, <8 x float> %v3)
  store <32 x float> %interleave, ptr %dst
  ret void
}

;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK-IADISABLED: {{.*}}
; CHECK-IAENABLED: {{.*}}