llvm/test/CodeGen/ARM/longMAC-overflow.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=armv7-eabi %s -o - | FileCheck %s --check-prefix=ARM
; RUN: llc -mtriple=thumbv7-eabi %s -o - | FileCheck %s --check-prefix=THUMB2

define { i64, i1 } @saddo_smlalbb(i64 %acc, i16 %a, i16 %b) {
; ARM-LABEL: saddo_smlalbb:
; ARM:       @ %bb.0: @ %entry
; ARM-NEXT:    smulbb r3, r2, r3
; ARM-NEXT:    mov r2, #0
; ARM-NEXT:    adds r0, r0, r3
; ARM-NEXT:    adcs r1, r1, r3, asr #31
; ARM-NEXT:    movwvs r2, #1
; ARM-NEXT:    bx lr
;
; THUMB2-LABEL: saddo_smlalbb:
; THUMB2:       @ %bb.0: @ %entry
; THUMB2-NEXT:    smulbb r3, r2, r3
; THUMB2-NEXT:    movs r2, #0
; THUMB2-NEXT:    adds r0, r0, r3
; THUMB2-NEXT:    adcs.w r1, r1, r3, asr #31
; THUMB2-NEXT:    it vs
; THUMB2-NEXT:    movvs r2, #1
; THUMB2-NEXT:    bx lr
entry:
  %sext.a = sext i16 %a to i32
  %sext.b = sext i16 %b to i32
  %mul = mul nsw i32 %sext.a, %sext.b
  %sext.mul = sext i32 %mul to i64
  %res = tail call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %acc, i64 %sext.mul)
  ret { i64, i1 } %res
}

define { i64, i1 } @uaddo_smlalbb(i64 %acc, i16 %a, i16 %b) {
; ARM-LABEL: uaddo_smlalbb:
; ARM:       @ %bb.0: @ %entry
; ARM-NEXT:    smulbb r2, r2, r3
; ARM-NEXT:    mov r3, #0
; ARM-NEXT:    adds r0, r0, r2
; ARM-NEXT:    adcs r1, r1, r2, asr #31
; ARM-NEXT:    adc r2, r3, #0
; ARM-NEXT:    bx lr
;
; THUMB2-LABEL: uaddo_smlalbb:
; THUMB2:       @ %bb.0: @ %entry
; THUMB2-NEXT:    smulbb r2, r2, r3
; THUMB2-NEXT:    movs r3, #0
; THUMB2-NEXT:    adds r0, r0, r2
; THUMB2-NEXT:    adcs.w r1, r1, r2, asr #31
; THUMB2-NEXT:    adc r2, r3, #0
; THUMB2-NEXT:    bx lr
entry:
  %sext.a = sext i16 %a to i32
  %sext.b = sext i16 %b to i32
  %mul = mul nsw i32 %sext.a, %sext.b
  %sext.mul = sext i32 %mul to i64
  %res = tail call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %acc, i64 %sext.mul)
  ret { i64, i1 } %res
}

define { i64, i1 } @saddo_smlal(i64 %acc, i32 %a, i32 %b) {
; ARM-LABEL: saddo_smlal:
; ARM:       @ %bb.0: @ %entry
; ARM-NEXT:    smull r3, r12, r2, r3
; ARM-NEXT:    mov r2, #0
; ARM-NEXT:    adds r0, r0, r3
; ARM-NEXT:    adcs r1, r1, r12
; ARM-NEXT:    movwvs r2, #1
; ARM-NEXT:    bx lr
;
; THUMB2-LABEL: saddo_smlal:
; THUMB2:       @ %bb.0: @ %entry
; THUMB2-NEXT:    smull r3, r12, r2, r3
; THUMB2-NEXT:    movs r2, #0
; THUMB2-NEXT:    adds r0, r0, r3
; THUMB2-NEXT:    adcs.w r1, r1, r12
; THUMB2-NEXT:    it vs
; THUMB2-NEXT:    movvs r2, #1
; THUMB2-NEXT:    bx lr
entry:
  %sext.a = sext i32 %a to i64
  %sext.b = sext i32 %b to i64
  %mul = mul nsw i64 %sext.a, %sext.b
  %res = tail call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %acc, i64 %mul)
  ret { i64, i1 } %res
}

define { i64, i1 } @uaddo_umlal(i64 %acc, i32 %a, i32 %b) {
; ARM-LABEL: uaddo_umlal:
; ARM:       @ %bb.0: @ %entry
; ARM-NEXT:    umull r2, r3, r2, r3
; ARM-NEXT:    mov r12, #0
; ARM-NEXT:    adds r0, r0, r2
; ARM-NEXT:    adcs r1, r1, r3
; ARM-NEXT:    adc r2, r12, #0
; ARM-NEXT:    bx lr
;
; THUMB2-LABEL: uaddo_umlal:
; THUMB2:       @ %bb.0: @ %entry
; THUMB2-NEXT:    umull r2, r3, r2, r3
; THUMB2-NEXT:    mov.w r12, #0
; THUMB2-NEXT:    adds r0, r0, r2
; THUMB2-NEXT:    adcs r1, r3
; THUMB2-NEXT:    adc r2, r12, #0
; THUMB2-NEXT:    bx lr
entry:
  %zext.a = zext i32 %a to i64
  %zext.b = zext i32 %b to i64
  %mul = mul nuw i64 %zext.a, %zext.b
  %res = tail call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %acc, i64 %mul)
  ret { i64, i1 } %res
}

define { i64, i1 } @ssubo_smlal(i64 %acc, i32 %a, i32 %b) {
; ARM-LABEL: ssubo_smlal:
; ARM:       @ %bb.0: @ %entry
; ARM-NEXT:    smull r3, r12, r2, r3
; ARM-NEXT:    mov r2, #0
; ARM-NEXT:    subs r0, r0, r3
; ARM-NEXT:    sbcs r1, r1, r12
; ARM-NEXT:    movwvs r2, #1
; ARM-NEXT:    bx lr
;
; THUMB2-LABEL: ssubo_smlal:
; THUMB2:       @ %bb.0: @ %entry
; THUMB2-NEXT:    smull r3, r12, r2, r3
; THUMB2-NEXT:    movs r2, #0
; THUMB2-NEXT:    subs r0, r0, r3
; THUMB2-NEXT:    sbcs.w r1, r1, r12
; THUMB2-NEXT:    it vs
; THUMB2-NEXT:    movvs r2, #1
; THUMB2-NEXT:    bx lr
entry:
  %sext.a = sext i32 %a to i64
  %sext.b = sext i32 %b to i64
  %mul = mul nsw i64 %sext.a, %sext.b
  %res = tail call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 %acc, i64 %mul)
  ret { i64, i1 } %res
}

define { i64, i1 } @uaddo_umaal(i32 %a, i32 %b, i32 %lo, i32 %hi) {
; ARM-LABEL: uaddo_umaal:
; ARM:       @ %bb.0: @ %entry
; ARM-NEXT:    .save {r11, lr}
; ARM-NEXT:    push {r11, lr}
; ARM-NEXT:    mov lr, #0
; ARM-NEXT:    mov r12, #0
; ARM-NEXT:    umlal r2, lr, r0, r1
; ARM-NEXT:    adds r0, r2, r3
; ARM-NEXT:    adcs r1, lr, #0
; ARM-NEXT:    adc r2, r12, #0
; ARM-NEXT:    pop {r11, pc}
;
; THUMB2-LABEL: uaddo_umaal:
; THUMB2:       @ %bb.0: @ %entry
; THUMB2-NEXT:    .save {r7, lr}
; THUMB2-NEXT:    push {r7, lr}
; THUMB2-NEXT:    mov.w lr, #0
; THUMB2-NEXT:    mov.w r12, #0
; THUMB2-NEXT:    umlal r2, lr, r0, r1
; THUMB2-NEXT:    adds r0, r2, r3
; THUMB2-NEXT:    adcs r1, lr, #0
; THUMB2-NEXT:    adc r2, r12, #0
; THUMB2-NEXT:    pop {r7, pc}
entry:
  %zext.a = zext i32 %a to i64
  %zext.b = zext i32 %b to i64
  %mul = mul nuw i64 %zext.a, %zext.b
  %zext.lo = zext i32 %lo to i64
  %add = add nuw i64 %mul, %zext.lo
  %zext.hi = zext i32 %hi to i64
  %res = tail call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %add, i64 %zext.hi)
  ret { i64, i1 } %res
}