llvm/test/CodeGen/AMDGPU/wave-reduce-move-source.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgpu12.50-amd-amdpal -global-isel=0 < %s | FileCheck %s
; RUN: llc -mtriple=amdgpu12.50-amd-amdpal -global-isel=1 < %s | FileCheck %s

; Uniform wave.reduce sources defined by a move of something other than an
; immediate: a register (the uniform lowering of wave.reduce.umin and
; wave.reduce.and), a frame index and a global address.
; gfx1250 with PAL moves the 64-bit address of @gv with one s_mov_b64.

@gv = addrspace(4) global i32 0

define i32 @add_of_umin(i32 inreg %x) {
; CHECK-LABEL: add_of_umin:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT:    s_wait_kmcnt 0x0
; CHECK-NEXT:    s_mov_b32 s1, exec_lo
; CHECK-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; CHECK-NEXT:    s_bcnt1_i32_b32 s1, s1
; CHECK-NEXT:    s_mul_i32 s0, s0, s1
; CHECK-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; CHECK-NEXT:    v_mov_b32_e32 v0, s0
; CHECK-NEXT:    s_set_pc_i64 s[30:31]
  %m = call i32 @llvm.amdgcn.wave.reduce.umin.i32(i32 %x, i32 1)
  %r = call i32 @llvm.amdgcn.wave.reduce.add.i32(i32 %m, i32 1)
  ret i32 %r
}

define i32 @add_frame_index() {
; CHECK-LABEL: add_frame_index:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT:    s_wait_kmcnt 0x0
; CHECK-NEXT:    s_mov_b32 s0, exec_lo
; CHECK-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; CHECK-NEXT:    s_bcnt1_i32_b32 s0, s0
; CHECK-NEXT:    s_mul_i32 s0, s0, s32
; CHECK-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; CHECK-NEXT:    v_mov_b32_e32 v0, s0
; CHECK-NEXT:    s_set_pc_i64 s[30:31]
  %a = alloca i32, align 4, addrspace(5)
  %p = ptrtoint ptr addrspace(5) %a to i32
  %r = call i32 @llvm.amdgcn.wave.reduce.add.i32(i32 %p, i32 1)
  ret i32 %r
}

define i32 @xor_frame_index() {
; CHECK-LABEL: xor_frame_index:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT:    s_wait_kmcnt 0x0
; CHECK-NEXT:    s_mov_b32 s0, exec_lo
; CHECK-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; CHECK-NEXT:    s_bcnt1_i32_b32 s0, s0
; CHECK-NEXT:    s_and_b32 s0, s0, 1
; CHECK-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; CHECK-NEXT:    s_mul_i32 s0, s0, s32
; CHECK-NEXT:    v_mov_b32_e32 v0, s0
; CHECK-NEXT:    s_set_pc_i64 s[30:31]
  %a = alloca i32, align 4, addrspace(5)
  %p = ptrtoint ptr addrspace(5) %a to i32
  %r = call i32 @llvm.amdgcn.wave.reduce.xor.i32(i32 %p, i32 1)
  ret i32 %r
}

define i64 @add_global_address_i64() {
; CHECK-LABEL: add_global_address_i64:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT:    s_wait_kmcnt 0x0
; CHECK-NEXT:    s_mov_b32 s2, exec_lo
; CHECK-NEXT:    s_mov_b64 s[0:1], gv@abs64
; CHECK-NEXT:    s_bcnt1_i32_b32 s2, s2
; CHECK-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
; CHECK-NEXT:    s_mul_hi_u32 s3, s0, s2
; CHECK-NEXT:    s_mul_i32 s1, s1, s2
; CHECK-NEXT:    s_mul_i32 s0, s0, s2
; CHECK-NEXT:    s_add_co_u32 s1, s3, s1
; CHECK-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; CHECK-NEXT:    s_set_pc_i64 s[30:31]
  %p = ptrtoint ptr addrspace(4) @gv to i64
  %r = call i64 @llvm.amdgcn.wave.reduce.add.i64(i64 %p, i32 1)
  ret i64 %r
}

define i64 @sub_of_and_i64(i64 inreg %x) {
; CHECK-LABEL: sub_of_and_i64:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT:    s_wait_kmcnt 0x0
; CHECK-NEXT:    s_mov_b32 s2, exec_lo
; CHECK-NEXT:    s_mov_b64 s[0:1], s[0:1]
; CHECK-NEXT:    s_bcnt1_i32_b32 s2, s2
; CHECK-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; CHECK-NEXT:    s_sub_co_i32 s2, 0, s2
; CHECK-NEXT:    s_ashr_i32 s3, s2, 31
; CHECK-NEXT:    s_mul_hi_u32 s4, s0, s2
; CHECK-NEXT:    s_mul_i32 s1, s1, s2
; CHECK-NEXT:    s_mul_i32 s3, s0, s3
; CHECK-NEXT:    s_add_co_u32 s1, s4, s1
; CHECK-NEXT:    s_mul_i32 s0, s0, s2
; CHECK-NEXT:    s_add_co_u32 s1, s1, s3
; CHECK-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; CHECK-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; CHECK-NEXT:    s_set_pc_i64 s[30:31]
  %m = call i64 @llvm.amdgcn.wave.reduce.and.i64(i64 %x, i32 1)
  %r = call i64 @llvm.amdgcn.wave.reduce.sub.i64(i64 %m, i32 1)
  ret i64 %r
}