llvm/test/CodeGen/AMDGPU/wave-reduce-live-scc.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck %s

; The wave.reduce expansions write SCC: the Iterative loop's compare, and
; s_bcnt1 for a uniform value. A uniform condition that is live across the
; call must not be read from SCC after it.

define amdgpu_kernel void @add_iterative_live_scc(ptr addrspace(1) %out, i32 %a, i32 %b) {
; CHECK-LABEL: add_iterative_live_scc:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2c
; CHECK-NEXT:    s_mov_b64 s[2:3], exec
; CHECK-NEXT:    s_mov_b32 s6, 0
; CHECK-NEXT:  .LBB0_1: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT:    s_ff1_i32_b64 s7, s[2:3]
; CHECK-NEXT:    v_readlane_b32 s8, v0, s7
; CHECK-NEXT:    s_bitset0_b64 s[2:3], s7
; CHECK-NEXT:    s_add_i32 s6, s6, s8
; CHECK-NEXT:    s_cmp_lg_u64 s[2:3], 0
; CHECK-NEXT:    s_cbranch_scc1 .LBB0_1
; CHECK-NEXT:  ; %bb.2:
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    s_cmp_lg_u32 s0, s1
; CHECK-NEXT:    s_cbranch_scc1 .LBB0_4
; CHECK-NEXT:  ; %bb.3: ; %t
; CHECK-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; CHECK-NEXT:    v_mov_b32_e32 v0, s6
; CHECK-NEXT:    v_mov_b32_e32 v1, 0
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    global_store_dword v1, v0, s[0:1]
; CHECK-NEXT:  .LBB0_4: ; %e
; CHECK-NEXT:    s_endpgm
  %id = call i32 @llvm.amdgcn.workitem.id.x()
  %c = icmp eq i32 %a, %b
  %r = call i32 @llvm.amdgcn.wave.reduce.add.i32(i32 %id, i32 1)
  br i1 %c, label %t, label %e

t:
  store i32 %r, ptr addrspace(1) %out
  br label %e

e:
  ret void
}

define amdgpu_kernel void @add_uniform_live_scc(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %u) {
; CHECK-LABEL: add_uniform_live_scc:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x2c
; CHECK-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x24
; CHECK-NEXT:    s_mov_b64 s[4:5], exec
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    s_bcnt1_i32_b64 s3, s[4:5]
; CHECK-NEXT:    v_mov_b32_e32 v0, 0
; CHECK-NEXT:    s_mul_i32 s2, s2, s3
; CHECK-NEXT:    s_cmp_eq_u32 s0, s1
; CHECK-NEXT:    s_cselect_b32 s0, s2, 1
; CHECK-NEXT:    v_mov_b32_e32 v1, s0
; CHECK-NEXT:    global_store_dword v0, v1, s[6:7]
; CHECK-NEXT:    s_endpgm
  %c = icmp eq i32 %a, %b
  %r = call i32 @llvm.amdgcn.wave.reduce.add.i32(i32 %u, i32 0)
  %s = select i1 %c, i32 %r, i32 1
  store i32 %s, ptr addrspace(1) %out
  ret void
}