llvm/test/CodeGen/AMDGPU/vgpr-setreg-pred-block.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=amdgpu-lower-vgpr-encoding -o - %s | FileCheck %s

# All S_SETREG_IMM32_B32(MODE) in the file have size=4(<12) and imm32[12:19]=0.
# This ensures they do not cause the insertion of a S_NOP by default. All
# V_MOV_B32_e32 use src0/dst VGPRs with MSB=1 which triggers the check for a
# S_SETREG_IMM32_B32(MODE) in their block predecessors.

---
name:            implicit_fallthrough_insert_nop
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: implicit_fallthrough_insert_nop
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   S_SETREG_IMM32_B32 5, 6145, implicit-def $mode, implicit $mode
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   S_NOP 0
  ; CHECK-NEXT:   S_SET_VGPR_MSB 65, implicit-def $mode
  ; CHECK-NEXT:   $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    S_SETREG_IMM32_B32 5, 6145, implicit-def $mode, implicit $mode

  bb.1:
    $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    S_ENDPGM 0
...

---
name:            explicit_fallthrough_dont_insert_nop
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: explicit_fallthrough_dont_insert_nop
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   S_SETREG_IMM32_B32 5, 6145, implicit-def $mode, implicit $mode
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   S_SET_VGPR_MSB 65, implicit-def $mode
  ; CHECK-NEXT:   $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    S_SETREG_IMM32_B32 5, 6145, implicit-def $mode, implicit $mode
    S_BRANCH %bb.1

  bb.1:
    $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    S_ENDPGM 0
...

---
name:            vgpr_instr_in_second_position_dont_insert_nop
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: vgpr_instr_in_second_position_dont_insert_nop
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   S_SETREG_IMM32_B32 5, 6145, implicit-def $mode, implicit $mode
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   $sgpr0 = S_MOV_B32 0
  ; CHECK-NEXT:   S_SET_VGPR_MSB 65, implicit-def $mode
  ; CHECK-NEXT:   $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    S_SETREG_IMM32_B32 5, 6145, implicit-def $mode, implicit $mode

  bb.1:
    $sgpr0 = S_MOV_B32 0
    $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    S_ENDPGM 0
...

---
name:            empty_pred_block_insert_nop
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: empty_pred_block_insert_nop
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   S_SETREG_IMM32_B32 5, 6145, implicit-def $mode, implicit $mode
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   DBG_VALUE $noreg
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   S_NOP 0
  ; CHECK-NEXT:   S_SET_VGPR_MSB 65, implicit-def $mode
  ; CHECK-NEXT:   $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    S_SETREG_IMM32_B32 5, 6145, implicit-def $mode, implicit $mode

  bb.1:
    DBG_VALUE $noreg

  bb.2:
    $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    S_ENDPGM 0
...

---
name:            setreg_on_any_pred_insert_nop
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: setreg_on_any_pred_insert_nop
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   S_BRANCH %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   S_SETREG_IMM32_B32 5, 6145, implicit-def $mode, implicit $mode
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   S_NOP 0
  ; CHECK-NEXT:   S_SET_VGPR_MSB 65, implicit-def $mode
  ; CHECK-NEXT:   $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    S_BRANCH %bb.2

  bb.1:
    S_SETREG_IMM32_B32 5, 6145, implicit-def $mode, implicit $mode

  bb.2:
    $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    S_ENDPGM 0
...

---
name:            implicit_fallthrough_coissue_opt_insert_nop
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: implicit_fallthrough_coissue_opt_insert_nop
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   S_SETREG_IMM32_B32 5, 6145, implicit-def $mode, implicit $mode
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   S_NOP 0
  ; CHECK-NEXT:   S_SET_VGPR_MSB 65, implicit-def $mode
  ; CHECK-NEXT:   S_BARRIER_WAIT -1
  ; CHECK-NEXT:   $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    S_SETREG_IMM32_B32 5, 6145, implicit-def $mode, implicit $mode

  bb.1:
    S_BARRIER_WAIT -1
    $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    S_ENDPGM 0
...